1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2017 NVIDIA Corporation
5 * Author: Thierry Reding <treding@nvidia.com>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
15 #include <dt-bindings/gpio/tegra186-gpio.h>
16 #include <dt-bindings/gpio/tegra194-gpio.h>
17 #include <dt-bindings/gpio/tegra234-gpio.h>
18 #include <dt-bindings/gpio/tegra241-gpio.h>
20 /* security registers */
21 #define TEGRA186_GPIO_CTL_SCR 0x0c
22 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
23 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
25 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
27 /* control registers */
28 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
29 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
30 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
35 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
36 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
37 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
38 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
40 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
41 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
43 #define TEGRA186_GPIO_INPUT 0x08
44 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
46 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
47 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
49 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
50 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
52 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
54 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
56 struct tegra_gpio_port {
63 struct tegra186_pin_range {
68 struct tegra_gpio_soc {
69 const struct tegra_gpio_port *ports;
70 unsigned int num_ports;
72 unsigned int instance;
74 unsigned int num_irqs_per_bank;
76 const struct tegra186_pin_range *pin_ranges;
77 unsigned int num_pin_ranges;
82 struct gpio_chip gpio;
87 const struct tegra_gpio_soc *soc;
88 unsigned int num_irqs_per_bank;
89 unsigned int num_banks;
95 static const struct tegra_gpio_port *
96 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
98 unsigned int start = 0, i;
100 for (i = 0; i < gpio->soc->num_ports; i++) {
101 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
103 if (*pin >= start && *pin < start + port->pins) {
114 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
117 const struct tegra_gpio_port *port;
120 port = tegra186_gpio_get_port(gpio, &pin);
124 offset = port->bank * 0x1000 + port->port * 0x200;
126 return gpio->base + offset + pin * 0x20;
129 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
132 struct tegra_gpio *gpio = gpiochip_get_data(chip);
136 base = tegra186_gpio_get_base(gpio, offset);
137 if (WARN_ON(base == NULL))
140 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
141 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
142 return GPIO_LINE_DIRECTION_OUT;
144 return GPIO_LINE_DIRECTION_IN;
147 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
150 struct tegra_gpio *gpio = gpiochip_get_data(chip);
154 base = tegra186_gpio_get_base(gpio, offset);
155 if (WARN_ON(base == NULL))
158 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
159 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
160 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
162 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
163 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
164 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
165 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
170 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
171 unsigned int offset, int level)
173 struct tegra_gpio *gpio = gpiochip_get_data(chip);
177 /* configure output level first */
178 chip->set(chip, offset, level);
180 base = tegra186_gpio_get_base(gpio, offset);
181 if (WARN_ON(base == NULL))
184 /* set the direction */
185 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
186 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
187 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
189 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
190 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
191 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
192 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
197 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
199 struct tegra_gpio *gpio = gpiochip_get_data(chip);
203 base = tegra186_gpio_get_base(gpio, offset);
204 if (WARN_ON(base == NULL))
207 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
208 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
209 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
211 value = readl(base + TEGRA186_GPIO_INPUT);
213 return value & BIT(0);
216 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
219 struct tegra_gpio *gpio = gpiochip_get_data(chip);
223 base = tegra186_gpio_get_base(gpio, offset);
224 if (WARN_ON(base == NULL))
227 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
229 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
231 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
233 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
236 static int tegra186_gpio_set_config(struct gpio_chip *chip,
238 unsigned long config)
240 struct tegra_gpio *gpio = gpiochip_get_data(chip);
244 base = tegra186_gpio_get_base(gpio, offset);
248 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
251 debounce = pinconf_to_config_argument(config);
254 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
257 if (debounce > 255000)
260 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
262 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
263 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
265 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
266 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
267 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
272 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
274 struct tegra_gpio *gpio = gpiochip_get_data(chip);
275 struct pinctrl_dev *pctldev;
276 struct device_node *np;
280 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
283 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
287 pctldev = of_pinctrl_get(np);
290 return -EPROBE_DEFER;
292 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
293 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
294 const char *group = gpio->soc->pin_ranges[i].group;
299 if (port >= gpio->soc->num_ports) {
300 dev_warn(chip->parent, "invalid port %u for %s\n",
305 for (j = 0; j < port; j++)
306 pin += gpio->soc->ports[j].pins;
308 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
316 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
317 const struct of_phandle_args *spec,
320 struct tegra_gpio *gpio = gpiochip_get_data(chip);
321 unsigned int port, pin, i, offset = 0;
323 if (WARN_ON(chip->of_gpio_n_cells < 2))
326 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
329 port = spec->args[0] / 8;
330 pin = spec->args[0] % 8;
332 if (port >= gpio->soc->num_ports) {
333 dev_err(chip->parent, "invalid port number: %u\n", port);
337 for (i = 0; i < port; i++)
338 offset += gpio->soc->ports[i].pins;
341 *flags = spec->args[1];
346 static void tegra186_irq_ack(struct irq_data *data)
348 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
351 base = tegra186_gpio_get_base(gpio, data->hwirq);
352 if (WARN_ON(base == NULL))
355 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
358 static void tegra186_irq_mask(struct irq_data *data)
360 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
364 base = tegra186_gpio_get_base(gpio, data->hwirq);
365 if (WARN_ON(base == NULL))
368 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
369 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
370 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
373 static void tegra186_irq_unmask(struct irq_data *data)
375 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
379 base = tegra186_gpio_get_base(gpio, data->hwirq);
380 if (WARN_ON(base == NULL))
383 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
384 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
385 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
388 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
390 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
394 base = tegra186_gpio_get_base(gpio, data->hwirq);
395 if (WARN_ON(base == NULL))
398 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
399 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
400 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
402 switch (type & IRQ_TYPE_SENSE_MASK) {
406 case IRQ_TYPE_EDGE_RISING:
407 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
408 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
411 case IRQ_TYPE_EDGE_FALLING:
412 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
415 case IRQ_TYPE_EDGE_BOTH:
416 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
419 case IRQ_TYPE_LEVEL_HIGH:
420 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
421 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
424 case IRQ_TYPE_LEVEL_LOW:
425 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
432 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
434 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
435 irq_set_handler_locked(data, handle_level_irq);
437 irq_set_handler_locked(data, handle_edge_irq);
439 if (data->parent_data)
440 return irq_chip_set_type_parent(data, type);
445 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
447 if (data->parent_data)
448 return irq_chip_set_wake_parent(data, on);
453 static void tegra186_gpio_irq(struct irq_desc *desc)
455 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
456 struct irq_domain *domain = gpio->gpio.irq.domain;
457 struct irq_chip *chip = irq_desc_get_chip(desc);
458 unsigned int parent = irq_desc_get_irq(desc);
459 unsigned int i, j, offset = 0;
461 chained_irq_enter(chip, desc);
463 for (i = 0; i < gpio->soc->num_ports; i++) {
464 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
469 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
471 /* skip ports that are not associated with this bank */
472 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
473 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
477 if (j == gpio->num_irqs_per_bank)
480 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
482 for_each_set_bit(pin, &value, port->pins) {
483 int ret = generic_handle_domain_irq(domain, offset + pin);
484 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
488 offset += port->pins;
491 chained_irq_exit(chip, desc);
494 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
495 struct irq_fwspec *fwspec,
496 unsigned long *hwirq,
499 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
500 unsigned int port, pin, i, offset = 0;
502 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
505 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
508 port = fwspec->param[0] / 8;
509 pin = fwspec->param[0] % 8;
511 if (port >= gpio->soc->num_ports)
514 for (i = 0; i < port; i++)
515 offset += gpio->soc->ports[i].pins;
517 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
518 *hwirq = offset + pin;
523 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
524 unsigned int parent_hwirq,
525 unsigned int parent_type)
527 struct tegra_gpio *gpio = gpiochip_get_data(chip);
528 struct irq_fwspec *fwspec;
530 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
534 fwspec->fwnode = chip->irq.parent_domain->fwnode;
535 fwspec->param_count = 3;
536 fwspec->param[0] = gpio->soc->instance;
537 fwspec->param[1] = parent_hwirq;
538 fwspec->param[2] = parent_type;
543 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
546 unsigned int *parent_hwirq,
547 unsigned int *parent_type)
549 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
555 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
558 struct tegra_gpio *gpio = gpiochip_get_data(chip);
561 for (i = 0; i < gpio->soc->num_ports; i++) {
562 if (offset < gpio->soc->ports[i].pins)
565 offset -= gpio->soc->ports[i].pins;
568 return offset + i * 8;
571 static const struct of_device_id tegra186_pmc_of_match[] = {
572 { .compatible = "nvidia,tegra186-pmc" },
573 { .compatible = "nvidia,tegra194-pmc" },
577 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
579 struct device *dev = gpio->gpio.parent;
583 for (i = 0; i < gpio->soc->num_ports; i++) {
584 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
585 unsigned int offset, p = port->port;
588 base = gpio->secure + port->bank * 0x1000 + 0x800;
590 value = readl(base + TEGRA186_GPIO_CTL_SCR);
593 * For controllers that haven't been locked down yet, make
594 * sure to program the default interrupt route mapping.
596 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
597 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
599 * On Tegra194 and later, each pin can be routed to one or more
602 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
603 dev_dbg(dev, "programming default interrupt routing for port %s\n",
606 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
609 * By default we only want to route GPIO pins to IRQ 0. This works
610 * only under the assumption that we're running as the host kernel
611 * and hence all GPIO pins are owned by Linux.
613 * For cases where Linux is the guest OS, the hypervisor will have
614 * to configure the interrupt routing and pass only the valid
615 * interrupts via device tree.
618 value = readl(base + offset);
619 value = BIT(port->pins) - 1;
620 writel(value, base + offset);
627 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
629 struct device *dev = gpio->gpio.parent;
631 if (gpio->num_irq > gpio->num_banks) {
632 if (gpio->num_irq % gpio->num_banks != 0)
636 if (gpio->num_irq < gpio->num_banks)
639 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
641 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
647 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
648 gpio->num_irq, gpio->num_banks);
652 static int tegra186_gpio_probe(struct platform_device *pdev)
654 unsigned int i, j, offset;
655 struct gpio_irq_chip *irq;
656 struct tegra_gpio *gpio;
657 struct device_node *np;
661 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
665 gpio->soc = device_get_match_data(&pdev->dev);
666 gpio->gpio.label = gpio->soc->name;
667 gpio->gpio.parent = &pdev->dev;
669 /* count the number of banks in the controller */
670 for (i = 0; i < gpio->soc->num_ports; i++)
671 if (gpio->soc->ports[i].bank > gpio->num_banks)
672 gpio->num_banks = gpio->soc->ports[i].bank;
676 /* get register apertures */
677 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
678 if (IS_ERR(gpio->secure)) {
679 gpio->secure = devm_platform_ioremap_resource(pdev, 0);
680 if (IS_ERR(gpio->secure))
681 return PTR_ERR(gpio->secure);
684 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
685 if (IS_ERR(gpio->base)) {
686 gpio->base = devm_platform_ioremap_resource(pdev, 1);
687 if (IS_ERR(gpio->base))
688 return PTR_ERR(gpio->base);
691 err = platform_irq_count(pdev);
697 err = tegra186_gpio_irqs_per_bank(gpio);
701 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
706 for (i = 0; i < gpio->num_irq; i++) {
707 err = platform_get_irq(pdev, i);
714 gpio->gpio.request = gpiochip_generic_request;
715 gpio->gpio.free = gpiochip_generic_free;
716 gpio->gpio.get_direction = tegra186_gpio_get_direction;
717 gpio->gpio.direction_input = tegra186_gpio_direction_input;
718 gpio->gpio.direction_output = tegra186_gpio_direction_output;
719 gpio->gpio.get = tegra186_gpio_get;
720 gpio->gpio.set = tegra186_gpio_set;
721 gpio->gpio.set_config = tegra186_gpio_set_config;
722 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
724 gpio->gpio.base = -1;
726 for (i = 0; i < gpio->soc->num_ports; i++)
727 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
729 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
730 sizeof(*names), GFP_KERNEL);
734 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
735 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
738 for (j = 0; j < port->pins; j++) {
739 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
740 "P%s.%02x", port->name, j);
744 names[offset + j] = name;
747 offset += port->pins;
750 gpio->gpio.names = (const char * const *)names;
752 #if defined(CONFIG_OF_GPIO)
753 gpio->gpio.of_gpio_n_cells = 2;
754 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
755 #endif /* CONFIG_OF_GPIO */
757 gpio->intc.name = dev_name(&pdev->dev);
758 gpio->intc.irq_ack = tegra186_irq_ack;
759 gpio->intc.irq_mask = tegra186_irq_mask;
760 gpio->intc.irq_unmask = tegra186_irq_unmask;
761 gpio->intc.irq_set_type = tegra186_irq_set_type;
762 gpio->intc.irq_set_wake = tegra186_irq_set_wake;
764 irq = &gpio->gpio.irq;
765 irq->chip = &gpio->intc;
766 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
767 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
768 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
769 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
770 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
771 irq->handler = handle_simple_irq;
772 irq->default_type = IRQ_TYPE_NONE;
773 irq->parent_handler = tegra186_gpio_irq;
774 irq->parent_handler_data = gpio;
775 irq->num_parents = gpio->num_irq;
778 * To simplify things, use a single interrupt per bank for now. Some
779 * chips support up to 8 interrupts per bank, which can be useful to
780 * distribute the load and decrease the processing latency for GPIOs
781 * but it also requires a more complicated interrupt routing than we
784 if (gpio->num_irqs_per_bank > 1) {
785 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
786 sizeof(*irq->parents), GFP_KERNEL);
790 for (i = 0; i < gpio->num_banks; i++)
791 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
793 irq->num_parents = gpio->num_banks;
795 irq->num_parents = gpio->num_irq;
796 irq->parents = gpio->irq;
799 if (gpio->soc->num_irqs_per_bank > 1)
800 tegra186_gpio_init_route_mapping(gpio);
802 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
804 irq->parent_domain = irq_find_host(np);
807 if (!irq->parent_domain)
808 return -EPROBE_DEFER;
811 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
812 sizeof(*irq->map), GFP_KERNEL);
816 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
817 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
819 for (j = 0; j < port->pins; j++)
820 irq->map[offset + j] = irq->parents[port->bank];
822 offset += port->pins;
825 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
828 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
829 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
836 static const struct tegra_gpio_port tegra186_main_ports[] = {
837 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
838 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
839 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
840 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
841 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
842 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
843 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
844 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
845 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
846 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
847 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
848 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
849 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
850 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
851 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
852 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
853 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
854 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
855 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
856 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
857 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
858 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
859 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
862 static const struct tegra_gpio_soc tegra186_main_soc = {
863 .num_ports = ARRAY_SIZE(tegra186_main_ports),
864 .ports = tegra186_main_ports,
865 .name = "tegra186-gpio",
867 .num_irqs_per_bank = 1,
870 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
871 [TEGRA186_AON_GPIO_PORT_##_name] = { \
878 static const struct tegra_gpio_port tegra186_aon_ports[] = {
879 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
880 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
881 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
882 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
883 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
884 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
885 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
886 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
889 static const struct tegra_gpio_soc tegra186_aon_soc = {
890 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
891 .ports = tegra186_aon_ports,
892 .name = "tegra186-gpio-aon",
894 .num_irqs_per_bank = 1,
897 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
898 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
905 static const struct tegra_gpio_port tegra194_main_ports[] = {
906 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
907 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
908 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
909 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
910 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
911 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
912 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
913 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
914 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
915 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
916 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
917 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
918 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
919 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
920 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
921 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
922 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
923 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
924 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
925 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
926 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
927 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
928 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
929 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
930 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
931 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
932 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
933 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
936 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
937 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
938 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
941 static const struct tegra_gpio_soc tegra194_main_soc = {
942 .num_ports = ARRAY_SIZE(tegra194_main_ports),
943 .ports = tegra194_main_ports,
944 .name = "tegra194-gpio",
946 .num_irqs_per_bank = 8,
947 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
948 .pin_ranges = tegra194_main_pin_ranges,
949 .pinmux = "nvidia,tegra194-pinmux",
952 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
953 [TEGRA194_AON_GPIO_PORT_##_name] = { \
960 static const struct tegra_gpio_port tegra194_aon_ports[] = {
961 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
962 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
963 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
964 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
965 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
968 static const struct tegra_gpio_soc tegra194_aon_soc = {
969 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
970 .ports = tegra194_aon_ports,
971 .name = "tegra194-gpio-aon",
973 .num_irqs_per_bank = 8,
976 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
977 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
984 static const struct tegra_gpio_port tegra234_main_ports[] = {
985 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
986 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
987 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
988 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
989 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
990 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
991 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
992 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
993 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
994 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
995 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
996 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
997 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
998 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
999 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1000 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1001 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1002 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1003 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1004 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1005 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1006 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1007 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1008 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1009 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1012 static const struct tegra_gpio_soc tegra234_main_soc = {
1013 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1014 .ports = tegra234_main_ports,
1015 .name = "tegra234-gpio",
1017 .num_irqs_per_bank = 8,
1020 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1021 [TEGRA234_AON_GPIO_PORT_##_name] = { \
1028 static const struct tegra_gpio_port tegra234_aon_ports[] = {
1029 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1030 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1031 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1032 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1033 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1034 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1037 static const struct tegra_gpio_soc tegra234_aon_soc = {
1038 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1039 .ports = tegra234_aon_ports,
1040 .name = "tegra234-gpio-aon",
1042 .num_irqs_per_bank = 8,
1045 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1046 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
1053 static const struct tegra_gpio_port tegra241_main_ports[] = {
1054 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1055 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1056 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1057 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1058 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1059 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1060 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1061 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1062 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1063 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1064 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1067 static const struct tegra_gpio_soc tegra241_main_soc = {
1068 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1069 .ports = tegra241_main_ports,
1070 .name = "tegra241-gpio",
1074 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1075 [TEGRA241_AON_GPIO_PORT_##_name] = { \
1082 static const struct tegra_gpio_port tegra241_aon_ports[] = {
1083 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1084 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1087 static const struct tegra_gpio_soc tegra241_aon_soc = {
1088 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1089 .ports = tegra241_aon_ports,
1090 .name = "tegra241-gpio-aon",
1094 static const struct of_device_id tegra186_gpio_of_match[] = {
1096 .compatible = "nvidia,tegra186-gpio",
1097 .data = &tegra186_main_soc
1099 .compatible = "nvidia,tegra186-gpio-aon",
1100 .data = &tegra186_aon_soc
1102 .compatible = "nvidia,tegra194-gpio",
1103 .data = &tegra194_main_soc
1105 .compatible = "nvidia,tegra194-gpio-aon",
1106 .data = &tegra194_aon_soc
1108 .compatible = "nvidia,tegra234-gpio",
1109 .data = &tegra234_main_soc
1111 .compatible = "nvidia,tegra234-gpio-aon",
1112 .data = &tegra234_aon_soc
1117 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1119 static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1120 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1121 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1122 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1123 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1124 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1125 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1128 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1130 static struct platform_driver tegra186_gpio_driver = {
1132 .name = "tegra186-gpio",
1133 .of_match_table = tegra186_gpio_of_match,
1134 .acpi_match_table = tegra186_gpio_acpi_match,
1136 .probe = tegra186_gpio_probe,
1138 module_platform_driver(tegra186_gpio_driver);
1140 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1141 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1142 MODULE_LICENSE("GPL v2");