1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCA953x 4/8/16/24/40 bit I/O ports
5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
6 * Copyright (C) 2007 Marvell International Ltd.
8 * Derived from drivers/i2c/chips/pca9539.c
11 #include <linux/acpi.h>
12 #include <linux/bitmap.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_data/pca953x.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
25 #include <asm/unaligned.h>
27 #define PCA953X_INPUT 0x00
28 #define PCA953X_OUTPUT 0x01
29 #define PCA953X_INVERT 0x02
30 #define PCA953X_DIRECTION 0x03
32 #define REG_ADDR_MASK GENMASK(5, 0)
33 #define REG_ADDR_EXT BIT(6)
34 #define REG_ADDR_AI BIT(7)
36 #define PCA957X_IN 0x00
37 #define PCA957X_INVRT 0x01
38 #define PCA957X_BKEN 0x02
39 #define PCA957X_PUPD 0x03
40 #define PCA957X_CFG 0x04
41 #define PCA957X_OUT 0x05
42 #define PCA957X_MSK 0x06
43 #define PCA957X_INTS 0x07
45 #define PCAL953X_OUT_STRENGTH 0x20
46 #define PCAL953X_IN_LATCH 0x22
47 #define PCAL953X_PULL_EN 0x23
48 #define PCAL953X_PULL_SEL 0x24
49 #define PCAL953X_INT_MASK 0x25
50 #define PCAL953X_INT_STAT 0x26
51 #define PCAL953X_OUT_CONF 0x27
53 #define PCAL6524_INT_EDGE 0x28
54 #define PCAL6524_INT_CLR 0x2a
55 #define PCAL6524_IN_STATUS 0x2b
56 #define PCAL6524_OUT_INDCONF 0x2c
57 #define PCAL6524_DEBOUNCE 0x2d
59 #define PCA_GPIO_MASK GENMASK(7, 0)
61 #define PCAL_GPIO_MASK GENMASK(4, 0)
62 #define PCAL_PINCTRL_MASK GENMASK(6, 5)
64 #define PCA_INT BIT(8)
65 #define PCA_PCAL BIT(9)
66 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
67 #define PCA953X_TYPE BIT(12)
68 #define PCA957X_TYPE BIT(13)
69 #define PCA_TYPE_MASK GENMASK(15, 12)
71 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
73 static const struct i2c_device_id pca953x_id[] = {
74 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
75 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
76 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, },
77 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
78 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
79 { "pca9536", 4 | PCA953X_TYPE, },
80 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
81 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
82 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
83 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
84 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
85 { "pca9556", 8 | PCA953X_TYPE, },
86 { "pca9557", 8 | PCA953X_TYPE, },
87 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
88 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
89 { "pca9698", 40 | PCA953X_TYPE, },
91 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
92 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
93 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
94 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
95 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
97 { "max7310", 8 | PCA953X_TYPE, },
98 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
99 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
100 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
101 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
102 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
103 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
104 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
105 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
106 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
107 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
108 { "xra1202", 8 | PCA953X_TYPE },
111 MODULE_DEVICE_TABLE(i2c, pca953x_id);
113 #ifdef CONFIG_GPIO_PCA953X_IRQ
115 #include <linux/dmi.h>
116 #include <linux/gpio.h>
117 #include <linux/list.h>
119 static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
122 * On Intel Galileo Gen 2 board the IRQ pin of one of
123 * the I²C GPIO expanders, which has GpioInt() resource,
124 * is provided as an absolute number instead of being
125 * relative. Since first controller (gpio-sch.c) and
126 * second (gpio-dwapb.c) are at the fixed bases, we may
127 * safely refer to the number in the global space to get
131 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
138 static int pca953x_acpi_get_pin(struct acpi_resource *ares, void *data)
140 struct acpi_resource_gpio *agpio;
143 if (acpi_gpio_get_irq_resource(ares, &agpio))
144 *pin = agpio->pin_table[0];
148 static int pca953x_acpi_find_pin(struct device *dev)
150 struct acpi_device *adev = ACPI_COMPANION(dev);
151 int pin = -ENOENT, ret;
154 ret = acpi_dev_get_resources(adev, &r, pca953x_acpi_get_pin, &pin);
155 acpi_dev_free_resource_list(&r);
162 static inline int pca953x_acpi_find_pin(struct device *dev) { return -ENXIO; }
165 static int pca953x_acpi_get_irq(struct device *dev)
169 pin = pca953x_acpi_find_pin(dev);
173 dev_info(dev, "Applying ACPI interrupt quirk (GPIO %d)\n", pin);
175 if (!gpio_is_valid(pin))
178 ret = gpio_request(pin, "pca953x interrupt");
182 ret = gpio_to_irq(pin);
184 /* When pin is used as an IRQ, no need to keep it requested */
191 static const struct acpi_device_id pca953x_acpi_ids[] = {
192 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
195 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
199 #define MAX_LINE (MAX_BANK * BANK_SZ)
201 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
203 struct pca953x_reg_config {
210 static const struct pca953x_reg_config pca953x_regs = {
211 .direction = PCA953X_DIRECTION,
212 .output = PCA953X_OUTPUT,
213 .input = PCA953X_INPUT,
214 .invert = PCA953X_INVERT,
217 static const struct pca953x_reg_config pca957x_regs = {
218 .direction = PCA957X_CFG,
219 .output = PCA957X_OUT,
221 .invert = PCA957X_INVRT,
224 struct pca953x_chip {
226 struct mutex i2c_lock;
227 struct regmap *regmap;
229 #ifdef CONFIG_GPIO_PCA953X_IRQ
230 struct mutex irq_lock;
231 DECLARE_BITMAP(irq_mask, MAX_LINE);
232 DECLARE_BITMAP(irq_stat, MAX_LINE);
233 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
234 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
235 struct irq_chip irq_chip;
237 atomic_t wakeup_path;
239 struct i2c_client *client;
240 struct gpio_chip gpio_chip;
241 const char *const *names;
242 unsigned long driver_data;
243 struct regulator *regulator;
245 const struct pca953x_reg_config *regs;
248 static int pca953x_bank_shift(struct pca953x_chip *chip)
250 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
253 #define PCA953x_BANK_INPUT BIT(0)
254 #define PCA953x_BANK_OUTPUT BIT(1)
255 #define PCA953x_BANK_POLARITY BIT(2)
256 #define PCA953x_BANK_CONFIG BIT(3)
258 #define PCA957x_BANK_INPUT BIT(0)
259 #define PCA957x_BANK_POLARITY BIT(1)
260 #define PCA957x_BANK_BUSHOLD BIT(2)
261 #define PCA957x_BANK_CONFIG BIT(4)
262 #define PCA957x_BANK_OUTPUT BIT(5)
264 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
265 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
266 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
267 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
268 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
271 * We care about the following registers:
272 * - Standard set, below 0x40, each port can be replicated up to 8 times
274 * Input port 0x00 + 0 * bank_size R
275 * Output port 0x00 + 1 * bank_size RW
276 * Polarity Inversion port 0x00 + 2 * bank_size RW
277 * Configuration port 0x00 + 3 * bank_size RW
278 * - PCA957x with mixed up registers
279 * Input port 0x00 + 0 * bank_size R
280 * Polarity Inversion port 0x00 + 1 * bank_size RW
281 * Bus hold port 0x00 + 2 * bank_size RW
282 * Configuration port 0x00 + 4 * bank_size RW
283 * Output port 0x00 + 5 * bank_size RW
285 * - Extended set, above 0x40, often chip specific.
286 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
287 * Input latch register 0x40 + 2 * bank_size RW
288 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
289 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
290 * Interrupt mask register 0x40 + 5 * bank_size RW
291 * Interrupt status register 0x40 + 6 * bank_size R
293 * - Registers with bit 0x80 set, the AI bit
294 * The bit is cleared and the registers fall into one of the
298 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
301 int bank_shift = pca953x_bank_shift(chip);
302 int bank = (reg & REG_ADDR_MASK) >> bank_shift;
303 int offset = reg & (BIT(bank_shift) - 1);
305 /* Special PCAL extended register check. */
306 if (reg & REG_ADDR_EXT) {
307 if (!(chip->driver_data & PCA_PCAL))
312 /* Register is not in the matching bank. */
313 if (!(BIT(bank) & checkbank))
316 /* Register is not within allowed range of bank. */
317 if (offset >= NBANK(chip))
323 static bool pca953x_readable_register(struct device *dev, unsigned int reg)
325 struct pca953x_chip *chip = dev_get_drvdata(dev);
328 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
329 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
330 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
332 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
333 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
334 PCA957x_BANK_BUSHOLD;
337 if (chip->driver_data & PCA_PCAL) {
338 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
339 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
340 PCAL9xxx_BANK_IRQ_STAT;
343 return pca953x_check_register(chip, reg, bank);
346 static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
348 struct pca953x_chip *chip = dev_get_drvdata(dev);
351 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
352 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
355 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
356 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
359 if (chip->driver_data & PCA_PCAL)
360 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
361 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
363 return pca953x_check_register(chip, reg, bank);
366 static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
368 struct pca953x_chip *chip = dev_get_drvdata(dev);
371 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
372 bank = PCA953x_BANK_INPUT;
374 bank = PCA957x_BANK_INPUT;
376 if (chip->driver_data & PCA_PCAL)
377 bank |= PCAL9xxx_BANK_IRQ_STAT;
379 return pca953x_check_register(chip, reg, bank);
382 static const struct regmap_config pca953x_i2c_regmap = {
386 .readable_reg = pca953x_readable_register,
387 .writeable_reg = pca953x_writeable_register,
388 .volatile_reg = pca953x_volatile_register,
390 .disable_locking = true,
391 .cache_type = REGCACHE_RBTREE,
392 .max_register = 0x7f,
395 static const struct regmap_config pca953x_ai_i2c_regmap = {
399 .read_flag_mask = REG_ADDR_AI,
400 .write_flag_mask = REG_ADDR_AI,
402 .readable_reg = pca953x_readable_register,
403 .writeable_reg = pca953x_writeable_register,
404 .volatile_reg = pca953x_volatile_register,
406 .disable_locking = true,
407 .cache_type = REGCACHE_RBTREE,
408 .max_register = 0x7f,
411 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
413 int bank_shift = pca953x_bank_shift(chip);
414 int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
415 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
416 u8 regaddr = pinctrl | addr | (off / BANK_SZ);
421 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
423 u8 regaddr = pca953x_recalc_addr(chip, reg, 0);
427 for (i = 0; i < NBANK(chip); i++)
428 value[i] = bitmap_get_value8(val, i * BANK_SZ);
430 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
432 dev_err(&chip->client->dev, "failed writing register\n");
439 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
441 u8 regaddr = pca953x_recalc_addr(chip, reg, 0);
445 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
447 dev_err(&chip->client->dev, "failed reading register\n");
451 for (i = 0; i < NBANK(chip); i++)
452 bitmap_set_value8(val, value[i], i * BANK_SZ);
457 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
459 struct pca953x_chip *chip = gpiochip_get_data(gc);
460 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
461 u8 bit = BIT(off % BANK_SZ);
464 mutex_lock(&chip->i2c_lock);
465 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
466 mutex_unlock(&chip->i2c_lock);
470 static int pca953x_gpio_direction_output(struct gpio_chip *gc,
471 unsigned off, int val)
473 struct pca953x_chip *chip = gpiochip_get_data(gc);
474 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
475 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off);
476 u8 bit = BIT(off % BANK_SZ);
479 mutex_lock(&chip->i2c_lock);
480 /* set output level */
481 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
486 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
488 mutex_unlock(&chip->i2c_lock);
492 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
494 struct pca953x_chip *chip = gpiochip_get_data(gc);
495 u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off);
496 u8 bit = BIT(off % BANK_SZ);
500 mutex_lock(&chip->i2c_lock);
501 ret = regmap_read(chip->regmap, inreg, ®_val);
502 mutex_unlock(&chip->i2c_lock);
506 * diagnostic already emitted; that's all we should
507 * do unless gpio_*_value_cansleep() calls become different
508 * from their nonsleeping siblings (and report faults).
513 return !!(reg_val & bit);
516 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
518 struct pca953x_chip *chip = gpiochip_get_data(gc);
519 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off);
520 u8 bit = BIT(off % BANK_SZ);
522 mutex_lock(&chip->i2c_lock);
523 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
524 mutex_unlock(&chip->i2c_lock);
527 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
529 struct pca953x_chip *chip = gpiochip_get_data(gc);
530 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off);
531 u8 bit = BIT(off % BANK_SZ);
535 mutex_lock(&chip->i2c_lock);
536 ret = regmap_read(chip->regmap, dirreg, ®_val);
537 mutex_unlock(&chip->i2c_lock);
542 return GPIO_LINE_DIRECTION_IN;
544 return GPIO_LINE_DIRECTION_OUT;
547 static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
548 unsigned long *mask, unsigned long *bits)
550 struct pca953x_chip *chip = gpiochip_get_data(gc);
551 DECLARE_BITMAP(reg_val, MAX_LINE);
554 mutex_lock(&chip->i2c_lock);
555 ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
556 mutex_unlock(&chip->i2c_lock);
560 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
564 static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
565 unsigned long *mask, unsigned long *bits)
567 struct pca953x_chip *chip = gpiochip_get_data(gc);
568 DECLARE_BITMAP(reg_val, MAX_LINE);
571 mutex_lock(&chip->i2c_lock);
572 ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
576 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio);
578 pca953x_write_regs(chip, chip->regs->output, reg_val);
580 mutex_unlock(&chip->i2c_lock);
583 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
585 unsigned long config)
587 u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset);
588 u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset);
589 u8 bit = BIT(offset % BANK_SZ);
593 * pull-up/pull-down configuration requires PCAL extended
596 if (!(chip->driver_data & PCA_PCAL))
599 mutex_lock(&chip->i2c_lock);
601 /* Disable pull-up/pull-down */
602 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
606 /* Configure pull-up/pull-down */
607 if (config == PIN_CONFIG_BIAS_PULL_UP)
608 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
609 else if (config == PIN_CONFIG_BIAS_PULL_DOWN)
610 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
614 /* Enable pull-up/pull-down */
615 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
618 mutex_unlock(&chip->i2c_lock);
622 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
623 unsigned long config)
625 struct pca953x_chip *chip = gpiochip_get_data(gc);
627 switch (pinconf_to_config_param(config)) {
628 case PIN_CONFIG_BIAS_PULL_UP:
629 case PIN_CONFIG_BIAS_PULL_DOWN:
630 return pca953x_gpio_set_pull_up_down(chip, offset, config);
636 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
638 struct gpio_chip *gc;
640 gc = &chip->gpio_chip;
642 gc->direction_input = pca953x_gpio_direction_input;
643 gc->direction_output = pca953x_gpio_direction_output;
644 gc->get = pca953x_gpio_get_value;
645 gc->set = pca953x_gpio_set_value;
646 gc->get_direction = pca953x_gpio_get_direction;
647 gc->get_multiple = pca953x_gpio_get_multiple;
648 gc->set_multiple = pca953x_gpio_set_multiple;
649 gc->set_config = pca953x_gpio_set_config;
650 gc->can_sleep = true;
652 gc->base = chip->gpio_start;
654 gc->label = dev_name(&chip->client->dev);
655 gc->parent = &chip->client->dev;
656 gc->owner = THIS_MODULE;
657 gc->names = chip->names;
660 #ifdef CONFIG_GPIO_PCA953X_IRQ
661 static void pca953x_irq_mask(struct irq_data *d)
663 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
664 struct pca953x_chip *chip = gpiochip_get_data(gc);
665 irq_hw_number_t hwirq = irqd_to_hwirq(d);
667 clear_bit(hwirq, chip->irq_mask);
670 static void pca953x_irq_unmask(struct irq_data *d)
672 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
673 struct pca953x_chip *chip = gpiochip_get_data(gc);
674 irq_hw_number_t hwirq = irqd_to_hwirq(d);
676 set_bit(hwirq, chip->irq_mask);
679 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
681 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
682 struct pca953x_chip *chip = gpiochip_get_data(gc);
685 atomic_inc(&chip->wakeup_path);
687 atomic_dec(&chip->wakeup_path);
689 return irq_set_irq_wake(chip->client->irq, on);
692 static void pca953x_irq_bus_lock(struct irq_data *d)
694 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
695 struct pca953x_chip *chip = gpiochip_get_data(gc);
697 mutex_lock(&chip->irq_lock);
700 static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
702 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
703 struct pca953x_chip *chip = gpiochip_get_data(gc);
704 DECLARE_BITMAP(irq_mask, MAX_LINE);
705 DECLARE_BITMAP(reg_direction, MAX_LINE);
708 if (chip->driver_data & PCA_PCAL) {
709 /* Enable latch on interrupt-enabled inputs */
710 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
712 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
714 /* Unmask enabled interrupts */
715 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask);
718 /* Switch direction to input if needed */
719 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
721 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
722 bitmap_complement(reg_direction, reg_direction, gc->ngpio);
723 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
725 /* Look for any newly setup interrupt */
726 for_each_set_bit(level, irq_mask, gc->ngpio)
727 pca953x_gpio_direction_input(&chip->gpio_chip, level);
729 mutex_unlock(&chip->irq_lock);
732 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
734 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
735 struct pca953x_chip *chip = gpiochip_get_data(gc);
736 irq_hw_number_t hwirq = irqd_to_hwirq(d);
738 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
739 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
744 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
745 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
750 static void pca953x_irq_shutdown(struct irq_data *d)
752 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
753 struct pca953x_chip *chip = gpiochip_get_data(gc);
754 irq_hw_number_t hwirq = irqd_to_hwirq(d);
756 clear_bit(hwirq, chip->irq_trig_raise);
757 clear_bit(hwirq, chip->irq_trig_fall);
760 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
762 struct gpio_chip *gc = &chip->gpio_chip;
763 DECLARE_BITMAP(reg_direction, MAX_LINE);
764 DECLARE_BITMAP(old_stat, MAX_LINE);
765 DECLARE_BITMAP(cur_stat, MAX_LINE);
766 DECLARE_BITMAP(new_stat, MAX_LINE);
767 DECLARE_BITMAP(trigger, MAX_LINE);
770 if (chip->driver_data & PCA_PCAL) {
771 /* Read the current interrupt status from the device */
772 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
776 /* Check latched inputs and clear interrupt status */
777 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
781 /* Apply filter for rising/falling edge selection */
782 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
784 bitmap_and(pending, new_stat, trigger, gc->ngpio);
786 return !bitmap_empty(pending, gc->ngpio);
789 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
793 /* Remove output pins from the equation */
794 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
796 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
798 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio);
799 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio);
800 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
802 if (bitmap_empty(trigger, gc->ngpio))
805 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
807 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
808 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
809 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio);
810 bitmap_and(pending, new_stat, trigger, gc->ngpio);
812 return !bitmap_empty(pending, gc->ngpio);
815 static irqreturn_t pca953x_irq_handler(int irq, void *devid)
817 struct pca953x_chip *chip = devid;
818 struct gpio_chip *gc = &chip->gpio_chip;
819 DECLARE_BITMAP(pending, MAX_LINE);
823 bitmap_zero(pending, MAX_LINE);
825 mutex_lock(&chip->i2c_lock);
826 ret = pca953x_irq_pending(chip, pending);
827 mutex_unlock(&chip->i2c_lock);
832 for_each_set_bit(level, pending, gc->ngpio) {
833 int nested_irq = irq_find_mapping(gc->irq.domain, level);
835 if (unlikely(nested_irq <= 0)) {
836 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
840 handle_nested_irq(nested_irq);
845 return IRQ_RETVAL(ret);
848 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
850 struct i2c_client *client = chip->client;
851 struct irq_chip *irq_chip = &chip->irq_chip;
852 DECLARE_BITMAP(reg_direction, MAX_LINE);
853 DECLARE_BITMAP(irq_stat, MAX_LINE);
854 struct gpio_irq_chip *girq;
857 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) {
858 ret = pca953x_acpi_get_irq(&client->dev);
869 if (!(chip->driver_data & PCA_INT))
872 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
877 * There is no way to know which GPIO line generated the
878 * interrupt. We have to rely on the previous read for
881 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
882 bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio);
883 mutex_init(&chip->irq_lock);
885 irq_chip->name = dev_name(&client->dev);
886 irq_chip->irq_mask = pca953x_irq_mask;
887 irq_chip->irq_unmask = pca953x_irq_unmask;
888 irq_chip->irq_set_wake = pca953x_irq_set_wake;
889 irq_chip->irq_bus_lock = pca953x_irq_bus_lock;
890 irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock;
891 irq_chip->irq_set_type = pca953x_irq_set_type;
892 irq_chip->irq_shutdown = pca953x_irq_shutdown;
894 girq = &chip->gpio_chip.irq;
895 girq->chip = irq_chip;
896 /* This will let us handle the parent IRQ in the driver */
897 girq->parent_handler = NULL;
898 girq->num_parents = 0;
899 girq->parents = NULL;
900 girq->default_type = IRQ_TYPE_NONE;
901 girq->handler = handle_simple_irq;
902 girq->threaded = true;
903 girq->first = irq_base; /* FIXME: get rid of this */
905 ret = devm_request_threaded_irq(&client->dev, client->irq,
906 NULL, pca953x_irq_handler,
907 IRQF_ONESHOT | IRQF_SHARED,
908 dev_name(&client->dev), chip);
910 dev_err(&client->dev, "failed to request irq %d\n",
918 #else /* CONFIG_GPIO_PCA953X_IRQ */
919 static int pca953x_irq_setup(struct pca953x_chip *chip,
922 struct i2c_client *client = chip->client;
924 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
925 dev_warn(&client->dev, "interrupt support not compiled in\n");
931 static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
933 DECLARE_BITMAP(val, MAX_LINE);
936 ret = regcache_sync_region(chip->regmap, chip->regs->output,
937 chip->regs->output + NBANK(chip));
941 ret = regcache_sync_region(chip->regmap, chip->regs->direction,
942 chip->regs->direction + NBANK(chip));
946 /* set platform specific polarity inversion */
948 bitmap_fill(val, MAX_LINE);
950 bitmap_zero(val, MAX_LINE);
952 ret = pca953x_write_regs(chip, chip->regs->invert, val);
957 static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
959 DECLARE_BITMAP(val, MAX_LINE);
963 ret = device_pca95xx_init(chip, invert);
967 /* To enable register 6, 7 to control pull up and pull down */
968 for (i = 0; i < NBANK(chip); i++)
969 bitmap_set_value8(val, 0x02, i * BANK_SZ);
971 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
980 static int pca953x_probe(struct i2c_client *client,
981 const struct i2c_device_id *i2c_id)
983 struct pca953x_platform_data *pdata;
984 struct pca953x_chip *chip;
988 struct regulator *reg;
989 const struct regmap_config *regmap_config;
991 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
995 pdata = dev_get_platdata(&client->dev);
997 irq_base = pdata->irq_base;
998 chip->gpio_start = pdata->gpio_base;
999 invert = pdata->invert;
1000 chip->names = pdata->names;
1002 struct gpio_desc *reset_gpio;
1004 chip->gpio_start = -1;
1008 * See if we need to de-assert a reset pin.
1010 * There is no known ACPI-enabled platforms that are
1011 * using "reset" GPIO. Otherwise any of those platform
1012 * must use _DSD method with corresponding property.
1014 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1016 if (IS_ERR(reset_gpio))
1017 return PTR_ERR(reset_gpio);
1020 chip->client = client;
1022 reg = devm_regulator_get(&client->dev, "vcc");
1024 return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n");
1026 ret = regulator_enable(reg);
1028 dev_err(&client->dev, "reg en err: %d\n", ret);
1031 chip->regulator = reg;
1034 chip->driver_data = i2c_id->driver_data;
1038 match = device_get_match_data(&client->dev);
1044 chip->driver_data = (uintptr_t)match;
1047 i2c_set_clientdata(client, chip);
1049 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
1051 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1052 dev_info(&client->dev, "using AI\n");
1053 regmap_config = &pca953x_ai_i2c_regmap;
1055 dev_info(&client->dev, "using no AI\n");
1056 regmap_config = &pca953x_i2c_regmap;
1059 chip->regmap = devm_regmap_init_i2c(client, regmap_config);
1060 if (IS_ERR(chip->regmap)) {
1061 ret = PTR_ERR(chip->regmap);
1065 regcache_mark_dirty(chip->regmap);
1067 mutex_init(&chip->i2c_lock);
1069 * In case we have an i2c-mux controlled by a GPIO provided by an
1070 * expander using the same driver higher on the device tree, read the
1071 * i2c adapter nesting depth and use the retrieved value as lockdep
1072 * subclass for chip->i2c_lock.
1074 * REVISIT: This solution is not complete. It protects us from lockdep
1075 * false positives when the expander controlling the i2c-mux is on
1076 * a different level on the device tree, but not when it's on the same
1077 * level on a different branch (in which case the subclass number
1078 * would be the same).
1080 * TODO: Once a correct solution is developed, a similar fix should be
1081 * applied to all other i2c-controlled GPIO expanders (and potentially
1084 lockdep_set_subclass(&chip->i2c_lock,
1085 i2c_adapter_depth(client->adapter));
1087 /* initialize cached registers from their original values.
1088 * we can't share this chip with another i2c master.
1091 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
1092 chip->regs = &pca953x_regs;
1093 ret = device_pca95xx_init(chip, invert);
1095 chip->regs = &pca957x_regs;
1096 ret = device_pca957x_init(chip, invert);
1101 ret = pca953x_irq_setup(chip, irq_base);
1105 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
1109 if (pdata && pdata->setup) {
1110 ret = pdata->setup(client, chip->gpio_chip.base,
1111 chip->gpio_chip.ngpio, pdata->context);
1113 dev_warn(&client->dev, "setup failed, %d\n", ret);
1119 regulator_disable(chip->regulator);
1123 static int pca953x_remove(struct i2c_client *client)
1125 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
1126 struct pca953x_chip *chip = i2c_get_clientdata(client);
1129 if (pdata && pdata->teardown) {
1130 ret = pdata->teardown(client, chip->gpio_chip.base,
1131 chip->gpio_chip.ngpio, pdata->context);
1133 dev_err(&client->dev, "teardown failed, %d\n", ret);
1138 regulator_disable(chip->regulator);
1143 #ifdef CONFIG_PM_SLEEP
1144 static int pca953x_regcache_sync(struct device *dev)
1146 struct pca953x_chip *chip = dev_get_drvdata(dev);
1150 * The ordering between direction and output is important,
1151 * sync these registers first and only then sync the rest.
1153 ret = regcache_sync_region(chip->regmap, chip->regs->direction,
1154 chip->regs->direction + NBANK(chip));
1156 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
1160 ret = regcache_sync_region(chip->regmap, chip->regs->output,
1161 chip->regs->output + NBANK(chip));
1163 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
1167 #ifdef CONFIG_GPIO_PCA953X_IRQ
1168 if (chip->driver_data & PCA_PCAL) {
1169 ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH,
1170 PCAL953X_IN_LATCH + NBANK(chip));
1172 dev_err(dev, "Failed to sync INT latch registers: %d\n",
1177 ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK,
1178 PCAL953X_INT_MASK + NBANK(chip));
1180 dev_err(dev, "Failed to sync INT mask registers: %d\n",
1190 static int pca953x_suspend(struct device *dev)
1192 struct pca953x_chip *chip = dev_get_drvdata(dev);
1194 regcache_cache_only(chip->regmap, true);
1196 if (atomic_read(&chip->wakeup_path))
1197 device_set_wakeup_path(dev);
1199 regulator_disable(chip->regulator);
1204 static int pca953x_resume(struct device *dev)
1206 struct pca953x_chip *chip = dev_get_drvdata(dev);
1209 if (!atomic_read(&chip->wakeup_path)) {
1210 ret = regulator_enable(chip->regulator);
1212 dev_err(dev, "Failed to enable regulator: %d\n", ret);
1217 regcache_cache_only(chip->regmap, false);
1218 regcache_mark_dirty(chip->regmap);
1219 ret = pca953x_regcache_sync(dev);
1223 ret = regcache_sync(chip->regmap);
1225 dev_err(dev, "Failed to restore register map: %d\n", ret);
1233 /* convenience to stop overlong match-table lines */
1234 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
1235 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
1237 static const struct of_device_id pca953x_dt_ids[] = {
1238 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
1239 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
1240 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },
1241 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
1242 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
1243 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
1244 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
1245 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
1246 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
1247 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
1248 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
1249 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
1250 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
1251 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
1252 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
1253 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
1255 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1256 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1257 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
1258 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
1259 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1261 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
1262 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
1263 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
1264 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1265 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
1267 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
1268 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1269 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1270 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1271 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1272 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
1274 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
1275 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
1277 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
1281 MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
1283 static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
1285 static struct i2c_driver pca953x_driver = {
1288 .pm = &pca953x_pm_ops,
1289 .of_match_table = pca953x_dt_ids,
1290 .acpi_match_table = pca953x_acpi_ids,
1292 .probe = pca953x_probe,
1293 .remove = pca953x_remove,
1294 .id_table = pca953x_id,
1297 static int __init pca953x_init(void)
1299 return i2c_add_driver(&pca953x_driver);
1301 /* register after i2c postcore initcall and before
1302 * subsys initcalls that may rely on these GPIOs
1304 subsys_initcall(pca953x_init);
1306 static void __exit pca953x_exit(void)
1308 i2c_del_driver(&pca953x_driver);
1310 module_exit(pca953x_exit);
1312 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
1313 MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
1314 MODULE_LICENSE("GPL");