drivers/gpio/gpio-omap.c

   1 /*
   2  * Support functions for OMAP GPIO
   3  *
   4  * Copyright (C) 2003-2005 Nokia Corporation
   5  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   6  *
   7  * Copyright (C) 2009 Texas Instruments
   8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/pm.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/gpio.h>
  28 #include <linux/bitops.h>
  29 #include <linux/platform_data/gpio-omap.h>
  30
  31 #define OFF_MODE        1
  32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
  33
  34 static LIST_HEAD(omap_gpio_list);
  35
  36 struct gpio_regs {
  37         u32 irqenable1;
  38         u32 irqenable2;
  39         u32 wake_en;
  40         u32 ctrl;
  41         u32 oe;
  42         u32 leveldetect0;
  43         u32 leveldetect1;
  44         u32 risingdetect;
  45         u32 fallingdetect;
  46         u32 dataout;
  47         u32 debounce;
  48         u32 debounce_en;
  49 };
  50
  51 struct gpio_bank {
  52         struct list_head node;
  53         void __iomem *base;
  54         int irq;
  55         u32 non_wakeup_gpios;
  56         u32 enabled_non_wakeup_gpios;
  57         struct gpio_regs context;
  58         u32 saved_datain;
  59         u32 level_mask;
  60         u32 toggle_mask;
  61         raw_spinlock_t lock;
  62         raw_spinlock_t wa_lock;
  63         struct gpio_chip chip;
  64         struct clk *dbck;
  65         u32 mod_usage;
  66         u32 irq_usage;
  67         u32 dbck_enable_mask;
  68         bool dbck_enabled;
  69         bool is_mpuio;
  70         bool dbck_flag;
  71         bool loses_context;
  72         bool context_valid;
  73         int stride;
  74         u32 width;
  75         int context_loss_count;
  76         int power_mode;
  77         bool workaround_enabled;
  78
  79         void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
  80         int (*get_context_loss_count)(struct device *dev);
  81
  82         struct omap_gpio_reg_offs *regs;
  83 };
  84
  85 #define GPIO_MOD_CTRL_BIT       BIT(0)
  86
  87 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
  88 #define LINE_USED(line, offset) (line & (BIT(offset)))
  89
  90 static void omap_gpio_unmask_irq(struct irq_data *d);
  91
  92 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
  93 {
  94         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  95         return gpiochip_get_data(chip);
  96 }
  97
  98 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
  99                                     int is_input)
 100 {
 101         void __iomem *reg = bank->base;
 102         u32 l;
 103
 104         reg += bank->regs->direction;
 105         l = readl_relaxed(reg);
 106         if (is_input)
 107                 l |= BIT(gpio);
 108         else
 109                 l &= ~(BIT(gpio));
 110         writel_relaxed(l, reg);
 111         bank->context.oe = l;
 112 }
 113
 114
 115 /* set data out value using dedicate set/clear register */
 116 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
 117                                       int enable)
 118 {
 119         void __iomem *reg = bank->base;
 120         u32 l = BIT(offset);
 121
 122         if (enable) {
 123                 reg += bank->regs->set_dataout;
 124                 bank->context.dataout |= l;
 125         } else {
 126                 reg += bank->regs->clr_dataout;
 127                 bank->context.dataout &= ~l;
 128         }
 129
 130         writel_relaxed(l, reg);
 131 }
 132
 133 /* set data out value using mask register */
 134 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
 135                                        int enable)
 136 {
 137         void __iomem *reg = bank->base + bank->regs->dataout;
 138         u32 gpio_bit = BIT(offset);
 139         u32 l;
 140
 141         l = readl_relaxed(reg);
 142         if (enable)
 143                 l |= gpio_bit;
 144         else
 145                 l &= ~gpio_bit;
 146         writel_relaxed(l, reg);
 147         bank->context.dataout = l;
 148 }
 149
 150 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
 151 {
 152         void __iomem *reg = bank->base + bank->regs->datain;
 153
 154         return (readl_relaxed(reg) & (BIT(offset))) != 0;
 155 }
 156
 157 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
 158 {
 159         void __iomem *reg = bank->base + bank->regs->dataout;
 160
 161         return (readl_relaxed(reg) & (BIT(offset))) != 0;
 162 }
 163
 164 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
 165 {
 166         int l = readl_relaxed(base + reg);
 167
 168         if (set)
 169                 l |= mask;
 170         else
 171                 l &= ~mask;
 172
 173         writel_relaxed(l, base + reg);
 174 }
 175
 176 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
 177 {
 178         if (bank->dbck_enable_mask && !bank->dbck_enabled) {
 179                 clk_enable(bank->dbck);
 180                 bank->dbck_enabled = true;
 181
 182                 writel_relaxed(bank->dbck_enable_mask,
 183                              bank->base + bank->regs->debounce_en);
 184         }
 185 }
 186
 187 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
 188 {
 189         if (bank->dbck_enable_mask && bank->dbck_enabled) {
 190                 /*
 191                  * Disable debounce before cutting it's clock. If debounce is
 192                  * enabled but the clock is not, GPIO module seems to be unable
 193                  * to detect events and generate interrupts at least on OMAP3.
 194                  */
 195                 writel_relaxed(0, bank->base + bank->regs->debounce_en);
 196
 197                 clk_disable(bank->dbck);
 198                 bank->dbck_enabled = false;
 199         }
 200 }
 201
 202 /**
 203  * omap2_set_gpio_debounce - low level gpio debounce time
 204  * @bank: the gpio bank we're acting upon
 205  * @offset: the gpio number on this @bank
 206  * @debounce: debounce time to use
 207  *
 208  * OMAP's debounce time is in 31us steps
 209  *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
 210  * so we need to convert and round up to the closest unit.
 211  *
 212  * Return: 0 on success, negative error otherwise.
 213  */
 214 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
 215                                    unsigned debounce)
 216 {
 217         void __iomem            *reg;
 218         u32                     val;
 219         u32                     l;
 220         bool                    enable = !!debounce;
 221
 222         if (!bank->dbck_flag)
 223                 return -ENOTSUPP;
 224
 225         if (enable) {
 226                 debounce = DIV_ROUND_UP(debounce, 31) - 1;
 227                 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
 228                         return -EINVAL;
 229         }
 230
 231         l = BIT(offset);
 232
 233         clk_enable(bank->dbck);
 234         reg = bank->base + bank->regs->debounce;
 235         writel_relaxed(debounce, reg);
 236
 237         reg = bank->base + bank->regs->debounce_en;
 238         val = readl_relaxed(reg);
 239
 240         if (enable)
 241                 val |= l;
 242         else
 243                 val &= ~l;
 244         bank->dbck_enable_mask = val;
 245
 246         writel_relaxed(val, reg);
 247         clk_disable(bank->dbck);
 248         /*
 249          * Enable debounce clock per module.
 250          * This call is mandatory because in omap_gpio_request() when
 251          * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
 252          * runtime callbck fails to turn on dbck because dbck_enable_mask
 253          * used within _gpio_dbck_enable() is still not initialized at
 254          * that point. Therefore we have to enable dbck here.
 255          */
 256         omap_gpio_dbck_enable(bank);
 257         if (bank->dbck_enable_mask) {
 258                 bank->context.debounce = debounce;
 259                 bank->context.debounce_en = val;
 260         }
 261
 262         return 0;
 263 }
 264
 265 /**
 266  * omap_clear_gpio_debounce - clear debounce settings for a gpio
 267  * @bank: the gpio bank we're acting upon
 268  * @offset: the gpio number on this @bank
 269  *
 270  * If a gpio is using debounce, then clear the debounce enable bit and if
 271  * this is the only gpio in this bank using debounce, then clear the debounce
 272  * time too. The debounce clock will also be disabled when calling this function
 273  * if this is the only gpio in the bank using debounce.
 274  */
 275 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
 276 {
 277         u32 gpio_bit = BIT(offset);
 278
 279         if (!bank->dbck_flag)
 280                 return;
 281
 282         if (!(bank->dbck_enable_mask & gpio_bit))
 283                 return;
 284
 285         bank->dbck_enable_mask &= ~gpio_bit;
 286         bank->context.debounce_en &= ~gpio_bit;
 287         writel_relaxed(bank->context.debounce_en,
 288                      bank->base + bank->regs->debounce_en);
 289
 290         if (!bank->dbck_enable_mask) {
 291                 bank->context.debounce = 0;
 292                 writel_relaxed(bank->context.debounce, bank->base +
 293                              bank->regs->debounce);
 294                 clk_disable(bank->dbck);
 295                 bank->dbck_enabled = false;
 296         }
 297 }
 298
 299 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
 300                                                 unsigned trigger)
 301 {
 302         void __iomem *base = bank->base;
 303         u32 gpio_bit = BIT(gpio);
 304
 305         omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
 306                       trigger & IRQ_TYPE_LEVEL_LOW);
 307         omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
 308                       trigger & IRQ_TYPE_LEVEL_HIGH);
 309         omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
 310                       trigger & IRQ_TYPE_EDGE_RISING);
 311         omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
 312                       trigger & IRQ_TYPE_EDGE_FALLING);
 313
 314         bank->context.leveldetect0 =
 315                         readl_relaxed(bank->base + bank->regs->leveldetect0);
 316         bank->context.leveldetect1 =
 317                         readl_relaxed(bank->base + bank->regs->leveldetect1);
 318         bank->context.risingdetect =
 319                         readl_relaxed(bank->base + bank->regs->risingdetect);
 320         bank->context.fallingdetect =
 321                         readl_relaxed(bank->base + bank->regs->fallingdetect);
 322
 323         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 324                 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
 325                 bank->context.wake_en =
 326                         readl_relaxed(bank->base + bank->regs->wkup_en);
 327         }
 328
 329         /* This part needs to be executed always for OMAP{34xx, 44xx} */
 330         if (!bank->regs->irqctrl) {
 331                 /* On omap24xx proceed only when valid GPIO bit is set */
 332                 if (bank->non_wakeup_gpios) {
 333                         if (!(bank->non_wakeup_gpios & gpio_bit))
 334                                 goto exit;
 335                 }
 336
 337                 /*
 338                  * Log the edge gpio and manually trigger the IRQ
 339                  * after resume if the input level changes
 340                  * to avoid irq lost during PER RET/OFF mode
 341                  * Applies for omap2 non-wakeup gpio and all omap3 gpios
 342                  */
 343                 if (trigger & IRQ_TYPE_EDGE_BOTH)
 344                         bank->enabled_non_wakeup_gpios |= gpio_bit;
 345                 else
 346                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 347         }
 348
 349 exit:
 350         bank->level_mask =
 351                 readl_relaxed(bank->base + bank->regs->leveldetect0) |
 352                 readl_relaxed(bank->base + bank->regs->leveldetect1);
 353 }
 354
 355 #ifdef CONFIG_ARCH_OMAP1
 356 /*
 357  * This only applies to chips that can't do both rising and falling edge
 358  * detection at once.  For all other chips, this function is a noop.
 359  */
 360 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 361 {
 362         void __iomem *reg = bank->base;
 363         u32 l = 0;
 364
 365         if (!bank->regs->irqctrl)
 366                 return;
 367
 368         reg += bank->regs->irqctrl;
 369
 370         l = readl_relaxed(reg);
 371         if ((l >> gpio) & 1)
 372                 l &= ~(BIT(gpio));
 373         else
 374                 l |= BIT(gpio);
 375
 376         writel_relaxed(l, reg);
 377 }
 378 #else
 379 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 380 #endif
 381
 382 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
 383                                     unsigned trigger)
 384 {
 385         void __iomem *reg = bank->base;
 386         void __iomem *base = bank->base;
 387         u32 l = 0;
 388
 389         if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
 390                 omap_set_gpio_trigger(bank, gpio, trigger);
 391         } else if (bank->regs->irqctrl) {
 392                 reg += bank->regs->irqctrl;
 393
 394                 l = readl_relaxed(reg);
 395                 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
 396                         bank->toggle_mask |= BIT(gpio);
 397                 if (trigger & IRQ_TYPE_EDGE_RISING)
 398                         l |= BIT(gpio);
 399                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 400                         l &= ~(BIT(gpio));
 401                 else
 402                         return -EINVAL;
 403
 404                 writel_relaxed(l, reg);
 405         } else if (bank->regs->edgectrl1) {
 406                 if (gpio & 0x08)
 407                         reg += bank->regs->edgectrl2;
 408                 else
 409                         reg += bank->regs->edgectrl1;
 410
 411                 gpio &= 0x07;
 412                 l = readl_relaxed(reg);
 413                 l &= ~(3 << (gpio << 1));
 414                 if (trigger & IRQ_TYPE_EDGE_RISING)
 415                         l |= 2 << (gpio << 1);
 416                 if (trigger & IRQ_TYPE_EDGE_FALLING)
 417                         l |= BIT(gpio << 1);
 418
 419                 /* Enable wake-up during idle for dynamic tick */
 420                 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
 421                 bank->context.wake_en =
 422                         readl_relaxed(bank->base + bank->regs->wkup_en);
 423                 writel_relaxed(l, reg);
 424         }
 425         return 0;
 426 }
 427
 428 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
 429 {
 430         if (bank->regs->pinctrl) {
 431                 void __iomem *reg = bank->base + bank->regs->pinctrl;
 432
 433                 /* Claim the pin for MPU */
 434                 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
 435         }
 436
 437         if (bank->regs->ctrl && !BANK_USED(bank)) {
 438                 void __iomem *reg = bank->base + bank->regs->ctrl;
 439                 u32 ctrl;
 440
 441                 ctrl = readl_relaxed(reg);
 442                 /* Module is enabled, clocks are not gated */
 443                 ctrl &= ~GPIO_MOD_CTRL_BIT;
 444                 writel_relaxed(ctrl, reg);
 445                 bank->context.ctrl = ctrl;
 446         }
 447 }
 448
 449 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
 450 {
 451         void __iomem *base = bank->base;
 452
 453         if (bank->regs->wkup_en &&
 454             !LINE_USED(bank->mod_usage, offset) &&
 455             !LINE_USED(bank->irq_usage, offset)) {
 456                 /* Disable wake-up during idle for dynamic tick */
 457                 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
 458                 bank->context.wake_en =
 459                         readl_relaxed(bank->base + bank->regs->wkup_en);
 460         }
 461
 462         if (bank->regs->ctrl && !BANK_USED(bank)) {
 463                 void __iomem *reg = bank->base + bank->regs->ctrl;
 464                 u32 ctrl;
 465
 466                 ctrl = readl_relaxed(reg);
 467                 /* Module is disabled, clocks are gated */
 468                 ctrl |= GPIO_MOD_CTRL_BIT;
 469                 writel_relaxed(ctrl, reg);
 470                 bank->context.ctrl = ctrl;
 471         }
 472 }
 473
 474 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
 475 {
 476         void __iomem *reg = bank->base + bank->regs->direction;
 477
 478         return readl_relaxed(reg) & BIT(offset);
 479 }
 480
 481 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
 482 {
 483         if (!LINE_USED(bank->mod_usage, offset)) {
 484                 omap_enable_gpio_module(bank, offset);
 485                 omap_set_gpio_direction(bank, offset, 1);
 486         }
 487         bank->irq_usage |= BIT(offset);
 488 }
 489
 490 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
 491 {
 492         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 493         int retval;
 494         unsigned long flags;
 495         unsigned offset = d->hwirq;
 496
 497         if (type & ~IRQ_TYPE_SENSE_MASK)
 498                 return -EINVAL;
 499
 500         if (!bank->regs->leveldetect0 &&
 501                 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 502                 return -EINVAL;
 503
 504         raw_spin_lock_irqsave(&bank->lock, flags);
 505         retval = omap_set_gpio_triggering(bank, offset, type);
 506         if (retval) {
 507                 raw_spin_unlock_irqrestore(&bank->lock, flags);
 508                 goto error;
 509         }
 510         omap_gpio_init_irq(bank, offset);
 511         if (!omap_gpio_is_input(bank, offset)) {
 512                 raw_spin_unlock_irqrestore(&bank->lock, flags);
 513                 retval = -EINVAL;
 514                 goto error;
 515         }
 516         raw_spin_unlock_irqrestore(&bank->lock, flags);
 517
 518         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 519                 irq_set_handler_locked(d, handle_level_irq);
 520         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 521                 /*
 522                  * Edge IRQs are already cleared/acked in irq_handler and
 523                  * not need to be masked, as result handle_edge_irq()
 524                  * logic is excessed here and may cause lose of interrupts.
 525                  * So just use handle_simple_irq.
 526                  */
 527                 irq_set_handler_locked(d, handle_simple_irq);
 528
 529         return 0;
 530
 531 error:
 532         return retval;
 533 }
 534
 535 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 536 {
 537         void __iomem *reg = bank->base;
 538
 539         reg += bank->regs->irqstatus;
 540         writel_relaxed(gpio_mask, reg);
 541
 542         /* Workaround for clearing DSP GPIO interrupts to allow retention */
 543         if (bank->regs->irqstatus2) {
 544                 reg = bank->base + bank->regs->irqstatus2;
 545                 writel_relaxed(gpio_mask, reg);
 546         }
 547
 548         /* Flush posted write for the irq status to avoid spurious interrupts */
 549         readl_relaxed(reg);
 550 }
 551
 552 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
 553                                              unsigned offset)
 554 {
 555         omap_clear_gpio_irqbank(bank, BIT(offset));
 556 }
 557
 558 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
 559 {
 560         void __iomem *reg = bank->base;
 561         u32 l;
 562         u32 mask = (BIT(bank->width)) - 1;
 563
 564         reg += bank->regs->irqenable;
 565         l = readl_relaxed(reg);
 566         if (bank->regs->irqenable_inv)
 567                 l = ~l;
 568         l &= mask;
 569         return l;
 570 }
 571
 572 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 573 {
 574         void __iomem *reg = bank->base;
 575         u32 l;
 576
 577         if (bank->regs->set_irqenable) {
 578                 reg += bank->regs->set_irqenable;
 579                 l = gpio_mask;
 580                 bank->context.irqenable1 |= gpio_mask;
 581         } else {
 582                 reg += bank->regs->irqenable;
 583                 l = readl_relaxed(reg);
 584                 if (bank->regs->irqenable_inv)
 585                         l &= ~gpio_mask;
 586                 else
 587                         l |= gpio_mask;
 588                 bank->context.irqenable1 = l;
 589         }
 590
 591         writel_relaxed(l, reg);
 592 }
 593
 594 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 595 {
 596         void __iomem *reg = bank->base;
 597         u32 l;
 598
 599         if (bank->regs->clr_irqenable) {
 600                 reg += bank->regs->clr_irqenable;
 601                 l = gpio_mask;
 602                 bank->context.irqenable1 &= ~gpio_mask;
 603         } else {
 604                 reg += bank->regs->irqenable;
 605                 l = readl_relaxed(reg);
 606                 if (bank->regs->irqenable_inv)
 607                         l |= gpio_mask;
 608                 else
 609                         l &= ~gpio_mask;
 610                 bank->context.irqenable1 = l;
 611         }
 612
 613         writel_relaxed(l, reg);
 614 }
 615
 616 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
 617                                            unsigned offset, int enable)
 618 {
 619         if (enable)
 620                 omap_enable_gpio_irqbank(bank, BIT(offset));
 621         else
 622                 omap_disable_gpio_irqbank(bank, BIT(offset));
 623 }
 624
 625 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
 626 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 627 {
 628         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 629
 630         return irq_set_irq_wake(bank->irq, enable);
 631 }
 632
 633 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 634 {
 635         struct gpio_bank *bank = gpiochip_get_data(chip);
 636         unsigned long flags;
 637
 638         /*
 639          * If this is the first gpio_request for the bank,
 640          * enable the bank module.
 641          */
 642         if (!BANK_USED(bank))
 643                 pm_runtime_get_sync(chip->parent);
 644
 645         raw_spin_lock_irqsave(&bank->lock, flags);
 646         omap_enable_gpio_module(bank, offset);
 647         bank->mod_usage |= BIT(offset);
 648         raw_spin_unlock_irqrestore(&bank->lock, flags);
 649
 650         return 0;
 651 }
 652
 653 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 654 {
 655         struct gpio_bank *bank = gpiochip_get_data(chip);
 656         unsigned long flags;
 657
 658         raw_spin_lock_irqsave(&bank->lock, flags);
 659         bank->mod_usage &= ~(BIT(offset));
 660         if (!LINE_USED(bank->irq_usage, offset)) {
 661                 omap_set_gpio_direction(bank, offset, 1);
 662                 omap_clear_gpio_debounce(bank, offset);
 663         }
 664         omap_disable_gpio_module(bank, offset);
 665         raw_spin_unlock_irqrestore(&bank->lock, flags);
 666
 667         /*
 668          * If this is the last gpio to be freed in the bank,
 669          * disable the bank module.
 670          */
 671         if (!BANK_USED(bank))
 672                 pm_runtime_put(chip->parent);
 673 }
 674
 675 /*
 676  * We need to unmask the GPIO bank interrupt as soon as possible to
 677  * avoid missing GPIO interrupts for other lines in the bank.
 678  * Then we need to mask-read-clear-unmask the triggered GPIO lines
 679  * in the bank to avoid missing nested interrupts for a GPIO line.
 680  * If we wait to unmask individual GPIO lines in the bank after the
 681  * line's interrupt handler has been run, we may miss some nested
 682  * interrupts.
 683  */
 684 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
 685 {
 686         void __iomem *isr_reg = NULL;
 687         u32 enabled, isr, level_mask;
 688         unsigned int bit;
 689         struct gpio_bank *bank = gpiobank;
 690         unsigned long wa_lock_flags;
 691         unsigned long lock_flags;
 692
 693         isr_reg = bank->base + bank->regs->irqstatus;
 694         if (WARN_ON(!isr_reg))
 695                 goto exit;
 696
 697         pm_runtime_get_sync(bank->chip.parent);
 698
 699         while (1) {
 700                 raw_spin_lock_irqsave(&bank->lock, lock_flags);
 701
 702                 enabled = omap_get_gpio_irqbank_mask(bank);
 703                 isr = readl_relaxed(isr_reg) & enabled;
 704
 705                 if (bank->level_mask)
 706                         level_mask = bank->level_mask & enabled;
 707                 else
 708                         level_mask = 0;
 709
 710                 /* clear edge sensitive interrupts before handler(s) are
 711                 called so that we don't miss any interrupt occurred while
 712                 executing them */
 713                 if (isr & ~level_mask)
 714                         omap_clear_gpio_irqbank(bank, isr & ~level_mask);
 715
 716                 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 717
 718                 if (!isr)
 719                         break;
 720
 721                 while (isr) {
 722                         bit = __ffs(isr);
 723                         isr &= ~(BIT(bit));
 724
 725                         raw_spin_lock_irqsave(&bank->lock, lock_flags);
 726                         /*
 727                          * Some chips can't respond to both rising and falling
 728                          * at the same time.  If this irq was requested with
 729                          * both flags, we need to flip the ICR data for the IRQ
 730                          * to respond to the IRQ for the opposite direction.
 731                          * This will be indicated in the bank toggle_mask.
 732                          */
 733                         if (bank->toggle_mask & (BIT(bit)))
 734                                 omap_toggle_gpio_edge_triggering(bank, bit);
 735
 736                         raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 737
 738                         raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
 739
 740                         generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
 741                                                             bit));
 742
 743                         raw_spin_unlock_irqrestore(&bank->wa_lock,
 744                                                    wa_lock_flags);
 745                 }
 746         }
 747 exit:
 748         pm_runtime_put(bank->chip.parent);
 749         return IRQ_HANDLED;
 750 }
 751
 752 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
 753 {
 754         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 755         unsigned long flags;
 756         unsigned offset = d->hwirq;
 757
 758         raw_spin_lock_irqsave(&bank->lock, flags);
 759
 760         if (!LINE_USED(bank->mod_usage, offset))
 761                 omap_set_gpio_direction(bank, offset, 1);
 762         else if (!omap_gpio_is_input(bank, offset))
 763                 goto err;
 764         omap_enable_gpio_module(bank, offset);
 765         bank->irq_usage |= BIT(offset);
 766
 767         raw_spin_unlock_irqrestore(&bank->lock, flags);
 768         omap_gpio_unmask_irq(d);
 769
 770         return 0;
 771 err:
 772         raw_spin_unlock_irqrestore(&bank->lock, flags);
 773         return -EINVAL;
 774 }
 775
 776 static void omap_gpio_irq_shutdown(struct irq_data *d)
 777 {
 778         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 779         unsigned long flags;
 780         unsigned offset = d->hwirq;
 781
 782         raw_spin_lock_irqsave(&bank->lock, flags);
 783         bank->irq_usage &= ~(BIT(offset));
 784         omap_set_gpio_irqenable(bank, offset, 0);
 785         omap_clear_gpio_irqstatus(bank, offset);
 786         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 787         if (!LINE_USED(bank->mod_usage, offset))
 788                 omap_clear_gpio_debounce(bank, offset);
 789         omap_disable_gpio_module(bank, offset);
 790         raw_spin_unlock_irqrestore(&bank->lock, flags);
 791 }
 792
 793 static void omap_gpio_irq_bus_lock(struct irq_data *data)
 794 {
 795         struct gpio_bank *bank = omap_irq_data_get_bank(data);
 796
 797         if (!BANK_USED(bank))
 798                 pm_runtime_get_sync(bank->chip.parent);
 799 }
 800
 801 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
 802 {
 803         struct gpio_bank *bank = omap_irq_data_get_bank(data);
 804
 805         /*
 806          * If this is the last IRQ to be freed in the bank,
 807          * disable the bank module.
 808          */
 809         if (!BANK_USED(bank))
 810                 pm_runtime_put(bank->chip.parent);
 811 }
 812
 813 static void omap_gpio_ack_irq(struct irq_data *d)
 814 {
 815         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 816         unsigned offset = d->hwirq;
 817
 818         omap_clear_gpio_irqstatus(bank, offset);
 819 }
 820
 821 static void omap_gpio_mask_irq(struct irq_data *d)
 822 {
 823         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 824         unsigned offset = d->hwirq;
 825         unsigned long flags;
 826
 827         raw_spin_lock_irqsave(&bank->lock, flags);
 828         omap_set_gpio_irqenable(bank, offset, 0);
 829         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 830         raw_spin_unlock_irqrestore(&bank->lock, flags);
 831 }
 832
 833 static void omap_gpio_unmask_irq(struct irq_data *d)
 834 {
 835         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 836         unsigned offset = d->hwirq;
 837         u32 trigger = irqd_get_trigger_type(d);
 838         unsigned long flags;
 839
 840         raw_spin_lock_irqsave(&bank->lock, flags);
 841         if (trigger)
 842                 omap_set_gpio_triggering(bank, offset, trigger);
 843
 844         /* For level-triggered GPIOs, the clearing must be done after
 845          * the HW source is cleared, thus after the handler has run */
 846         if (bank->level_mask & BIT(offset)) {
 847                 omap_set_gpio_irqenable(bank, offset, 0);
 848                 omap_clear_gpio_irqstatus(bank, offset);
 849         }
 850
 851         omap_set_gpio_irqenable(bank, offset, 1);
 852         raw_spin_unlock_irqrestore(&bank->lock, flags);
 853 }
 854
 855 /*---------------------------------------------------------------------*/
 856
 857 static int omap_mpuio_suspend_noirq(struct device *dev)
 858 {
 859         struct platform_device *pdev = to_platform_device(dev);
 860         struct gpio_bank        *bank = platform_get_drvdata(pdev);
 861         void __iomem            *mask_reg = bank->base +
 862                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 863         unsigned long           flags;
 864
 865         raw_spin_lock_irqsave(&bank->lock, flags);
 866         writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
 867         raw_spin_unlock_irqrestore(&bank->lock, flags);
 868
 869         return 0;
 870 }
 871
 872 static int omap_mpuio_resume_noirq(struct device *dev)
 873 {
 874         struct platform_device *pdev = to_platform_device(dev);
 875         struct gpio_bank        *bank = platform_get_drvdata(pdev);
 876         void __iomem            *mask_reg = bank->base +
 877                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 878         unsigned long           flags;
 879
 880         raw_spin_lock_irqsave(&bank->lock, flags);
 881         writel_relaxed(bank->context.wake_en, mask_reg);
 882         raw_spin_unlock_irqrestore(&bank->lock, flags);
 883
 884         return 0;
 885 }
 886
 887 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
 888         .suspend_noirq = omap_mpuio_suspend_noirq,
 889         .resume_noirq = omap_mpuio_resume_noirq,
 890 };
 891
 892 /* use platform_driver for this. */
 893 static struct platform_driver omap_mpuio_driver = {
 894         .driver         = {
 895                 .name   = "mpuio",
 896                 .pm     = &omap_mpuio_dev_pm_ops,
 897         },
 898 };
 899
 900 static struct platform_device omap_mpuio_device = {
 901         .name           = "mpuio",
 902         .id             = -1,
 903         .dev = {
 904                 .driver = &omap_mpuio_driver.driver,
 905         }
 906         /* could list the /proc/iomem resources */
 907 };
 908
 909 static inline void omap_mpuio_init(struct gpio_bank *bank)
 910 {
 911         platform_set_drvdata(&omap_mpuio_device, bank);
 912
 913         if (platform_driver_register(&omap_mpuio_driver) == 0)
 914                 (void) platform_device_register(&omap_mpuio_device);
 915 }
 916
 917 /*---------------------------------------------------------------------*/
 918
 919 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 920 {
 921         struct gpio_bank *bank;
 922         unsigned long flags;
 923         void __iomem *reg;
 924         int dir;
 925
 926         bank = gpiochip_get_data(chip);
 927         reg = bank->base + bank->regs->direction;
 928         raw_spin_lock_irqsave(&bank->lock, flags);
 929         dir = !!(readl_relaxed(reg) & BIT(offset));
 930         raw_spin_unlock_irqrestore(&bank->lock, flags);
 931         return dir;
 932 }
 933
 934 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
 935 {
 936         struct gpio_bank *bank;
 937         unsigned long flags;
 938
 939         bank = gpiochip_get_data(chip);
 940         raw_spin_lock_irqsave(&bank->lock, flags);
 941         omap_set_gpio_direction(bank, offset, 1);
 942         raw_spin_unlock_irqrestore(&bank->lock, flags);
 943         return 0;
 944 }
 945
 946 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
 947 {
 948         struct gpio_bank *bank;
 949
 950         bank = gpiochip_get_data(chip);
 951
 952         if (omap_gpio_is_input(bank, offset))
 953                 return omap_get_gpio_datain(bank, offset);
 954         else
 955                 return omap_get_gpio_dataout(bank, offset);
 956 }
 957
 958 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
 959 {
 960         struct gpio_bank *bank;
 961         unsigned long flags;
 962
 963         bank = gpiochip_get_data(chip);
 964         raw_spin_lock_irqsave(&bank->lock, flags);
 965         bank->set_dataout(bank, offset, value);
 966         omap_set_gpio_direction(bank, offset, 0);
 967         raw_spin_unlock_irqrestore(&bank->lock, flags);
 968         return 0;
 969 }
 970
 971 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
 972                               unsigned debounce)
 973 {
 974         struct gpio_bank *bank;
 975         unsigned long flags;
 976         int ret;
 977
 978         bank = gpiochip_get_data(chip);
 979
 980         raw_spin_lock_irqsave(&bank->lock, flags);
 981         ret = omap2_set_gpio_debounce(bank, offset, debounce);
 982         raw_spin_unlock_irqrestore(&bank->lock, flags);
 983
 984         if (ret)
 985                 dev_info(chip->parent,
 986                          "Could not set line %u debounce to %u microseconds (%d)",
 987                          offset, debounce, ret);
 988
 989         return ret;
 990 }
 991
 992 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
 993                                 unsigned long config)
 994 {
 995         u32 debounce;
 996
 997         if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
 998                 return -ENOTSUPP;
 999
1000         debounce = pinconf_to_config_argument(config);
1001         return omap_gpio_debounce(chip, offset, debounce);
1002 }
1003
1004 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1005 {
1006         struct gpio_bank *bank;
1007         unsigned long flags;
1008
1009         bank = gpiochip_get_data(chip);
1010         raw_spin_lock_irqsave(&bank->lock, flags);
1011         bank->set_dataout(bank, offset, value);
1012         raw_spin_unlock_irqrestore(&bank->lock, flags);
1013 }
1014
1015 /*---------------------------------------------------------------------*/
1016
1017 static void omap_gpio_show_rev(struct gpio_bank *bank)
1018 {
1019         static bool called;
1020         u32 rev;
1021
1022         if (called || bank->regs->revision == USHRT_MAX)
1023                 return;
1024
1025         rev = readw_relaxed(bank->base + bank->regs->revision);
1026         pr_info("OMAP GPIO hardware version %d.%d\n",
1027                 (rev >> 4) & 0x0f, rev & 0x0f);
1028
1029         called = true;
1030 }
1031
1032 static void omap_gpio_mod_init(struct gpio_bank *bank)
1033 {
1034         void __iomem *base = bank->base;
1035         u32 l = 0xffffffff;
1036
1037         if (bank->width == 16)
1038                 l = 0xffff;
1039
1040         if (bank->is_mpuio) {
1041                 writel_relaxed(l, bank->base + bank->regs->irqenable);
1042                 return;
1043         }
1044
1045         omap_gpio_rmw(base, bank->regs->irqenable, l,
1046                       bank->regs->irqenable_inv);
1047         omap_gpio_rmw(base, bank->regs->irqstatus, l,
1048                       !bank->regs->irqenable_inv);
1049         if (bank->regs->debounce_en)
1050                 writel_relaxed(0, base + bank->regs->debounce_en);
1051
1052         /* Save OE default value (0xffffffff) in the context */
1053         bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1054          /* Initialize interface clk ungated, module enabled */
1055         if (bank->regs->ctrl)
1056                 writel_relaxed(0, base + bank->regs->ctrl);
1057 }
1058
1059 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1060 {
1061         static int gpio;
1062         int irq_base = 0;
1063         int ret;
1064
1065         /*
1066          * REVISIT eventually switch from OMAP-specific gpio structs
1067          * over to the generic ones
1068          */
1069         bank->chip.request = omap_gpio_request;
1070         bank->chip.free = omap_gpio_free;
1071         bank->chip.get_direction = omap_gpio_get_direction;
1072         bank->chip.direction_input = omap_gpio_input;
1073         bank->chip.get = omap_gpio_get;
1074         bank->chip.direction_output = omap_gpio_output;
1075         bank->chip.set_config = omap_gpio_set_config;
1076         bank->chip.set = omap_gpio_set;
1077         if (bank->is_mpuio) {
1078                 bank->chip.label = "mpuio";
1079                 if (bank->regs->wkup_en)
1080                         bank->chip.parent = &omap_mpuio_device.dev;
1081                 bank->chip.base = OMAP_MPUIO(0);
1082         } else {
1083                 bank->chip.label = "gpio";
1084                 bank->chip.base = gpio;
1085         }
1086         bank->chip.ngpio = bank->width;
1087
1088         ret = gpiochip_add_data(&bank->chip, bank);
1089         if (ret) {
1090                 dev_err(bank->chip.parent,
1091                         "Could not register gpio chip %d\n", ret);
1092                 return ret;
1093         }
1094
1095         if (!bank->is_mpuio)
1096                 gpio += bank->width;
1097
1098 #ifdef CONFIG_ARCH_OMAP1
1099         /*
1100          * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1101          * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1102          */
1103         irq_base = devm_irq_alloc_descs(bank->chip.parent,
1104                                         -1, 0, bank->width, 0);
1105         if (irq_base < 0) {
1106                 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1107                 return -ENODEV;
1108         }
1109 #endif
1110
1111         /* MPUIO is a bit different, reading IRQ status clears it */
1112         if (bank->is_mpuio) {
1113                 irqc->irq_ack = dummy_irq_chip.irq_ack;
1114                 if (!bank->regs->wkup_en)
1115                         irqc->irq_set_wake = NULL;
1116         }
1117
1118         ret = gpiochip_irqchip_add(&bank->chip, irqc,
1119                                    irq_base, handle_bad_irq,
1120                                    IRQ_TYPE_NONE);
1121
1122         if (ret) {
1123                 dev_err(bank->chip.parent,
1124                         "Couldn't add irqchip to gpiochip %d\n", ret);
1125                 gpiochip_remove(&bank->chip);
1126                 return -ENODEV;
1127         }
1128
1129         gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1130
1131         ret = devm_request_irq(bank->chip.parent, bank->irq,
1132                                omap_gpio_irq_handler,
1133                                0, dev_name(bank->chip.parent), bank);
1134         if (ret)
1135                 gpiochip_remove(&bank->chip);
1136
1137         return ret;
1138 }
1139
1140 static const struct of_device_id omap_gpio_match[];
1141
1142 static int omap_gpio_probe(struct platform_device *pdev)
1143 {
1144         struct device *dev = &pdev->dev;
1145         struct device_node *node = dev->of_node;
1146         const struct of_device_id *match;
1147         const struct omap_gpio_platform_data *pdata;
1148         struct resource *res;
1149         struct gpio_bank *bank;
1150         struct irq_chip *irqc;
1151         int ret;
1152
1153         match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1154
1155         pdata = match ? match->data : dev_get_platdata(dev);
1156         if (!pdata)
1157                 return -EINVAL;
1158
1159         bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1160         if (!bank) {
1161                 dev_err(dev, "Memory alloc failed\n");
1162                 return -ENOMEM;
1163         }
1164
1165         irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1166         if (!irqc)
1167                 return -ENOMEM;
1168
1169         irqc->irq_startup = omap_gpio_irq_startup,
1170         irqc->irq_shutdown = omap_gpio_irq_shutdown,
1171         irqc->irq_ack = omap_gpio_ack_irq,
1172         irqc->irq_mask = omap_gpio_mask_irq,
1173         irqc->irq_unmask = omap_gpio_unmask_irq,
1174         irqc->irq_set_type = omap_gpio_irq_type,
1175         irqc->irq_set_wake = omap_gpio_wake_enable,
1176         irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1177         irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1178         irqc->name = dev_name(&pdev->dev);
1179         irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1180
1181         bank->irq = platform_get_irq(pdev, 0);
1182         if (bank->irq <= 0) {
1183                 if (!bank->irq)
1184                         bank->irq = -ENXIO;
1185                 if (bank->irq != -EPROBE_DEFER)
1186                         dev_err(dev,
1187                                 "can't get irq resource ret=%d\n", bank->irq);
1188                 return bank->irq;
1189         }
1190
1191         bank->chip.parent = dev;
1192         bank->chip.owner = THIS_MODULE;
1193         bank->dbck_flag = pdata->dbck_flag;
1194         bank->stride = pdata->bank_stride;
1195         bank->width = pdata->bank_width;
1196         bank->is_mpuio = pdata->is_mpuio;
1197         bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1198         bank->regs = pdata->regs;
1199 #ifdef CONFIG_OF_GPIO
1200         bank->chip.of_node = of_node_get(node);
1201 #endif
1202         if (node) {
1203                 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1204                         bank->loses_context = true;
1205         } else {
1206                 bank->loses_context = pdata->loses_context;
1207
1208                 if (bank->loses_context)
1209                         bank->get_context_loss_count =
1210                                 pdata->get_context_loss_count;
1211         }
1212
1213         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1214                 bank->set_dataout = omap_set_gpio_dataout_reg;
1215         else
1216                 bank->set_dataout = omap_set_gpio_dataout_mask;
1217
1218         raw_spin_lock_init(&bank->lock);
1219         raw_spin_lock_init(&bank->wa_lock);
1220
1221         /* Static mapping, never released */
1222         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1223         bank->base = devm_ioremap_resource(dev, res);
1224         if (IS_ERR(bank->base)) {
1225                 return PTR_ERR(bank->base);
1226         }
1227
1228         if (bank->dbck_flag) {
1229                 bank->dbck = devm_clk_get(dev, "dbclk");
1230                 if (IS_ERR(bank->dbck)) {
1231                         dev_err(dev,
1232                                 "Could not get gpio dbck. Disable debounce\n");
1233                         bank->dbck_flag = false;
1234                 } else {
1235                         clk_prepare(bank->dbck);
1236                 }
1237         }
1238
1239         platform_set_drvdata(pdev, bank);
1240
1241         pm_runtime_enable(dev);
1242         pm_runtime_irq_safe(dev);
1243         pm_runtime_get_sync(dev);
1244
1245         if (bank->is_mpuio)
1246                 omap_mpuio_init(bank);
1247
1248         omap_gpio_mod_init(bank);
1249
1250         ret = omap_gpio_chip_init(bank, irqc);
1251         if (ret) {
1252                 pm_runtime_put_sync(dev);
1253                 pm_runtime_disable(dev);
1254                 if (bank->dbck_flag)
1255                         clk_unprepare(bank->dbck);
1256                 return ret;
1257         }
1258
1259         omap_gpio_show_rev(bank);
1260
1261         pm_runtime_put(dev);
1262
1263         list_add_tail(&bank->node, &omap_gpio_list);
1264
1265         return 0;
1266 }
1267
1268 static int omap_gpio_remove(struct platform_device *pdev)
1269 {
1270         struct gpio_bank *bank = platform_get_drvdata(pdev);
1271
1272         list_del(&bank->node);
1273         gpiochip_remove(&bank->chip);
1274         pm_runtime_disable(&pdev->dev);
1275         if (bank->dbck_flag)
1276                 clk_unprepare(bank->dbck);
1277
1278         return 0;
1279 }
1280
1281 #ifdef CONFIG_ARCH_OMAP2PLUS
1282
1283 #if defined(CONFIG_PM)
1284 static void omap_gpio_restore_context(struct gpio_bank *bank);
1285
1286 static int omap_gpio_runtime_suspend(struct device *dev)
1287 {
1288         struct platform_device *pdev = to_platform_device(dev);
1289         struct gpio_bank *bank = platform_get_drvdata(pdev);
1290         u32 l1 = 0, l2 = 0;
1291         unsigned long flags;
1292         u32 wake_low, wake_hi;
1293
1294         raw_spin_lock_irqsave(&bank->lock, flags);
1295
1296         /*
1297          * Only edges can generate a wakeup event to the PRCM.
1298          *
1299          * Therefore, ensure any wake-up capable GPIOs have
1300          * edge-detection enabled before going idle to ensure a wakeup
1301          * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1302          * NDA TRM 25.5.3.1)
1303          *
1304          * The normal values will be restored upon ->runtime_resume()
1305          * by writing back the values saved in bank->context.
1306          */
1307         wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1308         if (wake_low)
1309                 writel_relaxed(wake_low | bank->context.fallingdetect,
1310                              bank->base + bank->regs->fallingdetect);
1311         wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1312         if (wake_hi)
1313                 writel_relaxed(wake_hi | bank->context.risingdetect,
1314                              bank->base + bank->regs->risingdetect);
1315
1316         if (!bank->enabled_non_wakeup_gpios)
1317                 goto update_gpio_context_count;
1318
1319         if (bank->power_mode != OFF_MODE) {
1320                 bank->power_mode = 0;
1321                 goto update_gpio_context_count;
1322         }
1323         /*
1324          * If going to OFF, remove triggering for all
1325          * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1326          * generated.  See OMAP2420 Errata item 1.101.
1327          */
1328         bank->saved_datain = readl_relaxed(bank->base +
1329                                                 bank->regs->datain);
1330         l1 = bank->context.fallingdetect;
1331         l2 = bank->context.risingdetect;
1332
1333         l1 &= ~bank->enabled_non_wakeup_gpios;
1334         l2 &= ~bank->enabled_non_wakeup_gpios;
1335
1336         writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1337         writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1338
1339         bank->workaround_enabled = true;
1340
1341 update_gpio_context_count:
1342         if (bank->get_context_loss_count)
1343                 bank->context_loss_count =
1344                                 bank->get_context_loss_count(dev);
1345
1346         omap_gpio_dbck_disable(bank);
1347         raw_spin_unlock_irqrestore(&bank->lock, flags);
1348
1349         return 0;
1350 }
1351
1352 static void omap_gpio_init_context(struct gpio_bank *p);
1353
1354 static int omap_gpio_runtime_resume(struct device *dev)
1355 {
1356         struct platform_device *pdev = to_platform_device(dev);
1357         struct gpio_bank *bank = platform_get_drvdata(pdev);
1358         u32 l = 0, gen, gen0, gen1;
1359         unsigned long flags;
1360         int c;
1361
1362         raw_spin_lock_irqsave(&bank->lock, flags);
1363
1364         /*
1365          * On the first resume during the probe, the context has not
1366          * been initialised and so initialise it now. Also initialise
1367          * the context loss count.
1368          */
1369         if (bank->loses_context && !bank->context_valid) {
1370                 omap_gpio_init_context(bank);
1371
1372                 if (bank->get_context_loss_count)
1373                         bank->context_loss_count =
1374                                 bank->get_context_loss_count(dev);
1375         }
1376
1377         omap_gpio_dbck_enable(bank);
1378
1379         /*
1380          * In ->runtime_suspend(), level-triggered, wakeup-enabled
1381          * GPIOs were set to edge trigger also in order to be able to
1382          * generate a PRCM wakeup.  Here we restore the
1383          * pre-runtime_suspend() values for edge triggering.
1384          */
1385         writel_relaxed(bank->context.fallingdetect,
1386                      bank->base + bank->regs->fallingdetect);
1387         writel_relaxed(bank->context.risingdetect,
1388                      bank->base + bank->regs->risingdetect);
1389
1390         if (bank->loses_context) {
1391                 if (!bank->get_context_loss_count) {
1392                         omap_gpio_restore_context(bank);
1393                 } else {
1394                         c = bank->get_context_loss_count(dev);
1395                         if (c != bank->context_loss_count) {
1396                                 omap_gpio_restore_context(bank);
1397                         } else {
1398                                 raw_spin_unlock_irqrestore(&bank->lock, flags);
1399                                 return 0;
1400                         }
1401                 }
1402         }
1403
1404         if (!bank->workaround_enabled) {
1405                 raw_spin_unlock_irqrestore(&bank->lock, flags);
1406                 return 0;
1407         }
1408
1409         l = readl_relaxed(bank->base + bank->regs->datain);
1410
1411         /*
1412          * Check if any of the non-wakeup interrupt GPIOs have changed
1413          * state.  If so, generate an IRQ by software.  This is
1414          * horribly racy, but it's the best we can do to work around
1415          * this silicon bug.
1416          */
1417         l ^= bank->saved_datain;
1418         l &= bank->enabled_non_wakeup_gpios;
1419
1420         /*
1421          * No need to generate IRQs for the rising edge for gpio IRQs
1422          * configured with falling edge only; and vice versa.
1423          */
1424         gen0 = l & bank->context.fallingdetect;
1425         gen0 &= bank->saved_datain;
1426
1427         gen1 = l & bank->context.risingdetect;
1428         gen1 &= ~(bank->saved_datain);
1429
1430         /* FIXME: Consider GPIO IRQs with level detections properly! */
1431         gen = l & (~(bank->context.fallingdetect) &
1432                                          ~(bank->context.risingdetect));
1433         /* Consider all GPIO IRQs needed to be updated */
1434         gen |= gen0 | gen1;
1435
1436         if (gen) {
1437                 u32 old0, old1;
1438
1439                 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1440                 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1441
1442                 if (!bank->regs->irqstatus_raw0) {
1443                         writel_relaxed(old0 | gen, bank->base +
1444                                                 bank->regs->leveldetect0);
1445                         writel_relaxed(old1 | gen, bank->base +
1446                                                 bank->regs->leveldetect1);
1447                 }
1448
1449                 if (bank->regs->irqstatus_raw0) {
1450                         writel_relaxed(old0 | l, bank->base +
1451                                                 bank->regs->leveldetect0);
1452                         writel_relaxed(old1 | l, bank->base +
1453                                                 bank->regs->leveldetect1);
1454                 }
1455                 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1456                 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1457         }
1458
1459         bank->workaround_enabled = false;
1460         raw_spin_unlock_irqrestore(&bank->lock, flags);
1461
1462         return 0;
1463 }
1464 #endif /* CONFIG_PM */
1465
1466 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1467 void omap2_gpio_prepare_for_idle(int pwr_mode)
1468 {
1469         struct gpio_bank *bank;
1470
1471         list_for_each_entry(bank, &omap_gpio_list, node) {
1472                 if (!BANK_USED(bank) || !bank->loses_context)
1473                         continue;
1474
1475                 bank->power_mode = pwr_mode;
1476
1477                 pm_runtime_put_sync_suspend(bank->chip.parent);
1478         }
1479 }
1480
1481 void omap2_gpio_resume_after_idle(void)
1482 {
1483         struct gpio_bank *bank;
1484
1485         list_for_each_entry(bank, &omap_gpio_list, node) {
1486                 if (!BANK_USED(bank) || !bank->loses_context)
1487                         continue;
1488
1489                 pm_runtime_get_sync(bank->chip.parent);
1490         }
1491 }
1492 #endif
1493
1494 #if defined(CONFIG_PM)
1495 static void omap_gpio_init_context(struct gpio_bank *p)
1496 {
1497         struct omap_gpio_reg_offs *regs = p->regs;
1498         void __iomem *base = p->base;
1499
1500         p->context.ctrl         = readl_relaxed(base + regs->ctrl);
1501         p->context.oe           = readl_relaxed(base + regs->direction);
1502         p->context.wake_en      = readl_relaxed(base + regs->wkup_en);
1503         p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1504         p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1505         p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1506         p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1507         p->context.irqenable1   = readl_relaxed(base + regs->irqenable);
1508         p->context.irqenable2   = readl_relaxed(base + regs->irqenable2);
1509
1510         if (regs->set_dataout && p->regs->clr_dataout)
1511                 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1512         else
1513                 p->context.dataout = readl_relaxed(base + regs->dataout);
1514
1515         p->context_valid = true;
1516 }
1517
1518 static void omap_gpio_restore_context(struct gpio_bank *bank)
1519 {
1520         writel_relaxed(bank->context.wake_en,
1521                                 bank->base + bank->regs->wkup_en);
1522         writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1523         writel_relaxed(bank->context.leveldetect0,
1524                                 bank->base + bank->regs->leveldetect0);
1525         writel_relaxed(bank->context.leveldetect1,
1526                                 bank->base + bank->regs->leveldetect1);
1527         writel_relaxed(bank->context.risingdetect,
1528                                 bank->base + bank->regs->risingdetect);
1529         writel_relaxed(bank->context.fallingdetect,
1530                                 bank->base + bank->regs->fallingdetect);
1531         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1532                 writel_relaxed(bank->context.dataout,
1533                                 bank->base + bank->regs->set_dataout);
1534         else
1535                 writel_relaxed(bank->context.dataout,
1536                                 bank->base + bank->regs->dataout);
1537         writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1538
1539         if (bank->dbck_enable_mask) {
1540                 writel_relaxed(bank->context.debounce, bank->base +
1541                                         bank->regs->debounce);
1542                 writel_relaxed(bank->context.debounce_en,
1543                                         bank->base + bank->regs->debounce_en);
1544         }
1545
1546         writel_relaxed(bank->context.irqenable1,
1547                                 bank->base + bank->regs->irqenable);
1548         writel_relaxed(bank->context.irqenable2,
1549                                 bank->base + bank->regs->irqenable2);
1550 }
1551 #endif /* CONFIG_PM */
1552 #else
1553 #define omap_gpio_runtime_suspend NULL
1554 #define omap_gpio_runtime_resume NULL
1555 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1556 #endif
1557
1558 static const struct dev_pm_ops gpio_pm_ops = {
1559         SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1560                                                                         NULL)
1561 };
1562
1563 #if defined(CONFIG_OF)
1564 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1565         .revision =             OMAP24XX_GPIO_REVISION,
1566         .direction =            OMAP24XX_GPIO_OE,
1567         .datain =               OMAP24XX_GPIO_DATAIN,
1568         .dataout =              OMAP24XX_GPIO_DATAOUT,
1569         .set_dataout =          OMAP24XX_GPIO_SETDATAOUT,
1570         .clr_dataout =          OMAP24XX_GPIO_CLEARDATAOUT,
1571         .irqstatus =            OMAP24XX_GPIO_IRQSTATUS1,
1572         .irqstatus2 =           OMAP24XX_GPIO_IRQSTATUS2,
1573         .irqenable =            OMAP24XX_GPIO_IRQENABLE1,
1574         .irqenable2 =           OMAP24XX_GPIO_IRQENABLE2,
1575         .set_irqenable =        OMAP24XX_GPIO_SETIRQENABLE1,
1576         .clr_irqenable =        OMAP24XX_GPIO_CLEARIRQENABLE1,
1577         .debounce =             OMAP24XX_GPIO_DEBOUNCE_VAL,
1578         .debounce_en =          OMAP24XX_GPIO_DEBOUNCE_EN,
1579         .ctrl =                 OMAP24XX_GPIO_CTRL,
1580         .wkup_en =              OMAP24XX_GPIO_WAKE_EN,
1581         .leveldetect0 =         OMAP24XX_GPIO_LEVELDETECT0,
1582         .leveldetect1 =         OMAP24XX_GPIO_LEVELDETECT1,
1583         .risingdetect =         OMAP24XX_GPIO_RISINGDETECT,
1584         .fallingdetect =        OMAP24XX_GPIO_FALLINGDETECT,
1585 };
1586
1587 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1588         .revision =             OMAP4_GPIO_REVISION,
1589         .direction =            OMAP4_GPIO_OE,
1590         .datain =               OMAP4_GPIO_DATAIN,
1591         .dataout =              OMAP4_GPIO_DATAOUT,
1592         .set_dataout =          OMAP4_GPIO_SETDATAOUT,
1593         .clr_dataout =          OMAP4_GPIO_CLEARDATAOUT,
1594         .irqstatus =            OMAP4_GPIO_IRQSTATUS0,
1595         .irqstatus2 =           OMAP4_GPIO_IRQSTATUS1,
1596         .irqenable =            OMAP4_GPIO_IRQSTATUSSET0,
1597         .irqenable2 =           OMAP4_GPIO_IRQSTATUSSET1,
1598         .set_irqenable =        OMAP4_GPIO_IRQSTATUSSET0,
1599         .clr_irqenable =        OMAP4_GPIO_IRQSTATUSCLR0,
1600         .debounce =             OMAP4_GPIO_DEBOUNCINGTIME,
1601         .debounce_en =          OMAP4_GPIO_DEBOUNCENABLE,
1602         .ctrl =                 OMAP4_GPIO_CTRL,
1603         .wkup_en =              OMAP4_GPIO_IRQWAKEN0,
1604         .leveldetect0 =         OMAP4_GPIO_LEVELDETECT0,
1605         .leveldetect1 =         OMAP4_GPIO_LEVELDETECT1,
1606         .risingdetect =         OMAP4_GPIO_RISINGDETECT,
1607         .fallingdetect =        OMAP4_GPIO_FALLINGDETECT,
1608 };
1609
1610 static const struct omap_gpio_platform_data omap2_pdata = {
1611         .regs = &omap2_gpio_regs,
1612         .bank_width = 32,
1613         .dbck_flag = false,
1614 };
1615
1616 static const struct omap_gpio_platform_data omap3_pdata = {
1617         .regs = &omap2_gpio_regs,
1618         .bank_width = 32,
1619         .dbck_flag = true,
1620 };
1621
1622 static const struct omap_gpio_platform_data omap4_pdata = {
1623         .regs = &omap4_gpio_regs,
1624         .bank_width = 32,
1625         .dbck_flag = true,
1626 };
1627
1628 static const struct of_device_id omap_gpio_match[] = {
1629         {
1630                 .compatible = "ti,omap4-gpio",
1631                 .data = &omap4_pdata,
1632         },
1633         {
1634                 .compatible = "ti,omap3-gpio",
1635                 .data = &omap3_pdata,
1636         },
1637         {
1638                 .compatible = "ti,omap2-gpio",
1639                 .data = &omap2_pdata,
1640         },
1641         { },
1642 };
1643 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1644 #endif
1645
1646 static struct platform_driver omap_gpio_driver = {
1647         .probe          = omap_gpio_probe,
1648         .remove         = omap_gpio_remove,
1649         .driver         = {
1650                 .name   = "omap_gpio",
1651                 .pm     = &gpio_pm_ops,
1652                 .of_match_table = of_match_ptr(omap_gpio_match),
1653         },
1654 };
1655
1656 /*
1657  * gpio driver register needs to be done before
1658  * machine_init functions access gpio APIs.
1659  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1660  */
1661 static int __init omap_gpio_drv_reg(void)
1662 {
1663         return platform_driver_register(&omap_gpio_driver);
1664 }
1665 postcore_initcall(omap_gpio_drv_reg);
1666
1667 static void __exit omap_gpio_exit(void)
1668 {
1669         platform_driver_unregister(&omap_gpio_driver);
1670 }
1671 module_exit(omap_gpio_exit);
1672
1673 MODULE_DESCRIPTION("omap gpio driver");
1674 MODULE_ALIAS("platform:gpio-omap");
1675 MODULE_LICENSE("GPL v2");