2 * GPIO driver for Marvell SoCs
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
36 #include <linux/bitops.h>
37 #include <linux/clk.h>
38 #include <linux/err.h>
39 #include <linux/gpio/driver.h>
40 #include <linux/gpio/consumer.h>
41 #include <linux/gpio/machine.h>
42 #include <linux/init.h>
44 #include <linux/irq.h>
45 #include <linux/irqchip/chained_irq.h>
46 #include <linux/irqdomain.h>
47 #include <linux/mfd/syscon.h>
48 #include <linux/of_device.h>
49 #include <linux/pinctrl/consumer.h>
50 #include <linux/platform_device.h>
51 #include <linux/pwm.h>
52 #include <linux/regmap.h>
53 #include <linux/slab.h>
56 * GPIO unit register offsets.
58 #define GPIO_OUT_OFF 0x0000
59 #define GPIO_IO_CONF_OFF 0x0004
60 #define GPIO_BLINK_EN_OFF 0x0008
61 #define GPIO_IN_POL_OFF 0x000c
62 #define GPIO_DATA_IN_OFF 0x0010
63 #define GPIO_EDGE_CAUSE_OFF 0x0014
64 #define GPIO_EDGE_MASK_OFF 0x0018
65 #define GPIO_LEVEL_MASK_OFF 0x001c
66 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
69 * PWM register offsets.
71 #define PWM_BLINK_ON_DURATION_OFF 0x0
72 #define PWM_BLINK_OFF_DURATION_OFF 0x4
75 /* The MV78200 has per-CPU registers for edge mask and level mask */
76 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
77 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
80 * The Armada XP has per-CPU registers for interrupt cause, interrupt
81 * mask and interrupt level mask. Those are in percpu_regs range.
83 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
84 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
85 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
87 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
88 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
89 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
90 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
92 #define MVEBU_MAX_GPIO_PER_BANK 32
96 unsigned long clk_rate;
97 struct gpio_desc *gpiod;
100 struct mvebu_gpio_chip *mvchip;
102 /* Used to preserve GPIO/PWM registers across suspend/resume */
104 u32 blink_on_duration;
105 u32 blink_off_duration;
108 struct mvebu_gpio_chip {
109 struct gpio_chip chip;
112 struct regmap *percpu_regs;
114 struct irq_domain *domain;
117 /* Used for PWM support */
119 struct mvebu_pwm *mvpwm;
121 /* Used to preserve GPIO registers across suspend/resume */
126 u32 edge_mask_regs[4];
127 u32 level_mask_regs[4];
131 * Functions returning addresses of individual registers for a given
135 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
136 struct regmap **map, unsigned int *offset)
140 switch (mvchip->soc_variant) {
141 case MVEBU_GPIO_SOC_VARIANT_ORION:
142 case MVEBU_GPIO_SOC_VARIANT_MV78200:
143 case MVEBU_GPIO_SOC_VARIANT_A8K:
145 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
147 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
148 cpu = smp_processor_id();
149 *map = mvchip->percpu_regs;
150 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
158 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
164 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
165 regmap_read(map, offset, &val);
171 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
176 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
177 regmap_write(map, offset, val);
181 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
182 struct regmap **map, unsigned int *offset)
186 switch (mvchip->soc_variant) {
187 case MVEBU_GPIO_SOC_VARIANT_ORION:
188 case MVEBU_GPIO_SOC_VARIANT_A8K:
190 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
192 case MVEBU_GPIO_SOC_VARIANT_MV78200:
193 cpu = smp_processor_id();
195 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
197 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
198 cpu = smp_processor_id();
199 *map = mvchip->percpu_regs;
200 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
208 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
214 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
215 regmap_read(map, offset, &val);
221 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
226 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
227 regmap_write(map, offset, val);
231 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
232 struct regmap **map, unsigned int *offset)
236 switch (mvchip->soc_variant) {
237 case MVEBU_GPIO_SOC_VARIANT_ORION:
238 case MVEBU_GPIO_SOC_VARIANT_A8K:
240 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
242 case MVEBU_GPIO_SOC_VARIANT_MV78200:
243 cpu = smp_processor_id();
245 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
247 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
248 cpu = smp_processor_id();
249 *map = mvchip->percpu_regs;
250 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
258 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
264 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
265 regmap_read(map, offset, &val);
271 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
276 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
277 regmap_write(map, offset, val);
281 * Functions returning offsets of individual registers for a given
284 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
286 return PWM_BLINK_ON_DURATION_OFF;
289 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
291 return PWM_BLINK_OFF_DURATION_OFF;
295 * Functions implementing the gpio_chip methods
297 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
299 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
301 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
302 BIT(pin), value ? BIT(pin) : 0);
305 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
307 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
310 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
315 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
317 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
319 u = data_in ^ in_pol;
321 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
324 return (u >> pin) & 1;
327 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
330 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
332 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
333 BIT(pin), value ? BIT(pin) : 0);
336 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
338 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
342 * Check with the pinctrl driver whether this pin is usable as
345 ret = pinctrl_gpio_direction_input(chip->base + pin);
349 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
355 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
358 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
362 * Check with the pinctrl driver whether this pin is usable as
365 ret = pinctrl_gpio_direction_output(chip->base + pin);
369 mvebu_gpio_blink(chip, pin, 0);
370 mvebu_gpio_set(chip, pin, value);
372 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
378 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
380 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
383 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
386 return GPIO_LINE_DIRECTION_IN;
388 return GPIO_LINE_DIRECTION_OUT;
391 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
393 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
395 return irq_create_mapping(mvchip->domain, pin);
399 * Functions implementing the irq_chip methods
401 static void mvebu_gpio_irq_ack(struct irq_data *d)
403 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
404 struct mvebu_gpio_chip *mvchip = gc->private;
408 mvebu_gpio_write_edge_cause(mvchip, ~mask);
412 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
414 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
415 struct mvebu_gpio_chip *mvchip = gc->private;
416 struct irq_chip_type *ct = irq_data_get_chip_type(d);
420 ct->mask_cache_priv &= ~mask;
421 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
425 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
427 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
428 struct mvebu_gpio_chip *mvchip = gc->private;
429 struct irq_chip_type *ct = irq_data_get_chip_type(d);
433 mvebu_gpio_write_edge_cause(mvchip, ~mask);
434 ct->mask_cache_priv |= mask;
435 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
439 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
441 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
442 struct mvebu_gpio_chip *mvchip = gc->private;
443 struct irq_chip_type *ct = irq_data_get_chip_type(d);
447 ct->mask_cache_priv &= ~mask;
448 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
452 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
454 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
455 struct mvebu_gpio_chip *mvchip = gc->private;
456 struct irq_chip_type *ct = irq_data_get_chip_type(d);
460 ct->mask_cache_priv |= mask;
461 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
465 /*****************************************************************************
468 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
469 * value of the line or the opposite value.
471 * Level IRQ handlers: DATA_IN is used directly as cause register.
472 * Interrupt are masked by LEVEL_MASK registers.
473 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
474 * Interrupt are masked by EDGE_MASK registers.
475 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
476 * the polarity to catch the next line transaction.
477 * This is a race condition that might not perfectly
478 * work on some use cases.
480 * Every eight GPIO lines are grouped (OR'ed) before going up to main
484 * data-in /--------| |-----| |----\
485 * -----| |----- ---- to main cause reg
486 * X \----------------| |----/
487 * polarity LEVEL mask
489 ****************************************************************************/
491 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
493 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
494 struct irq_chip_type *ct = irq_data_get_chip_type(d);
495 struct mvebu_gpio_chip *mvchip = gc->private;
501 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
502 if ((u & BIT(pin)) == 0)
505 type &= IRQ_TYPE_SENSE_MASK;
506 if (type == IRQ_TYPE_NONE)
509 /* Check if we need to change chip and handler */
510 if (!(ct->type & type))
511 if (irq_setup_alt_chip(d, type))
515 * Configure interrupt polarity.
518 case IRQ_TYPE_EDGE_RISING:
519 case IRQ_TYPE_LEVEL_HIGH:
520 regmap_update_bits(mvchip->regs,
521 GPIO_IN_POL_OFF + mvchip->offset,
524 case IRQ_TYPE_EDGE_FALLING:
525 case IRQ_TYPE_LEVEL_LOW:
526 regmap_update_bits(mvchip->regs,
527 GPIO_IN_POL_OFF + mvchip->offset,
530 case IRQ_TYPE_EDGE_BOTH: {
531 u32 data_in, in_pol, val;
533 regmap_read(mvchip->regs,
534 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
535 regmap_read(mvchip->regs,
536 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
539 * set initial polarity based on current input level
541 if ((data_in ^ in_pol) & BIT(pin))
542 val = BIT(pin); /* falling */
544 val = 0; /* raising */
546 regmap_update_bits(mvchip->regs,
547 GPIO_IN_POL_OFF + mvchip->offset,
555 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
557 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
558 struct irq_chip *chip = irq_desc_get_chip(desc);
559 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
565 chained_irq_enter(chip, desc);
567 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
568 level_mask = mvebu_gpio_read_level_mask(mvchip);
569 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
570 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
572 cause = (data_in & level_mask) | (edge_cause & edge_mask);
574 for (i = 0; i < mvchip->chip.ngpio; i++) {
577 irq = irq_find_mapping(mvchip->domain, i);
579 if (!(cause & BIT(i)))
582 type = irq_get_trigger_type(irq);
583 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
584 /* Swap polarity (race with GPIO line) */
587 regmap_read(mvchip->regs,
588 GPIO_IN_POL_OFF + mvchip->offset,
591 regmap_write(mvchip->regs,
592 GPIO_IN_POL_OFF + mvchip->offset,
596 generic_handle_irq(irq);
599 chained_irq_exit(chip, desc);
602 static const struct regmap_config mvebu_gpio_regmap_config = {
610 * Functions implementing the pwm_chip methods
612 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
614 return container_of(chip, struct mvebu_pwm, chip);
617 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
619 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
620 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
621 struct gpio_desc *desc;
625 spin_lock_irqsave(&mvpwm->lock, flags);
630 desc = gpiochip_request_own_desc(&mvchip->chip,
631 pwm->hwpwm, "mvebu-pwm",
642 spin_unlock_irqrestore(&mvpwm->lock, flags);
646 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
648 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
651 spin_lock_irqsave(&mvpwm->lock, flags);
652 gpiochip_free_own_desc(mvpwm->gpiod);
654 spin_unlock_irqrestore(&mvpwm->lock, flags);
657 static void mvebu_pwm_get_state(struct pwm_chip *chip,
658 struct pwm_device *pwm,
659 struct pwm_state *state) {
661 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
662 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
663 unsigned long long val;
667 spin_lock_irqsave(&mvpwm->lock, flags);
669 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
670 val = (unsigned long long) u * NSEC_PER_SEC;
671 do_div(val, mvpwm->clk_rate);
673 state->duty_cycle = UINT_MAX;
675 state->duty_cycle = val;
677 state->duty_cycle = 1;
679 val = (unsigned long long) u; /* on duration */
680 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
681 val += (unsigned long long) u; /* period = on + off duration */
683 do_div(val, mvpwm->clk_rate);
685 state->period = UINT_MAX;
691 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
693 state->enabled = true;
695 state->enabled = false;
697 spin_unlock_irqrestore(&mvpwm->lock, flags);
700 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
701 const struct pwm_state *state)
703 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
704 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
705 unsigned long long val;
707 unsigned int on, off;
709 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
710 do_div(val, NSEC_PER_SEC);
718 val = (unsigned long long) mvpwm->clk_rate *
719 (state->period - state->duty_cycle);
720 do_div(val, NSEC_PER_SEC);
728 spin_lock_irqsave(&mvpwm->lock, flags);
730 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on);
731 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off);
733 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
735 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
737 spin_unlock_irqrestore(&mvpwm->lock, flags);
742 static const struct pwm_ops mvebu_pwm_ops = {
743 .request = mvebu_pwm_request,
744 .free = mvebu_pwm_free,
745 .get_state = mvebu_pwm_get_state,
746 .apply = mvebu_pwm_apply,
747 .owner = THIS_MODULE,
750 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
752 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
754 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
755 &mvpwm->blink_select);
756 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
757 &mvpwm->blink_on_duration);
758 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
759 &mvpwm->blink_off_duration);
762 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
764 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
766 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
767 mvpwm->blink_select);
768 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
769 mvpwm->blink_on_duration);
770 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
771 mvpwm->blink_off_duration);
774 static int mvebu_pwm_probe(struct platform_device *pdev,
775 struct mvebu_gpio_chip *mvchip,
778 struct device *dev = &pdev->dev;
779 struct mvebu_pwm *mvpwm;
783 if (!of_device_is_compatible(mvchip->chip.of_node,
784 "marvell,armada-370-gpio"))
788 * There are only two sets of PWM configuration registers for
789 * all the GPIO lines on those SoCs which this driver reserves
790 * for the first two GPIO chips. So if the resource is missing
791 * we can't treat it as an error.
793 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
796 if (IS_ERR(mvchip->clk))
797 return PTR_ERR(mvchip->clk);
800 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
801 * with id 1. Don't allow further GPIO chips to be used for PWM.
809 regmap_write(mvchip->regs,
810 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
812 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
815 mvchip->mvpwm = mvpwm;
816 mvpwm->mvchip = mvchip;
818 base = devm_platform_ioremap_resource_byname(pdev, "pwm");
820 return PTR_ERR(base);
822 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
823 &mvebu_gpio_regmap_config);
824 if (IS_ERR(mvpwm->regs))
825 return PTR_ERR(mvpwm->regs);
827 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
828 if (!mvpwm->clk_rate) {
829 dev_err(dev, "failed to get clock rate\n");
833 mvpwm->chip.dev = dev;
834 mvpwm->chip.ops = &mvebu_pwm_ops;
835 mvpwm->chip.npwm = mvchip->chip.ngpio;
837 * There may already be some PWM allocated, so we can't force
838 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
839 * So, we let pwmchip_add() do the numbering and take the next free
842 mvpwm->chip.base = -1;
844 spin_lock_init(&mvpwm->lock);
846 return pwmchip_add(&mvpwm->chip);
849 #ifdef CONFIG_DEBUG_FS
850 #include <linux/seq_file.h>
852 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
854 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
855 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
859 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
860 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
861 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
862 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
863 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
864 cause = mvebu_gpio_read_edge_cause(mvchip);
865 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
866 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
868 for_each_requested_gpio(chip, i, label) {
873 is_out = !(io_conf & msk);
875 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
878 seq_printf(s, " out %s %s\n",
879 out & msk ? "hi" : "lo",
880 blink & msk ? "(blink )" : "");
884 seq_printf(s, " in %s (act %s) - IRQ",
885 (data_in ^ in_pol) & msk ? "hi" : "lo",
886 in_pol & msk ? "lo" : "hi");
887 if (!((edg_msk | lvl_msk) & msk)) {
888 seq_puts(s, " disabled\n");
892 seq_puts(s, " edge ");
894 seq_puts(s, " level");
895 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
899 #define mvebu_gpio_dbg_show NULL
902 static const struct of_device_id mvebu_gpio_of_match[] = {
904 .compatible = "marvell,orion-gpio",
905 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
908 .compatible = "marvell,mv78200-gpio",
909 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
912 .compatible = "marvell,armadaxp-gpio",
913 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
916 .compatible = "marvell,armada-370-gpio",
917 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
920 .compatible = "marvell,armada-8k-gpio",
921 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
928 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
930 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
933 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
935 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
936 &mvchip->io_conf_reg);
937 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
938 &mvchip->blink_en_reg);
939 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
940 &mvchip->in_pol_reg);
942 switch (mvchip->soc_variant) {
943 case MVEBU_GPIO_SOC_VARIANT_ORION:
944 case MVEBU_GPIO_SOC_VARIANT_A8K:
945 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
946 &mvchip->edge_mask_regs[0]);
947 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
948 &mvchip->level_mask_regs[0]);
950 case MVEBU_GPIO_SOC_VARIANT_MV78200:
951 for (i = 0; i < 2; i++) {
952 regmap_read(mvchip->regs,
953 GPIO_EDGE_MASK_MV78200_OFF(i),
954 &mvchip->edge_mask_regs[i]);
955 regmap_read(mvchip->regs,
956 GPIO_LEVEL_MASK_MV78200_OFF(i),
957 &mvchip->level_mask_regs[i]);
960 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
961 for (i = 0; i < 4; i++) {
962 regmap_read(mvchip->regs,
963 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
964 &mvchip->edge_mask_regs[i]);
965 regmap_read(mvchip->regs,
966 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
967 &mvchip->level_mask_regs[i]);
974 if (IS_ENABLED(CONFIG_PWM))
975 mvebu_pwm_suspend(mvchip);
980 static int mvebu_gpio_resume(struct platform_device *pdev)
982 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
985 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
987 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
988 mvchip->io_conf_reg);
989 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
990 mvchip->blink_en_reg);
991 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
994 switch (mvchip->soc_variant) {
995 case MVEBU_GPIO_SOC_VARIANT_ORION:
996 case MVEBU_GPIO_SOC_VARIANT_A8K:
997 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
998 mvchip->edge_mask_regs[0]);
999 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
1000 mvchip->level_mask_regs[0]);
1002 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1003 for (i = 0; i < 2; i++) {
1004 regmap_write(mvchip->regs,
1005 GPIO_EDGE_MASK_MV78200_OFF(i),
1006 mvchip->edge_mask_regs[i]);
1007 regmap_write(mvchip->regs,
1008 GPIO_LEVEL_MASK_MV78200_OFF(i),
1009 mvchip->level_mask_regs[i]);
1012 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1013 for (i = 0; i < 4; i++) {
1014 regmap_write(mvchip->regs,
1015 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1016 mvchip->edge_mask_regs[i]);
1017 regmap_write(mvchip->regs,
1018 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1019 mvchip->level_mask_regs[i]);
1026 if (IS_ENABLED(CONFIG_PWM))
1027 mvebu_pwm_resume(mvchip);
1032 static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1033 struct mvebu_gpio_chip *mvchip)
1037 base = devm_platform_ioremap_resource(pdev, 0);
1039 return PTR_ERR(base);
1041 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1042 &mvebu_gpio_regmap_config);
1043 if (IS_ERR(mvchip->regs))
1044 return PTR_ERR(mvchip->regs);
1047 * For the legacy SoCs, the regmap directly maps to the GPIO
1048 * registers, so no offset is needed.
1053 * The Armada XP has a second range of registers for the
1056 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1057 base = devm_platform_ioremap_resource(pdev, 1);
1059 return PTR_ERR(base);
1061 mvchip->percpu_regs =
1062 devm_regmap_init_mmio(&pdev->dev, base,
1063 &mvebu_gpio_regmap_config);
1064 if (IS_ERR(mvchip->percpu_regs))
1065 return PTR_ERR(mvchip->percpu_regs);
1071 static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1072 struct mvebu_gpio_chip *mvchip)
1074 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1075 if (IS_ERR(mvchip->regs))
1076 return PTR_ERR(mvchip->regs);
1078 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1084 static int mvebu_gpio_probe(struct platform_device *pdev)
1086 struct mvebu_gpio_chip *mvchip;
1087 const struct of_device_id *match;
1088 struct device_node *np = pdev->dev.of_node;
1089 struct irq_chip_generic *gc;
1090 struct irq_chip_type *ct;
1091 unsigned int ngpios;
1097 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
1099 soc_variant = (unsigned long) match->data;
1101 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
1103 /* Some gpio controllers do not provide irq support */
1104 err = platform_irq_count(pdev);
1108 have_irqs = err != 0;
1110 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1115 platform_set_drvdata(pdev, mvchip);
1117 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
1118 dev_err(&pdev->dev, "Missing ngpios OF property\n");
1122 id = of_alias_get_id(pdev->dev.of_node, "gpio");
1124 dev_err(&pdev->dev, "Couldn't get OF id\n");
1128 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1129 /* Not all SoCs require a clock.*/
1130 if (!IS_ERR(mvchip->clk))
1131 clk_prepare_enable(mvchip->clk);
1133 mvchip->soc_variant = soc_variant;
1134 mvchip->chip.label = dev_name(&pdev->dev);
1135 mvchip->chip.parent = &pdev->dev;
1136 mvchip->chip.request = gpiochip_generic_request;
1137 mvchip->chip.free = gpiochip_generic_free;
1138 mvchip->chip.get_direction = mvebu_gpio_get_direction;
1139 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1140 mvchip->chip.get = mvebu_gpio_get;
1141 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1142 mvchip->chip.set = mvebu_gpio_set;
1144 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1145 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1146 mvchip->chip.ngpio = ngpios;
1147 mvchip->chip.can_sleep = false;
1148 mvchip->chip.of_node = np;
1149 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1151 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1152 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1154 err = mvebu_gpio_probe_raw(pdev, mvchip);
1160 * Mask and clear GPIO interrupts.
1162 switch (soc_variant) {
1163 case MVEBU_GPIO_SOC_VARIANT_ORION:
1164 case MVEBU_GPIO_SOC_VARIANT_A8K:
1165 regmap_write(mvchip->regs,
1166 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1167 regmap_write(mvchip->regs,
1168 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1169 regmap_write(mvchip->regs,
1170 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1172 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1173 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1174 for (cpu = 0; cpu < 2; cpu++) {
1175 regmap_write(mvchip->regs,
1176 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1177 regmap_write(mvchip->regs,
1178 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1181 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1182 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1183 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1184 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1185 for (cpu = 0; cpu < 4; cpu++) {
1186 regmap_write(mvchip->percpu_regs,
1187 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1188 regmap_write(mvchip->percpu_regs,
1189 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1190 regmap_write(mvchip->percpu_regs,
1191 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1198 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1200 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1201 if (IS_ENABLED(CONFIG_PWM)) {
1202 err = mvebu_pwm_probe(pdev, mvchip, id);
1207 /* Some gpio controllers do not provide irq support */
1212 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
1213 if (!mvchip->domain) {
1214 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1215 mvchip->chip.label);
1220 err = irq_alloc_domain_generic_chips(
1221 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1222 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1224 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1225 mvchip->chip.label);
1230 * NOTE: The common accessors cannot be used because of the percpu
1231 * access to the mask registers
1233 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1234 gc->private = mvchip;
1235 ct = &gc->chip_types[0];
1236 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1237 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1238 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1239 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1240 ct->chip.name = mvchip->chip.label;
1242 ct = &gc->chip_types[1];
1243 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1244 ct->chip.irq_ack = mvebu_gpio_irq_ack;
1245 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1246 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1247 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1248 ct->handler = handle_edge_irq;
1249 ct->chip.name = mvchip->chip.label;
1252 * Setup the interrupt handlers. Each chip can have up to 4
1253 * interrupt handlers, with each handler dealing with 8 GPIO
1256 for (i = 0; i < 4; i++) {
1257 int irq = platform_get_irq_optional(pdev, i);
1261 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1268 irq_domain_remove(mvchip->domain);
1270 pwmchip_remove(&mvchip->mvpwm->chip);
1275 static struct platform_driver mvebu_gpio_driver = {
1277 .name = "mvebu-gpio",
1278 .of_match_table = mvebu_gpio_of_match,
1280 .probe = mvebu_gpio_probe,
1281 .suspend = mvebu_gpio_suspend,
1282 .resume = mvebu_gpio_resume,
1284 builtin_platform_driver(mvebu_gpio_driver);