1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
5 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * Copyright (C) 2016 Freescale Semiconductor Inc.
9 #include <linux/acpi.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/spinlock.h>
15 #include <linux/of_gpio.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/property.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/slab.h>
22 #include <linux/irq.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/bitops.h>
25 #include <linux/interrupt.h>
27 #define MPC8XXX_GPIO_PINS 32
35 #define GPIO_ICR2 0x18
38 struct mpc8xxx_gpio_chip {
43 int (*direction_output)(struct gpio_chip *chip,
44 unsigned offset, int value);
46 struct irq_domain *irq;
51 * This hardware has a big endian bit assignment such that GPIO line 0 is
52 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
53 * This inline helper give the right bitmask for a certain line.
55 static inline u32 mpc_pin2mask(unsigned int offset)
57 return BIT(31 - offset);
60 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
61 * defined as output cannot be determined by reading GPDAT register,
62 * so we use shadow data register instead. The status of input pins
63 * is determined by reading GPDAT register.
65 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
68 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
69 u32 out_mask, out_shadow;
71 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
72 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
73 out_shadow = gc->bgpio_data & out_mask;
75 return !!((val | out_shadow) & mpc_pin2mask(gpio));
78 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
79 unsigned int gpio, int val)
81 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
82 /* GPIO 28..31 are input only on MPC5121 */
86 return mpc8xxx_gc->direction_output(gc, gpio, val);
89 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
90 unsigned int gpio, int val)
92 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
93 /* GPIO 0..3 are input only on MPC5125 */
97 return mpc8xxx_gc->direction_output(gc, gpio, val);
100 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
102 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
104 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
105 return irq_create_mapping(mpc8xxx_gc->irq, offset);
110 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
112 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
113 struct gpio_chip *gc = &mpc8xxx_gc->gc;
117 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
118 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
119 for_each_set_bit(i, &mask, 32)
120 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
125 static void mpc8xxx_irq_unmask(struct irq_data *d)
127 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
128 struct gpio_chip *gc = &mpc8xxx_gc->gc;
131 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
133 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
134 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
135 | mpc_pin2mask(irqd_to_hwirq(d)));
137 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
140 static void mpc8xxx_irq_mask(struct irq_data *d)
142 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
143 struct gpio_chip *gc = &mpc8xxx_gc->gc;
146 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
148 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
149 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
150 & ~mpc_pin2mask(irqd_to_hwirq(d)));
152 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
155 static void mpc8xxx_irq_ack(struct irq_data *d)
157 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
158 struct gpio_chip *gc = &mpc8xxx_gc->gc;
160 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
161 mpc_pin2mask(irqd_to_hwirq(d)));
164 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
166 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
167 struct gpio_chip *gc = &mpc8xxx_gc->gc;
171 case IRQ_TYPE_EDGE_FALLING:
172 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
173 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
174 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
175 | mpc_pin2mask(irqd_to_hwirq(d)));
176 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
179 case IRQ_TYPE_EDGE_BOTH:
180 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
181 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
182 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
183 & ~mpc_pin2mask(irqd_to_hwirq(d)));
184 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
194 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
196 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
197 struct gpio_chip *gc = &mpc8xxx_gc->gc;
198 unsigned long gpio = irqd_to_hwirq(d);
204 reg = mpc8xxx_gc->regs + GPIO_ICR;
205 shift = (15 - gpio) * 2;
207 reg = mpc8xxx_gc->regs + GPIO_ICR2;
208 shift = (15 - (gpio % 16)) * 2;
212 case IRQ_TYPE_EDGE_FALLING:
213 case IRQ_TYPE_LEVEL_LOW:
214 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
215 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
217 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
220 case IRQ_TYPE_EDGE_RISING:
221 case IRQ_TYPE_LEVEL_HIGH:
222 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
223 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
225 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
228 case IRQ_TYPE_EDGE_BOTH:
229 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
230 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
231 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
241 static struct irq_chip mpc8xxx_irq_chip = {
242 .name = "mpc8xxx-gpio",
243 .irq_unmask = mpc8xxx_irq_unmask,
244 .irq_mask = mpc8xxx_irq_mask,
245 .irq_ack = mpc8xxx_irq_ack,
246 /* this might get overwritten in mpc8xxx_probe() */
247 .irq_set_type = mpc8xxx_irq_set_type,
250 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
251 irq_hw_number_t hwirq)
253 irq_set_chip_data(irq, h->host_data);
254 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
259 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
260 .map = mpc8xxx_gpio_irq_map,
261 .xlate = irq_domain_xlate_twocell,
264 struct mpc8xxx_gpio_devtype {
265 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
266 int (*gpio_get)(struct gpio_chip *, unsigned int);
267 int (*irq_set_type)(struct irq_data *, unsigned int);
270 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
271 .gpio_dir_out = mpc5121_gpio_dir_out,
272 .irq_set_type = mpc512x_irq_set_type,
275 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
276 .gpio_dir_out = mpc5125_gpio_dir_out,
277 .irq_set_type = mpc512x_irq_set_type,
280 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
281 .gpio_get = mpc8572_gpio_get,
284 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
285 .irq_set_type = mpc8xxx_irq_set_type,
288 static const struct of_device_id mpc8xxx_gpio_ids[] = {
289 { .compatible = "fsl,mpc8349-gpio", },
290 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
291 { .compatible = "fsl,mpc8610-gpio", },
292 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
293 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
294 { .compatible = "fsl,pq3-gpio", },
295 { .compatible = "fsl,ls1028a-gpio", },
296 { .compatible = "fsl,ls1088a-gpio", },
297 { .compatible = "fsl,qoriq-gpio", },
301 static int mpc8xxx_probe(struct platform_device *pdev)
303 struct device_node *np = pdev->dev.of_node;
304 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
305 struct gpio_chip *gc;
306 const struct mpc8xxx_gpio_devtype *devtype = NULL;
307 struct fwnode_handle *fwnode;
310 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
314 platform_set_drvdata(pdev, mpc8xxx_gc);
316 raw_spin_lock_init(&mpc8xxx_gc->lock);
318 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
319 if (IS_ERR(mpc8xxx_gc->regs))
320 return PTR_ERR(mpc8xxx_gc->regs);
322 gc = &mpc8xxx_gc->gc;
323 gc->parent = &pdev->dev;
325 if (device_property_read_bool(&pdev->dev, "little-endian")) {
326 ret = bgpio_init(gc, &pdev->dev, 4,
327 mpc8xxx_gc->regs + GPIO_DAT,
329 mpc8xxx_gc->regs + GPIO_DIR, NULL,
333 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
335 ret = bgpio_init(gc, &pdev->dev, 4,
336 mpc8xxx_gc->regs + GPIO_DAT,
338 mpc8xxx_gc->regs + GPIO_DIR, NULL,
340 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
343 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
346 mpc8xxx_gc->direction_output = gc->direction_output;
348 devtype = device_get_match_data(&pdev->dev);
350 devtype = &mpc8xxx_gpio_devtype_default;
353 * It's assumed that only a single type of gpio controller is available
354 * on the current machine, so overwriting global data is fine.
356 if (devtype->irq_set_type)
357 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
359 if (devtype->gpio_dir_out)
360 gc->direction_output = devtype->gpio_dir_out;
361 if (devtype->gpio_get)
362 gc->get = devtype->gpio_get;
364 gc->to_irq = mpc8xxx_gpio_to_irq;
367 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
368 * the input enable of each individual GPIO port. When an individual
369 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
370 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
371 * the port value to the GPIO Data Register.
373 fwnode = dev_fwnode(&pdev->dev);
374 if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
375 of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
376 of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
377 is_acpi_node(fwnode))
378 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
380 ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
383 "GPIO chip registration failed with status %d\n", ret);
387 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
388 if (mpc8xxx_gc->irqn < 0)
389 return mpc8xxx_gc->irqn;
391 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
393 &mpc8xxx_gpio_irq_ops,
396 if (!mpc8xxx_gc->irq)
399 /* ack and mask all irqs */
400 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
401 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
403 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
404 mpc8xxx_gpio_irq_cascade,
405 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
409 "failed to devm_request_irq(%d), ret = %d\n",
410 mpc8xxx_gc->irqn, ret);
416 irq_domain_remove(mpc8xxx_gc->irq);
420 static int mpc8xxx_remove(struct platform_device *pdev)
422 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
424 if (mpc8xxx_gc->irq) {
425 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
426 irq_domain_remove(mpc8xxx_gc->irq);
433 static const struct acpi_device_id gpio_acpi_ids[] = {
437 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
440 static struct platform_driver mpc8xxx_plat_driver = {
441 .probe = mpc8xxx_probe,
442 .remove = mpc8xxx_remove,
444 .name = "gpio-mpc8xxx",
445 .of_match_table = mpc8xxx_gpio_ids,
446 .acpi_match_table = ACPI_PTR(gpio_acpi_ids),
450 static int __init mpc8xxx_init(void)
452 return platform_driver_register(&mpc8xxx_plat_driver);
455 arch_initcall(mpc8xxx_init);