2 * Generic driver for memory-mapped GPIO controllers.
4 * Copyright 2008 MontaVista Software, Inc.
5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
14 * ..The simplest form of a GPIO controller that the driver supports is``
15 * `.just a single "data" register, where GPIO state can be read and/or `
16 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
19 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
20 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
21 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
22 `....trivial..'~`.```.```
24 * .```````~~~~`..`.``.``.
25 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
26 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
27 * . register the device with -be`. .with a pair of set/clear-bit registers ,
28 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
29 * ``.`.``...``` ```.. output pins are also supported.`
30 * ^^ `````.`````````.,``~``~``~~``````
32 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
33 * .. The expectation is that in at least some cases . ,-~~~-,
34 * .this will be used with roll-your-own ASIC/FPGA .` \ /
35 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
36 * ..````````......``````````` \o_
40 * ...`````~~`.....``.`..........``````.`.``.```........``.
41 * ` 8, 16, 32 and 64 bits registers are supported, and``.
42 * . the number of GPIOs is determined by the width of ~
43 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
47 #include <linux/init.h>
48 #include <linux/err.h>
49 #include <linux/bug.h>
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/spinlock.h>
53 #include <linux/compiler.h>
54 #include <linux/types.h>
55 #include <linux/errno.h>
56 #include <linux/log2.h>
57 #include <linux/ioport.h>
59 #include <linux/gpio/driver.h>
60 #include <linux/slab.h>
61 #include <linux/bitops.h>
62 #include <linux/platform_device.h>
63 #include <linux/mod_devicetable.h>
65 #include <linux/of_device.h>
67 static void bgpio_write8(void __iomem *reg, unsigned long data)
72 static unsigned long bgpio_read8(void __iomem *reg)
77 static void bgpio_write16(void __iomem *reg, unsigned long data)
82 static unsigned long bgpio_read16(void __iomem *reg)
87 static void bgpio_write32(void __iomem *reg, unsigned long data)
92 static unsigned long bgpio_read32(void __iomem *reg)
97 #if BITS_PER_LONG >= 64
98 static void bgpio_write64(void __iomem *reg, unsigned long data)
103 static unsigned long bgpio_read64(void __iomem *reg)
107 #endif /* BITS_PER_LONG >= 64 */
109 static void bgpio_write16be(void __iomem *reg, unsigned long data)
111 iowrite16be(data, reg);
114 static unsigned long bgpio_read16be(void __iomem *reg)
116 return ioread16be(reg);
119 static void bgpio_write32be(void __iomem *reg, unsigned long data)
121 iowrite32be(data, reg);
124 static unsigned long bgpio_read32be(void __iomem *reg)
126 return ioread32be(reg);
129 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
132 return BIT(gc->bgpio_bits - 1 - line);
136 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
138 unsigned long pinmask = bgpio_line2mask(gc, gpio);
140 if (gc->bgpio_dir & pinmask)
141 return !!(gc->read_reg(gc->reg_set) & pinmask);
143 return !!(gc->read_reg(gc->reg_dat) & pinmask);
147 * This assumes that the bits in the GPIO register are in native endianness.
148 * We only assign the function pointer if we have that.
150 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
153 unsigned long get_mask = 0;
154 unsigned long set_mask = 0;
156 /* Make sure we first clear any bits that are zero when we read the register */
159 /* Exploit the fact that we know which directions are set */
160 set_mask = *mask & gc->bgpio_dir;
161 get_mask = *mask & ~gc->bgpio_dir;
164 *bits |= gc->read_reg(gc->reg_set) & set_mask;
166 *bits |= gc->read_reg(gc->reg_dat) & get_mask;
171 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
173 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
177 * This only works if the bits in the GPIO register are in native endianness.
179 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
182 /* Make sure we first clear any bits that are zero when we read the register */
184 *bits |= gc->read_reg(gc->reg_dat) & *mask;
189 * With big endian mirrored bit order it becomes more tedious.
191 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
194 unsigned long readmask = 0;
198 /* Make sure we first clear any bits that are zero when we read the register */
201 /* Create a mirrored mask */
203 while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio)
204 readmask |= bgpio_line2mask(gc, bit);
206 /* Read the register */
207 val = gc->read_reg(gc->reg_dat) & readmask;
210 * Mirror the result into the "bits" result, this will give line 0
211 * in bit 0 ... line 31 in bit 31 for a 32bit register.
214 while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio)
215 *bits |= bgpio_line2mask(gc, bit);
220 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
224 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
226 unsigned long mask = bgpio_line2mask(gc, gpio);
229 spin_lock_irqsave(&gc->bgpio_lock, flags);
232 gc->bgpio_data |= mask;
234 gc->bgpio_data &= ~mask;
236 gc->write_reg(gc->reg_dat, gc->bgpio_data);
238 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
241 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
244 unsigned long mask = bgpio_line2mask(gc, gpio);
247 gc->write_reg(gc->reg_set, mask);
249 gc->write_reg(gc->reg_clr, mask);
252 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
254 unsigned long mask = bgpio_line2mask(gc, gpio);
257 spin_lock_irqsave(&gc->bgpio_lock, flags);
260 gc->bgpio_data |= mask;
262 gc->bgpio_data &= ~mask;
264 gc->write_reg(gc->reg_set, gc->bgpio_data);
266 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
269 static void bgpio_multiple_get_masks(struct gpio_chip *gc,
270 unsigned long *mask, unsigned long *bits,
271 unsigned long *set_mask,
272 unsigned long *clear_mask)
279 for (i = 0; i < gc->bgpio_bits; i++) {
282 if (__test_and_clear_bit(i, mask)) {
283 if (test_bit(i, bits))
284 *set_mask |= bgpio_line2mask(gc, i);
286 *clear_mask |= bgpio_line2mask(gc, i);
291 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
297 unsigned long set_mask, clear_mask;
299 spin_lock_irqsave(&gc->bgpio_lock, flags);
301 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
303 gc->bgpio_data |= set_mask;
304 gc->bgpio_data &= ~clear_mask;
306 gc->write_reg(reg, gc->bgpio_data);
308 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
311 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
314 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
317 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
320 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
323 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
327 unsigned long set_mask, clear_mask;
329 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
332 gc->write_reg(gc->reg_set, set_mask);
334 gc->write_reg(gc->reg_clr, clear_mask);
337 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
342 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
348 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
351 gc->set(gc, gpio, val);
356 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
360 spin_lock_irqsave(&gc->bgpio_lock, flags);
362 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
363 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
365 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
370 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
372 /* Return 0 if output, 1 of input */
373 return !(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
376 static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
380 gc->set(gc, gpio, val);
382 spin_lock_irqsave(&gc->bgpio_lock, flags);
384 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
385 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
387 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
392 static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
396 spin_lock_irqsave(&gc->bgpio_lock, flags);
398 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
399 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
401 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
406 static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
410 gc->set(gc, gpio, val);
412 spin_lock_irqsave(&gc->bgpio_lock, flags);
414 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
415 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
417 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
422 static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
424 /* Return 0 if output, 1 if input */
425 return !!(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
428 static int bgpio_setup_accessors(struct device *dev,
429 struct gpio_chip *gc,
433 switch (gc->bgpio_bits) {
435 gc->read_reg = bgpio_read8;
436 gc->write_reg = bgpio_write8;
440 gc->read_reg = bgpio_read16be;
441 gc->write_reg = bgpio_write16be;
443 gc->read_reg = bgpio_read16;
444 gc->write_reg = bgpio_write16;
449 gc->read_reg = bgpio_read32be;
450 gc->write_reg = bgpio_write32be;
452 gc->read_reg = bgpio_read32;
453 gc->write_reg = bgpio_write32;
456 #if BITS_PER_LONG >= 64
460 "64 bit big endian byte order unsupported\n");
463 gc->read_reg = bgpio_read64;
464 gc->write_reg = bgpio_write64;
467 #endif /* BITS_PER_LONG >= 64 */
469 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
477 * Create the device and allocate the resources. For setting GPIO's there are
478 * three supported configurations:
480 * - single input/output register resource (named "dat").
481 * - set/clear pair (named "set" and "clr").
482 * - single output register resource and single input resource ("set" and
485 * For the single output register, this drives a 1 by setting a bit and a zero
486 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
487 * in the set register and clears it by setting a bit in the clear register.
488 * The configuration is detected by which resources are present.
490 * For setting the GPIO direction, there are three supported configurations:
492 * - simple bidirection GPIO that requires no configuration.
493 * - an output direction register (named "dirout") where a 1 bit
494 * indicates the GPIO is an output.
495 * - an input direction register (named "dirin") where a 1 bit indicates
496 * the GPIO is an input.
498 static int bgpio_setup_io(struct gpio_chip *gc,
512 gc->set = bgpio_set_with_clear;
513 gc->set_multiple = bgpio_set_multiple_with_clear;
514 } else if (set && !clr) {
516 gc->set = bgpio_set_set;
517 gc->set_multiple = bgpio_set_multiple_set;
518 } else if (flags & BGPIOF_NO_OUTPUT) {
519 gc->set = bgpio_set_none;
520 gc->set_multiple = NULL;
523 gc->set_multiple = bgpio_set_multiple;
526 if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
527 (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
528 gc->get = bgpio_get_set;
530 gc->get_multiple = bgpio_get_set_multiple;
532 * We deliberately avoid assigning the ->get_multiple() call
533 * for big endian mirrored registers which are ALSO reflecting
534 * their value in the set register when used as output. It is
535 * simply too much complexity, let the GPIO core fall back to
536 * reading each line individually in that fringe case.
541 gc->get_multiple = bgpio_get_multiple_be;
543 gc->get_multiple = bgpio_get_multiple;
549 static int bgpio_setup_direction(struct gpio_chip *gc,
550 void __iomem *dirout,
554 if (dirout && dirin) {
557 gc->reg_dir = dirout;
558 gc->direction_output = bgpio_dir_out;
559 gc->direction_input = bgpio_dir_in;
560 gc->get_direction = bgpio_get_dir;
563 gc->direction_output = bgpio_dir_out_inv;
564 gc->direction_input = bgpio_dir_in_inv;
565 gc->get_direction = bgpio_get_dir_inv;
567 if (flags & BGPIOF_NO_OUTPUT)
568 gc->direction_output = bgpio_dir_out_err;
570 gc->direction_output = bgpio_simple_dir_out;
571 gc->direction_input = bgpio_simple_dir_in;
577 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
579 if (gpio_pin < chip->ngpio)
585 int bgpio_init(struct gpio_chip *gc, struct device *dev,
586 unsigned long sz, void __iomem *dat, void __iomem *set,
587 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
592 if (!is_power_of_2(sz))
595 gc->bgpio_bits = sz * 8;
596 if (gc->bgpio_bits > BITS_PER_LONG)
599 spin_lock_init(&gc->bgpio_lock);
601 gc->label = dev_name(dev);
603 gc->ngpio = gc->bgpio_bits;
604 gc->request = bgpio_request;
605 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
607 ret = bgpio_setup_io(gc, dat, set, clr, flags);
611 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
615 ret = bgpio_setup_direction(gc, dirout, dirin, flags);
619 gc->bgpio_data = gc->read_reg(gc->reg_dat);
620 if (gc->set == bgpio_set_set &&
621 !(flags & BGPIOF_UNREADABLE_REG_SET))
622 gc->bgpio_data = gc->read_reg(gc->reg_set);
623 if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
624 gc->bgpio_dir = gc->read_reg(gc->reg_dir);
628 EXPORT_SYMBOL_GPL(bgpio_init);
630 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
632 static void __iomem *bgpio_map(struct platform_device *pdev,
634 resource_size_t sane_sz)
639 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
643 sz = resource_size(r);
645 return IOMEM_ERR_PTR(-EINVAL);
647 return devm_ioremap_resource(&pdev->dev, r);
651 static const struct of_device_id bgpio_of_match[] = {
652 { .compatible = "brcm,bcm6345-gpio" },
653 { .compatible = "wd,mbl-gpio" },
654 { .compatible = "ni,169445-nand-gpio" },
657 MODULE_DEVICE_TABLE(of, bgpio_of_match);
659 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
660 unsigned long *flags)
662 struct bgpio_pdata *pdata;
664 if (!of_match_device(bgpio_of_match, &pdev->dev))
667 pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
670 return ERR_PTR(-ENOMEM);
674 if (of_device_is_big_endian(pdev->dev.of_node))
675 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
677 if (of_property_read_bool(pdev->dev.of_node, "no-output"))
678 *flags |= BGPIOF_NO_OUTPUT;
683 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
684 unsigned long *flags)
688 #endif /* CONFIG_OF */
690 static int bgpio_pdev_probe(struct platform_device *pdev)
692 struct device *dev = &pdev->dev;
697 void __iomem *dirout;
700 unsigned long flags = 0;
702 struct gpio_chip *gc;
703 struct bgpio_pdata *pdata;
705 pdata = bgpio_parse_dt(pdev, &flags);
707 return PTR_ERR(pdata);
710 pdata = dev_get_platdata(dev);
711 flags = pdev->id_entry->driver_data;
714 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
718 sz = resource_size(r);
720 dat = bgpio_map(pdev, "dat", sz);
724 set = bgpio_map(pdev, "set", sz);
728 clr = bgpio_map(pdev, "clr", sz);
732 dirout = bgpio_map(pdev, "dirout", sz);
734 return PTR_ERR(dirout);
736 dirin = bgpio_map(pdev, "dirin", sz);
738 return PTR_ERR(dirin);
740 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
744 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
750 gc->label = pdata->label;
751 gc->base = pdata->base;
752 if (pdata->ngpio > 0)
753 gc->ngpio = pdata->ngpio;
756 platform_set_drvdata(pdev, gc);
758 return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
761 static const struct platform_device_id bgpio_id_table[] = {
763 .name = "basic-mmio-gpio",
766 .name = "basic-mmio-gpio-be",
767 .driver_data = BGPIOF_BIG_ENDIAN,
771 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
773 static struct platform_driver bgpio_driver = {
775 .name = "basic-mmio-gpio",
776 .of_match_table = of_match_ptr(bgpio_of_match),
778 .id_table = bgpio_id_table,
779 .probe = bgpio_pdev_probe,
782 module_platform_driver(bgpio_driver);
784 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
786 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
787 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
788 MODULE_LICENSE("GPL");