1 // SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause
2 /* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */
4 #include <linux/bitfield.h>
5 #include <linux/bitops.h>
6 #include <linux/device.h>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/spinlock.h>
14 #include <linux/types.h>
17 * There are 2 YU GPIO blocks:
18 * gpio[0]: HOST_GPIO0->HOST_GPIO31
19 * gpio[1]: HOST_GPIO32->HOST_GPIO55
21 #define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32
24 * fw_gpio[x] block registers and their offset
26 #define MLXBF_GPIO_FW_OUTPUT_ENABLE_SET 0x00
27 #define MLXBF_GPIO_FW_DATA_OUT_SET 0x04
29 #define MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR 0x00
30 #define MLXBF_GPIO_FW_DATA_OUT_CLEAR 0x04
32 #define MLXBF_GPIO_CAUSE_RISE_EN 0x00
33 #define MLXBF_GPIO_CAUSE_FALL_EN 0x04
34 #define MLXBF_GPIO_READ_DATA_IN 0x08
36 #define MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x00
37 #define MLXBF_GPIO_CAUSE_OR_EVTEN0 0x14
38 #define MLXBF_GPIO_CAUSE_OR_CLRCAUSE 0x18
40 struct mlxbf3_gpio_context {
43 /* YU GPIO block address */
44 void __iomem *gpio_set_io;
45 void __iomem *gpio_clr_io;
46 void __iomem *gpio_io;
48 /* YU GPIO cause block address */
49 void __iomem *gpio_cause_io;
52 static void mlxbf3_gpio_irq_enable(struct irq_data *irqd)
54 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
55 struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
56 irq_hw_number_t offset = irqd_to_hwirq(irqd);
60 gpiochip_enable_irq(gc, offset);
62 raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
63 writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
65 val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
67 writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
68 raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
71 static void mlxbf3_gpio_irq_disable(struct irq_data *irqd)
73 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
74 struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
75 irq_hw_number_t offset = irqd_to_hwirq(irqd);
79 raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
80 val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
82 writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
83 raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
85 gpiochip_disable_irq(gc, offset);
88 static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr)
90 struct mlxbf3_gpio_context *gs = ptr;
91 struct gpio_chip *gc = &gs->gc;
92 unsigned long pending;
95 pending = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0);
96 writel(pending, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
98 for_each_set_bit(level, &pending, gc->ngpio)
99 generic_handle_domain_irq(gc->irq.domain, level);
101 return IRQ_RETVAL(pending);
105 mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
107 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
108 struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
109 irq_hw_number_t offset = irqd_to_hwirq(irqd);
113 raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
115 switch (type & IRQ_TYPE_SENSE_MASK) {
116 case IRQ_TYPE_EDGE_BOTH:
117 val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
119 writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
120 val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
122 writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
124 case IRQ_TYPE_EDGE_RISING:
125 val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
127 writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
129 case IRQ_TYPE_EDGE_FALLING:
130 val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
132 writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
135 raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
139 raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
141 irq_set_handler_locked(irqd, handle_edge_irq);
146 /* This function needs to be defined for handle_edge_irq() */
147 static void mlxbf3_gpio_irq_ack(struct irq_data *data)
151 static const struct irq_chip gpio_mlxbf3_irqchip = {
153 .irq_ack = mlxbf3_gpio_irq_ack,
154 .irq_set_type = mlxbf3_gpio_irq_set_type,
155 .irq_enable = mlxbf3_gpio_irq_enable,
156 .irq_disable = mlxbf3_gpio_irq_disable,
157 .flags = IRQCHIP_IMMUTABLE,
158 GPIOCHIP_IRQ_RESOURCE_HELPERS,
161 static int mlxbf3_gpio_probe(struct platform_device *pdev)
163 struct device *dev = &pdev->dev;
164 struct mlxbf3_gpio_context *gs;
165 struct gpio_irq_chip *girq;
166 struct gpio_chip *gc;
169 gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
173 gs->gpio_io = devm_platform_ioremap_resource(pdev, 0);
174 if (IS_ERR(gs->gpio_io))
175 return PTR_ERR(gs->gpio_io);
177 gs->gpio_cause_io = devm_platform_ioremap_resource(pdev, 1);
178 if (IS_ERR(gs->gpio_cause_io))
179 return PTR_ERR(gs->gpio_cause_io);
181 gs->gpio_set_io = devm_platform_ioremap_resource(pdev, 2);
182 if (IS_ERR(gs->gpio_set_io))
183 return PTR_ERR(gs->gpio_set_io);
185 gs->gpio_clr_io = devm_platform_ioremap_resource(pdev, 3);
186 if (IS_ERR(gs->gpio_clr_io))
187 return PTR_ERR(gs->gpio_clr_io);
190 ret = bgpio_init(gc, dev, 4,
191 gs->gpio_io + MLXBF_GPIO_READ_DATA_IN,
192 gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET,
193 gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR,
194 gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET,
195 gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0);
197 gc->request = gpiochip_generic_request;
198 gc->free = gpiochip_generic_free;
199 gc->owner = THIS_MODULE;
201 irq = platform_get_irq(pdev, 0);
204 gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip);
205 girq->default_type = IRQ_TYPE_NONE;
206 /* This will let us handle the parent IRQ in the driver */
207 girq->num_parents = 0;
208 girq->parents = NULL;
209 girq->parent_handler = NULL;
210 girq->handler = handle_bad_irq;
213 * Directly request the irq here instead of passing
214 * a flow-handler because the irq is shared.
216 ret = devm_request_irq(dev, irq, mlxbf3_gpio_irq_handler,
217 IRQF_SHARED, dev_name(dev), gs);
219 return dev_err_probe(dev, ret, "failed to request IRQ");
222 platform_set_drvdata(pdev, gs);
224 ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
226 dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n");
231 static const struct acpi_device_id mlxbf3_gpio_acpi_match[] = {
235 MODULE_DEVICE_TABLE(acpi, mlxbf3_gpio_acpi_match);
237 static struct platform_driver mlxbf3_gpio_driver = {
239 .name = "mlxbf3_gpio",
240 .acpi_match_table = mlxbf3_gpio_acpi_match,
242 .probe = mlxbf3_gpio_probe,
244 module_platform_driver(mlxbf3_gpio_driver);
246 MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver");
247 MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
248 MODULE_LICENSE("Dual BSD/GPL");