2 * Moorestown platform Langwell chip GPIO driver
4 * Copyright (c) 2008, 2009, 2013, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * Moorestown platform Langwell chip.
22 * Medfield platform Penwell chip.
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/platform_device.h>
28 #include <linux/kernel.h>
29 #include <linux/delay.h>
30 #include <linux/stddef.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/irq.h>
35 #include <linux/gpio.h>
36 #include <linux/slab.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/irqdomain.h>
41 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
42 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
43 * registers to control them, so we only define the order here instead of a
44 * structure, to get a bit offset for a pin (use GPDR as an example):
49 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
51 * so the bit of reg_addr is to control pin offset's GPDR feature
55 GPLR = 0, /* pin level read-only */
56 GPDR, /* pin direction */
59 GRER, /* rising edge detect */
60 GFER, /* falling edge detect */
61 GEDR, /* edge detect result */
62 GAFR, /* alt function */
66 struct gpio_chip chip;
67 void __iomem *reg_base;
70 struct irq_domain *domain;
73 #define to_lnw_priv(chip) container_of(chip, struct lnw_gpio, chip)
75 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
76 enum GPIO_REG reg_type)
78 struct lnw_gpio *lnw = to_lnw_priv(chip);
79 unsigned nreg = chip->ngpio / 32;
82 return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
85 static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
86 enum GPIO_REG reg_type)
88 struct lnw_gpio *lnw = to_lnw_priv(chip);
89 unsigned nreg = chip->ngpio / 32;
92 return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
95 static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
97 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
98 u32 value = readl(gafr);
99 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
102 value &= ~(3 << shift);
108 static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
110 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
112 return readl(gplr) & BIT(offset % 32);
115 static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
117 void __iomem *gpsr, *gpcr;
120 gpsr = gpio_reg(chip, offset, GPSR);
121 writel(BIT(offset % 32), gpsr);
123 gpcr = gpio_reg(chip, offset, GPCR);
124 writel(BIT(offset % 32), gpcr);
128 static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
130 struct lnw_gpio *lnw = to_lnw_priv(chip);
131 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
136 pm_runtime_get(&lnw->pdev->dev);
138 spin_lock_irqsave(&lnw->lock, flags);
140 value &= ~BIT(offset % 32);
142 spin_unlock_irqrestore(&lnw->lock, flags);
145 pm_runtime_put(&lnw->pdev->dev);
150 static int lnw_gpio_direction_output(struct gpio_chip *chip,
151 unsigned offset, int value)
153 struct lnw_gpio *lnw = to_lnw_priv(chip);
154 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
157 lnw_gpio_set(chip, offset, value);
160 pm_runtime_get(&lnw->pdev->dev);
162 spin_lock_irqsave(&lnw->lock, flags);
164 value |= BIT(offset % 32);
166 spin_unlock_irqrestore(&lnw->lock, flags);
169 pm_runtime_put(&lnw->pdev->dev);
174 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
176 struct lnw_gpio *lnw = to_lnw_priv(chip);
177 return irq_create_mapping(lnw->domain, offset);
180 static int lnw_irq_type(struct irq_data *d, unsigned type)
182 struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
183 u32 gpio = irqd_to_hwirq(d);
186 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
187 void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
189 if (gpio >= lnw->chip.ngpio)
193 pm_runtime_get(&lnw->pdev->dev);
195 spin_lock_irqsave(&lnw->lock, flags);
196 if (type & IRQ_TYPE_EDGE_RISING)
197 value = readl(grer) | BIT(gpio % 32);
199 value = readl(grer) & (~BIT(gpio % 32));
202 if (type & IRQ_TYPE_EDGE_FALLING)
203 value = readl(gfer) | BIT(gpio % 32);
205 value = readl(gfer) & (~BIT(gpio % 32));
207 spin_unlock_irqrestore(&lnw->lock, flags);
210 pm_runtime_put(&lnw->pdev->dev);
215 static void lnw_irq_unmask(struct irq_data *d)
219 static void lnw_irq_mask(struct irq_data *d)
223 static struct irq_chip lnw_irqchip = {
225 .irq_mask = lnw_irq_mask,
226 .irq_unmask = lnw_irq_unmask,
227 .irq_set_type = lnw_irq_type,
230 static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
231 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
232 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
233 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
234 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), .driver_data = 96 },
235 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), .driver_data = 96 },
238 MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
240 static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
242 struct irq_data *data = irq_desc_get_irq_data(desc);
243 struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
244 struct irq_chip *chip = irq_data_get_irq_chip(data);
245 u32 base, gpio, mask;
246 unsigned long pending;
249 /* check GPIO controller to check which pin triggered the interrupt */
250 for (base = 0; base < lnw->chip.ngpio; base += 32) {
251 gedr = gpio_reg(&lnw->chip, base, GEDR);
252 while ((pending = readl(gedr))) {
253 gpio = __ffs(pending);
255 /* Clear before handling so we can't lose an edge */
257 generic_handle_irq(irq_find_mapping(lnw->domain,
265 static void lnw_irq_init_hw(struct lnw_gpio *lnw)
270 for (base = 0; base < lnw->chip.ngpio; base += 32) {
271 /* Clear the rising-edge detect register */
272 reg = gpio_reg(&lnw->chip, base, GRER);
274 /* Clear the falling-edge detect register */
275 reg = gpio_reg(&lnw->chip, base, GFER);
277 /* Clear the edge detect status register */
278 reg = gpio_reg(&lnw->chip, base, GEDR);
283 static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
286 struct lnw_gpio *lnw = d->host_data;
288 irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
290 irq_set_chip_data(virq, lnw);
291 irq_set_irq_type(virq, IRQ_TYPE_NONE);
296 static const struct irq_domain_ops lnw_gpio_irq_ops = {
297 .map = lnw_gpio_irq_map,
298 .xlate = irq_domain_xlate_twocell,
301 static int lnw_gpio_runtime_idle(struct device *dev)
303 pm_schedule_suspend(dev, 500);
307 static const struct dev_pm_ops lnw_gpio_pm_ops = {
308 SET_RUNTIME_PM_OPS(NULL, NULL, lnw_gpio_runtime_idle)
311 static int lnw_gpio_probe(struct pci_dev *pdev,
312 const struct pci_device_id *id)
315 struct lnw_gpio *lnw;
319 int ngpio = id->driver_data;
321 retval = pcim_enable_device(pdev);
325 retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
327 dev_err(&pdev->dev, "I/O memory mapping error\n");
331 base = pcim_iomap_table(pdev)[1];
333 irq_base = readl(base);
334 gpio_base = readl(sizeof(u32) + base);
336 /* release the IO mapping, since we already get the info from bar1 */
337 pcim_iounmap_regions(pdev, 1 << 1);
339 lnw = devm_kzalloc(&pdev->dev, sizeof(*lnw), GFP_KERNEL);
341 dev_err(&pdev->dev, "can't allocate chip data\n");
345 lnw->reg_base = pcim_iomap_table(pdev)[0];
346 lnw->chip.label = dev_name(&pdev->dev);
347 lnw->chip.request = lnw_gpio_request;
348 lnw->chip.direction_input = lnw_gpio_direction_input;
349 lnw->chip.direction_output = lnw_gpio_direction_output;
350 lnw->chip.get = lnw_gpio_get;
351 lnw->chip.set = lnw_gpio_set;
352 lnw->chip.to_irq = lnw_gpio_to_irq;
353 lnw->chip.base = gpio_base;
354 lnw->chip.ngpio = ngpio;
355 lnw->chip.can_sleep = 0;
358 spin_lock_init(&lnw->lock);
360 lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ngpio, irq_base,
361 &lnw_gpio_irq_ops, lnw);
365 pci_set_drvdata(pdev, lnw);
366 retval = gpiochip_add(&lnw->chip);
368 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
372 lnw_irq_init_hw(lnw);
374 irq_set_handler_data(pdev->irq, lnw);
375 irq_set_chained_handler(pdev->irq, lnw_irq_handler);
377 pm_runtime_put_noidle(&pdev->dev);
378 pm_runtime_allow(&pdev->dev);
383 static struct pci_driver lnw_gpio_driver = {
384 .name = "langwell_gpio",
385 .id_table = lnw_gpio_ids,
386 .probe = lnw_gpio_probe,
388 .pm = &lnw_gpio_pm_ops,
392 static int __init lnw_gpio_init(void)
394 return pci_register_driver(&lnw_gpio_driver);
397 device_initcall(lnw_gpio_init);