1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011 Jamie Iles
5 * All enquiries to support@picochip.com
7 #include <linux/acpi.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
19 #include <linux/platform_data/gpio-dwapb.h>
20 #include <linux/platform_device.h>
21 #include <linux/property.h>
22 #include <linux/reset.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
27 #include "gpiolib-acpi.h"
29 #define GPIO_SWPORTA_DR 0x00
30 #define GPIO_SWPORTA_DDR 0x04
31 #define GPIO_SWPORTB_DR 0x0c
32 #define GPIO_SWPORTB_DDR 0x10
33 #define GPIO_SWPORTC_DR 0x18
34 #define GPIO_SWPORTC_DDR 0x1c
35 #define GPIO_SWPORTD_DR 0x24
36 #define GPIO_SWPORTD_DDR 0x28
37 #define GPIO_INTEN 0x30
38 #define GPIO_INTMASK 0x34
39 #define GPIO_INTTYPE_LEVEL 0x38
40 #define GPIO_INT_POLARITY 0x3c
41 #define GPIO_INTSTATUS 0x40
42 #define GPIO_PORTA_DEBOUNCE 0x48
43 #define GPIO_PORTA_EOI 0x4c
44 #define GPIO_EXT_PORTA 0x50
45 #define GPIO_EXT_PORTB 0x54
46 #define GPIO_EXT_PORTC 0x58
47 #define GPIO_EXT_PORTD 0x5c
49 #define DWAPB_DRIVER_NAME "gpio-dwapb"
50 #define DWAPB_MAX_PORTS 4
52 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
53 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
54 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
56 #define GPIO_REG_OFFSET_V2 1
58 #define GPIO_INTMASK_V2 0x44
59 #define GPIO_INTTYPE_LEVEL_V2 0x34
60 #define GPIO_INT_POLARITY_V2 0x38
61 #define GPIO_INTSTATUS_V2 0x3c
62 #define GPIO_PORTA_EOI_V2 0x40
64 #define DWAPB_NR_CLOCKS 2
68 #ifdef CONFIG_PM_SLEEP
69 /* Store GPIO context across system-wide suspend/resume transitions */
70 struct dwapb_context {
83 struct dwapb_gpio_port_irqchip {
84 struct irq_chip irqchip;
86 unsigned int irq[DWAPB_MAX_GPIOS];
89 struct dwapb_gpio_port {
91 struct dwapb_gpio_port_irqchip *pirq;
92 struct dwapb_gpio *gpio;
93 #ifdef CONFIG_PM_SLEEP
94 struct dwapb_context *ctx;
98 #define to_dwapb_gpio(_gc) \
99 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
104 struct dwapb_gpio_port *ports;
105 unsigned int nr_ports;
107 struct reset_control *rst;
108 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
111 static inline u32 gpio_reg_v2_convert(unsigned int offset)
115 return GPIO_INTMASK_V2;
116 case GPIO_INTTYPE_LEVEL:
117 return GPIO_INTTYPE_LEVEL_V2;
118 case GPIO_INT_POLARITY:
119 return GPIO_INT_POLARITY_V2;
121 return GPIO_INTSTATUS_V2;
123 return GPIO_PORTA_EOI_V2;
129 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
131 if (gpio->flags & GPIO_REG_OFFSET_V2)
132 return gpio_reg_v2_convert(offset);
137 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
139 struct gpio_chip *gc = &gpio->ports[0].gc;
140 void __iomem *reg_base = gpio->regs;
142 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
145 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
148 struct gpio_chip *gc = &gpio->ports[0].gc;
149 void __iomem *reg_base = gpio->regs;
151 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
154 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
156 struct dwapb_gpio_port *port;
159 for (i = 0; i < gpio->nr_ports; i++) {
160 port = &gpio->ports[i];
161 if (port->idx == offs / DWAPB_MAX_GPIOS)
168 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
170 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
171 struct gpio_chip *gc;
179 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
180 /* Just read the current value right out of the data register */
181 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
187 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
190 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
192 struct gpio_chip *gc = &gpio->ports[0].gc;
193 unsigned long irq_status;
194 irq_hw_number_t hwirq;
196 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
197 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
198 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
199 u32 irq_type = irq_get_trigger_type(gpio_irq);
201 generic_handle_irq(gpio_irq);
203 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
204 dwapb_toggle_trigger(gpio, hwirq);
210 static void dwapb_irq_handler(struct irq_desc *desc)
212 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
213 struct irq_chip *chip = irq_desc_get_chip(desc);
215 chained_irq_enter(chip, desc);
217 chained_irq_exit(chip, desc);
220 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
222 return IRQ_RETVAL(dwapb_do_irq(dev_id));
225 static void dwapb_irq_ack(struct irq_data *d)
227 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
228 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
229 u32 val = BIT(irqd_to_hwirq(d));
232 spin_lock_irqsave(&gc->bgpio_lock, flags);
233 dwapb_write(gpio, GPIO_PORTA_EOI, val);
234 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
237 static void dwapb_irq_mask(struct irq_data *d)
239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
240 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
244 spin_lock_irqsave(&gc->bgpio_lock, flags);
245 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
246 dwapb_write(gpio, GPIO_INTMASK, val);
247 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
250 static void dwapb_irq_unmask(struct irq_data *d)
252 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
253 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
257 spin_lock_irqsave(&gc->bgpio_lock, flags);
258 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
259 dwapb_write(gpio, GPIO_INTMASK, val);
260 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
263 static void dwapb_irq_enable(struct irq_data *d)
265 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
266 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
270 spin_lock_irqsave(&gc->bgpio_lock, flags);
271 val = dwapb_read(gpio, GPIO_INTEN);
272 val |= BIT(irqd_to_hwirq(d));
273 dwapb_write(gpio, GPIO_INTEN, val);
274 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
277 static void dwapb_irq_disable(struct irq_data *d)
279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
280 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
284 spin_lock_irqsave(&gc->bgpio_lock, flags);
285 val = dwapb_read(gpio, GPIO_INTEN);
286 val &= ~BIT(irqd_to_hwirq(d));
287 dwapb_write(gpio, GPIO_INTEN, val);
288 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
291 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
293 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
294 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
295 irq_hw_number_t bit = irqd_to_hwirq(d);
296 unsigned long level, polarity, flags;
298 spin_lock_irqsave(&gc->bgpio_lock, flags);
299 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
300 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
303 case IRQ_TYPE_EDGE_BOTH:
305 dwapb_toggle_trigger(gpio, bit);
307 case IRQ_TYPE_EDGE_RISING:
309 polarity |= BIT(bit);
311 case IRQ_TYPE_EDGE_FALLING:
313 polarity &= ~BIT(bit);
315 case IRQ_TYPE_LEVEL_HIGH:
317 polarity |= BIT(bit);
319 case IRQ_TYPE_LEVEL_LOW:
321 polarity &= ~BIT(bit);
325 if (type & IRQ_TYPE_LEVEL_MASK)
326 irq_set_handler_locked(d, handle_level_irq);
327 else if (type & IRQ_TYPE_EDGE_BOTH)
328 irq_set_handler_locked(d, handle_edge_irq);
330 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
331 if (type != IRQ_TYPE_EDGE_BOTH)
332 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
333 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
338 #ifdef CONFIG_PM_SLEEP
339 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
341 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
342 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
343 struct dwapb_context *ctx = gpio->ports[0].ctx;
344 irq_hw_number_t bit = irqd_to_hwirq(d);
347 ctx->wake_en |= BIT(bit);
349 ctx->wake_en &= ~BIT(bit);
355 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
356 unsigned offset, unsigned debounce)
358 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
359 struct dwapb_gpio *gpio = port->gpio;
360 unsigned long flags, val_deb;
361 unsigned long mask = BIT(offset);
363 spin_lock_irqsave(&gc->bgpio_lock, flags);
365 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
370 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
372 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
377 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
378 unsigned long config)
382 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
385 debounce = pinconf_to_config_argument(config);
386 return dwapb_gpio_set_debounce(gc, offset, debounce);
389 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
390 struct dwapb_port_property *pp)
394 /* Group all available IRQs into an array of parental IRQs. */
395 for (i = 0; i < pp->ngpio; ++i) {
399 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
402 return pirq->nr_irqs ? 0 : -ENOENT;
405 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
406 struct dwapb_gpio_port *port,
407 struct dwapb_port_property *pp)
409 struct dwapb_gpio_port_irqchip *pirq;
410 struct gpio_chip *gc = &port->gc;
411 struct gpio_irq_chip *girq;
414 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
418 if (dwapb_convert_irqs(pirq, pp)) {
419 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
424 girq->handler = handle_bad_irq;
425 girq->default_type = IRQ_TYPE_NONE;
428 pirq->irqchip.name = DWAPB_DRIVER_NAME;
429 pirq->irqchip.irq_ack = dwapb_irq_ack;
430 pirq->irqchip.irq_mask = dwapb_irq_mask;
431 pirq->irqchip.irq_unmask = dwapb_irq_unmask;
432 pirq->irqchip.irq_set_type = dwapb_irq_set_type;
433 pirq->irqchip.irq_enable = dwapb_irq_enable;
434 pirq->irqchip.irq_disable = dwapb_irq_disable;
435 #ifdef CONFIG_PM_SLEEP
436 pirq->irqchip.irq_set_wake = dwapb_irq_set_wake;
439 if (!pp->irq_shared) {
440 girq->num_parents = pirq->nr_irqs;
441 girq->parents = pirq->irq;
442 girq->parent_handler_data = gpio;
443 girq->parent_handler = dwapb_irq_handler;
445 /* This will let us handle the parent IRQ in the driver */
446 girq->num_parents = 0;
447 girq->parents = NULL;
448 girq->parent_handler = NULL;
451 * Request a shared IRQ since where MFD would have devices
452 * using the same irq pin
454 err = devm_request_irq(gpio->dev, pp->irq[0],
455 dwapb_irq_handler_mfd,
456 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
458 dev_err(gpio->dev, "error requesting IRQ\n");
463 girq->chip = &pirq->irqchip;
468 devm_kfree(gpio->dev, pirq);
471 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
472 struct dwapb_port_property *pp,
475 struct dwapb_gpio_port *port;
476 void __iomem *dat, *set, *dirout;
479 port = &gpio->ports[offs];
483 #ifdef CONFIG_PM_SLEEP
484 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
489 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
490 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
491 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
493 /* This registers 32 GPIO lines per port */
494 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
497 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
502 #ifdef CONFIG_OF_GPIO
503 port->gc.of_node = to_of_node(pp->fwnode);
505 port->gc.ngpio = pp->ngpio;
506 port->gc.base = pp->gpio_base;
508 /* Only port A support debounce */
510 port->gc.set_config = dwapb_gpio_set_config;
512 /* Only port A can provide interrupts in all configurations of the IP */
514 dwapb_configure_irqs(gpio, port, pp);
516 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
518 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
526 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
527 struct dwapb_port_property *pp)
531 for (j = 0; j < pp->ngpio; j++) {
532 if (has_acpi_companion(dev))
533 irq = platform_get_irq_optional(to_platform_device(dev), j);
535 irq = fwnode_irq_get(fwnode, j);
541 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
543 struct fwnode_handle *fwnode;
544 struct dwapb_platform_data *pdata;
545 struct dwapb_port_property *pp;
549 nports = device_get_child_node_count(dev);
551 return ERR_PTR(-ENODEV);
553 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
555 return ERR_PTR(-ENOMEM);
557 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
558 if (!pdata->properties)
559 return ERR_PTR(-ENOMEM);
561 pdata->nports = nports;
564 device_for_each_child_node(dev, fwnode) {
565 pp = &pdata->properties[i++];
568 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
569 pp->idx >= DWAPB_MAX_PORTS) {
571 "missing/invalid port index for port%d\n", i);
572 fwnode_handle_put(fwnode);
573 return ERR_PTR(-EINVAL);
576 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
577 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
579 "failed to get number of gpios for port%d\n",
581 pp->ngpio = DWAPB_MAX_GPIOS;
584 pp->irq_shared = false;
588 * Only port A can provide interrupts in all configurations of
592 dwapb_get_irq(dev, fwnode, pp);
598 static void dwapb_assert_reset(void *data)
600 struct dwapb_gpio *gpio = data;
602 reset_control_assert(gpio->rst);
605 static int dwapb_get_reset(struct dwapb_gpio *gpio)
609 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
610 if (IS_ERR(gpio->rst))
611 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
612 "Cannot get reset descriptor\n");
614 err = reset_control_deassert(gpio->rst);
616 dev_err(gpio->dev, "Cannot deassert reset lane\n");
620 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
623 static void dwapb_disable_clks(void *data)
625 struct dwapb_gpio *gpio = data;
627 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
630 static int dwapb_get_clks(struct dwapb_gpio *gpio)
634 /* Optional bus and debounce clocks */
635 gpio->clks[0].id = "bus";
636 gpio->clks[1].id = "db";
637 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
640 dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n");
644 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
646 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
650 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
653 static const struct of_device_id dwapb_of_match[] = {
654 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
655 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
658 MODULE_DEVICE_TABLE(of, dwapb_of_match);
660 static const struct acpi_device_id dwapb_acpi_match[] = {
663 {"APMC0D81", GPIO_REG_OFFSET_V2},
666 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
668 static int dwapb_gpio_probe(struct platform_device *pdev)
671 struct dwapb_gpio *gpio;
673 struct device *dev = &pdev->dev;
674 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
677 pdata = dwapb_gpio_get_pdata(dev);
679 return PTR_ERR(pdata);
685 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
689 gpio->dev = &pdev->dev;
690 gpio->nr_ports = pdata->nports;
692 err = dwapb_get_reset(gpio);
696 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
697 sizeof(*gpio->ports), GFP_KERNEL);
701 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
702 if (IS_ERR(gpio->regs))
703 return PTR_ERR(gpio->regs);
705 err = dwapb_get_clks(gpio);
709 gpio->flags = (uintptr_t)device_get_match_data(dev);
711 for (i = 0; i < gpio->nr_ports; i++) {
712 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
717 platform_set_drvdata(pdev, gpio);
722 #ifdef CONFIG_PM_SLEEP
723 static int dwapb_gpio_suspend(struct device *dev)
725 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
726 struct gpio_chip *gc = &gpio->ports[0].gc;
730 spin_lock_irqsave(&gc->bgpio_lock, flags);
731 for (i = 0; i < gpio->nr_ports; i++) {
733 unsigned int idx = gpio->ports[i].idx;
734 struct dwapb_context *ctx = gpio->ports[i].ctx;
736 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
737 ctx->dir = dwapb_read(gpio, offset);
739 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
740 ctx->data = dwapb_read(gpio, offset);
742 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
743 ctx->ext = dwapb_read(gpio, offset);
745 /* Only port A can provide interrupts */
747 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
748 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
749 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
750 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
751 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
753 /* Mask out interrupts */
754 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
757 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
759 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
764 static int dwapb_gpio_resume(struct device *dev)
766 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
767 struct gpio_chip *gc = &gpio->ports[0].gc;
771 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
773 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
777 spin_lock_irqsave(&gc->bgpio_lock, flags);
778 for (i = 0; i < gpio->nr_ports; i++) {
780 unsigned int idx = gpio->ports[i].idx;
781 struct dwapb_context *ctx = gpio->ports[i].ctx;
783 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
784 dwapb_write(gpio, offset, ctx->data);
786 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
787 dwapb_write(gpio, offset, ctx->dir);
789 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
790 dwapb_write(gpio, offset, ctx->ext);
792 /* Only port A can provide interrupts */
794 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
795 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
796 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
797 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
798 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
800 /* Clear out spurious interrupts */
801 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
804 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
810 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
813 static struct platform_driver dwapb_gpio_driver = {
815 .name = DWAPB_DRIVER_NAME,
816 .pm = &dwapb_gpio_pm_ops,
817 .of_match_table = dwapb_of_match,
818 .acpi_match_table = dwapb_acpi_match,
820 .probe = dwapb_gpio_probe,
823 module_platform_driver(dwapb_gpio_driver);
825 MODULE_LICENSE("GPL");
826 MODULE_AUTHOR("Jamie Iles");
827 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
828 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);