1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011 Jamie Iles
5 * All enquiries to support@picochip.com
7 #include <linux/acpi.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
25 #include "gpiolib-acpi.h"
27 #define GPIO_SWPORTA_DR 0x00
28 #define GPIO_SWPORTA_DDR 0x04
29 #define GPIO_SWPORTB_DR 0x0c
30 #define GPIO_SWPORTB_DDR 0x10
31 #define GPIO_SWPORTC_DR 0x18
32 #define GPIO_SWPORTC_DDR 0x1c
33 #define GPIO_SWPORTD_DR 0x24
34 #define GPIO_SWPORTD_DDR 0x28
35 #define GPIO_INTEN 0x30
36 #define GPIO_INTMASK 0x34
37 #define GPIO_INTTYPE_LEVEL 0x38
38 #define GPIO_INT_POLARITY 0x3c
39 #define GPIO_INTSTATUS 0x40
40 #define GPIO_PORTA_DEBOUNCE 0x48
41 #define GPIO_PORTA_EOI 0x4c
42 #define GPIO_EXT_PORTA 0x50
43 #define GPIO_EXT_PORTB 0x54
44 #define GPIO_EXT_PORTC 0x58
45 #define GPIO_EXT_PORTD 0x5c
47 #define DWAPB_DRIVER_NAME "gpio-dwapb"
48 #define DWAPB_MAX_PORTS 4
49 #define DWAPB_MAX_GPIOS 32
51 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
52 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
53 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
55 #define GPIO_REG_OFFSET_V1 0
56 #define GPIO_REG_OFFSET_V2 1
57 #define GPIO_REG_OFFSET_MASK BIT(0)
59 #define GPIO_INTMASK_V2 0x44
60 #define GPIO_INTTYPE_LEVEL_V2 0x34
61 #define GPIO_INT_POLARITY_V2 0x38
62 #define GPIO_INTSTATUS_V2 0x3c
63 #define GPIO_PORTA_EOI_V2 0x40
65 #define DWAPB_NR_CLOCKS 2
69 struct dwapb_port_property {
70 struct fwnode_handle *fwnode;
73 unsigned int gpio_base;
74 int irq[DWAPB_MAX_GPIOS];
77 struct dwapb_platform_data {
78 struct dwapb_port_property *properties;
82 #ifdef CONFIG_PM_SLEEP
83 /* Store GPIO context across system-wide suspend/resume transitions */
84 struct dwapb_context {
97 struct dwapb_gpio_port_irqchip {
98 struct irq_chip irqchip;
100 unsigned int irq[DWAPB_MAX_GPIOS];
103 struct dwapb_gpio_port {
105 struct dwapb_gpio_port_irqchip *pirq;
106 struct dwapb_gpio *gpio;
107 #ifdef CONFIG_PM_SLEEP
108 struct dwapb_context *ctx;
112 #define to_dwapb_gpio(_gc) \
113 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
118 struct dwapb_gpio_port *ports;
119 unsigned int nr_ports;
121 struct reset_control *rst;
122 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
125 static inline u32 gpio_reg_v2_convert(unsigned int offset)
129 return GPIO_INTMASK_V2;
130 case GPIO_INTTYPE_LEVEL:
131 return GPIO_INTTYPE_LEVEL_V2;
132 case GPIO_INT_POLARITY:
133 return GPIO_INT_POLARITY_V2;
135 return GPIO_INTSTATUS_V2;
137 return GPIO_PORTA_EOI_V2;
143 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
145 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
146 return gpio_reg_v2_convert(offset);
151 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
153 struct gpio_chip *gc = &gpio->ports[0].gc;
154 void __iomem *reg_base = gpio->regs;
156 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
159 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
162 struct gpio_chip *gc = &gpio->ports[0].gc;
163 void __iomem *reg_base = gpio->regs;
165 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
168 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
170 struct dwapb_gpio_port *port;
173 for (i = 0; i < gpio->nr_ports; i++) {
174 port = &gpio->ports[i];
175 if (port->idx == offs / DWAPB_MAX_GPIOS)
182 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
184 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
185 struct gpio_chip *gc;
193 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
194 /* Just read the current value right out of the data register */
195 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
201 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
204 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
206 struct gpio_chip *gc = &gpio->ports[0].gc;
207 unsigned long irq_status;
208 irq_hw_number_t hwirq;
210 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
211 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
212 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
213 u32 irq_type = irq_get_trigger_type(gpio_irq);
215 generic_handle_irq(gpio_irq);
217 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
218 dwapb_toggle_trigger(gpio, hwirq);
224 static void dwapb_irq_handler(struct irq_desc *desc)
226 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
227 struct irq_chip *chip = irq_desc_get_chip(desc);
229 chained_irq_enter(chip, desc);
231 chained_irq_exit(chip, desc);
234 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
236 return IRQ_RETVAL(dwapb_do_irq(dev_id));
239 static void dwapb_irq_ack(struct irq_data *d)
241 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
242 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
243 u32 val = BIT(irqd_to_hwirq(d));
246 spin_lock_irqsave(&gc->bgpio_lock, flags);
247 dwapb_write(gpio, GPIO_PORTA_EOI, val);
248 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
251 static void dwapb_irq_mask(struct irq_data *d)
253 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
254 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
258 spin_lock_irqsave(&gc->bgpio_lock, flags);
259 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
260 dwapb_write(gpio, GPIO_INTMASK, val);
261 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
264 static void dwapb_irq_unmask(struct irq_data *d)
266 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
267 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
271 spin_lock_irqsave(&gc->bgpio_lock, flags);
272 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
273 dwapb_write(gpio, GPIO_INTMASK, val);
274 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
277 static void dwapb_irq_enable(struct irq_data *d)
279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
280 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
284 spin_lock_irqsave(&gc->bgpio_lock, flags);
285 val = dwapb_read(gpio, GPIO_INTEN);
286 val |= BIT(irqd_to_hwirq(d));
287 dwapb_write(gpio, GPIO_INTEN, val);
288 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
291 static void dwapb_irq_disable(struct irq_data *d)
293 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
294 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
298 spin_lock_irqsave(&gc->bgpio_lock, flags);
299 val = dwapb_read(gpio, GPIO_INTEN);
300 val &= ~BIT(irqd_to_hwirq(d));
301 dwapb_write(gpio, GPIO_INTEN, val);
302 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
305 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
307 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
308 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
309 irq_hw_number_t bit = irqd_to_hwirq(d);
310 unsigned long level, polarity, flags;
312 spin_lock_irqsave(&gc->bgpio_lock, flags);
313 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
314 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
317 case IRQ_TYPE_EDGE_BOTH:
319 dwapb_toggle_trigger(gpio, bit);
321 case IRQ_TYPE_EDGE_RISING:
323 polarity |= BIT(bit);
325 case IRQ_TYPE_EDGE_FALLING:
327 polarity &= ~BIT(bit);
329 case IRQ_TYPE_LEVEL_HIGH:
331 polarity |= BIT(bit);
333 case IRQ_TYPE_LEVEL_LOW:
335 polarity &= ~BIT(bit);
339 if (type & IRQ_TYPE_LEVEL_MASK)
340 irq_set_handler_locked(d, handle_level_irq);
341 else if (type & IRQ_TYPE_EDGE_BOTH)
342 irq_set_handler_locked(d, handle_edge_irq);
344 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
345 if (type != IRQ_TYPE_EDGE_BOTH)
346 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
347 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
352 #ifdef CONFIG_PM_SLEEP
353 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
355 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
356 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
357 struct dwapb_context *ctx = gpio->ports[0].ctx;
358 irq_hw_number_t bit = irqd_to_hwirq(d);
361 ctx->wake_en |= BIT(bit);
363 ctx->wake_en &= ~BIT(bit);
369 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
370 unsigned offset, unsigned debounce)
372 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
373 struct dwapb_gpio *gpio = port->gpio;
374 unsigned long flags, val_deb;
375 unsigned long mask = BIT(offset);
377 spin_lock_irqsave(&gc->bgpio_lock, flags);
379 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
384 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
386 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
391 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
392 unsigned long config)
396 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
399 debounce = pinconf_to_config_argument(config);
400 return dwapb_gpio_set_debounce(gc, offset, debounce);
403 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
404 struct dwapb_port_property *pp)
408 /* Group all available IRQs into an array of parental IRQs. */
409 for (i = 0; i < pp->ngpio; ++i) {
413 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
416 return pirq->nr_irqs ? 0 : -ENOENT;
419 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
420 struct dwapb_gpio_port *port,
421 struct dwapb_port_property *pp)
423 struct dwapb_gpio_port_irqchip *pirq;
424 struct gpio_chip *gc = &port->gc;
425 struct gpio_irq_chip *girq;
428 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
432 if (dwapb_convert_irqs(pirq, pp)) {
433 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
438 girq->handler = handle_bad_irq;
439 girq->default_type = IRQ_TYPE_NONE;
442 pirq->irqchip.name = DWAPB_DRIVER_NAME;
443 pirq->irqchip.irq_ack = dwapb_irq_ack;
444 pirq->irqchip.irq_mask = dwapb_irq_mask;
445 pirq->irqchip.irq_unmask = dwapb_irq_unmask;
446 pirq->irqchip.irq_set_type = dwapb_irq_set_type;
447 pirq->irqchip.irq_enable = dwapb_irq_enable;
448 pirq->irqchip.irq_disable = dwapb_irq_disable;
449 #ifdef CONFIG_PM_SLEEP
450 pirq->irqchip.irq_set_wake = dwapb_irq_set_wake;
454 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
455 * IRQ lane shared between several devices. In that case the parental
456 * IRQ has to be handled in the shared way so to be properly delivered
457 * to all the connected devices.
459 if (has_acpi_companion(gpio->dev)) {
460 girq->num_parents = 0;
461 girq->parents = NULL;
462 girq->parent_handler = NULL;
464 err = devm_request_irq(gpio->dev, pp->irq[0],
465 dwapb_irq_handler_mfd,
466 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
468 dev_err(gpio->dev, "error requesting IRQ\n");
472 girq->num_parents = pirq->nr_irqs;
473 girq->parents = pirq->irq;
474 girq->parent_handler_data = gpio;
475 girq->parent_handler = dwapb_irq_handler;
478 girq->chip = &pirq->irqchip;
483 devm_kfree(gpio->dev, pirq);
486 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
487 struct dwapb_port_property *pp,
490 struct dwapb_gpio_port *port;
491 void __iomem *dat, *set, *dirout;
494 port = &gpio->ports[offs];
498 #ifdef CONFIG_PM_SLEEP
499 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
504 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
505 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
506 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
508 /* This registers 32 GPIO lines per port */
509 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
512 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
517 port->gc.fwnode = pp->fwnode;
518 port->gc.ngpio = pp->ngpio;
519 port->gc.base = pp->gpio_base;
521 /* Only port A support debounce */
523 port->gc.set_config = dwapb_gpio_set_config;
525 /* Only port A can provide interrupts in all configurations of the IP */
527 dwapb_configure_irqs(gpio, port, pp);
529 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
531 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
539 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
540 struct dwapb_port_property *pp)
544 for (j = 0; j < pp->ngpio; j++) {
545 if (has_acpi_companion(dev))
546 irq = platform_get_irq_optional(to_platform_device(dev), j);
548 irq = fwnode_irq_get(fwnode, j);
554 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
556 struct fwnode_handle *fwnode;
557 struct dwapb_platform_data *pdata;
558 struct dwapb_port_property *pp;
562 nports = device_get_child_node_count(dev);
564 return ERR_PTR(-ENODEV);
566 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
568 return ERR_PTR(-ENOMEM);
570 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
571 if (!pdata->properties)
572 return ERR_PTR(-ENOMEM);
574 pdata->nports = nports;
577 device_for_each_child_node(dev, fwnode) {
578 pp = &pdata->properties[i++];
581 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
582 pp->idx >= DWAPB_MAX_PORTS) {
584 "missing/invalid port index for port%d\n", i);
585 fwnode_handle_put(fwnode);
586 return ERR_PTR(-EINVAL);
589 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
590 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
592 "failed to get number of gpios for port%d\n",
594 pp->ngpio = DWAPB_MAX_GPIOS;
599 /* For internal use only, new platforms mustn't exercise this */
600 if (is_software_node(fwnode))
601 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
604 * Only port A can provide interrupts in all configurations of
608 dwapb_get_irq(dev, fwnode, pp);
614 static void dwapb_assert_reset(void *data)
616 struct dwapb_gpio *gpio = data;
618 reset_control_assert(gpio->rst);
621 static int dwapb_get_reset(struct dwapb_gpio *gpio)
625 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
626 if (IS_ERR(gpio->rst))
627 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
628 "Cannot get reset descriptor\n");
630 err = reset_control_deassert(gpio->rst);
632 dev_err(gpio->dev, "Cannot deassert reset lane\n");
636 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
639 static void dwapb_disable_clks(void *data)
641 struct dwapb_gpio *gpio = data;
643 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
646 static int dwapb_get_clks(struct dwapb_gpio *gpio)
650 /* Optional bus and debounce clocks */
651 gpio->clks[0].id = "bus";
652 gpio->clks[1].id = "db";
653 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
656 dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n");
660 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
662 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
666 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
669 static const struct of_device_id dwapb_of_match[] = {
670 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
671 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
674 MODULE_DEVICE_TABLE(of, dwapb_of_match);
676 static const struct acpi_device_id dwapb_acpi_match[] = {
677 {"HISI0181", GPIO_REG_OFFSET_V1},
678 {"APMC0D07", GPIO_REG_OFFSET_V1},
679 {"APMC0D81", GPIO_REG_OFFSET_V2},
682 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
684 static int dwapb_gpio_probe(struct platform_device *pdev)
687 struct dwapb_gpio *gpio;
689 struct dwapb_platform_data *pdata;
690 struct device *dev = &pdev->dev;
692 pdata = dwapb_gpio_get_pdata(dev);
694 return PTR_ERR(pdata);
696 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
700 gpio->dev = &pdev->dev;
701 gpio->nr_ports = pdata->nports;
703 err = dwapb_get_reset(gpio);
707 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
708 sizeof(*gpio->ports), GFP_KERNEL);
712 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
713 if (IS_ERR(gpio->regs))
714 return PTR_ERR(gpio->regs);
716 err = dwapb_get_clks(gpio);
720 gpio->flags = (uintptr_t)device_get_match_data(dev);
722 for (i = 0; i < gpio->nr_ports; i++) {
723 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
728 platform_set_drvdata(pdev, gpio);
733 #ifdef CONFIG_PM_SLEEP
734 static int dwapb_gpio_suspend(struct device *dev)
736 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
737 struct gpio_chip *gc = &gpio->ports[0].gc;
741 spin_lock_irqsave(&gc->bgpio_lock, flags);
742 for (i = 0; i < gpio->nr_ports; i++) {
744 unsigned int idx = gpio->ports[i].idx;
745 struct dwapb_context *ctx = gpio->ports[i].ctx;
747 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
748 ctx->dir = dwapb_read(gpio, offset);
750 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
751 ctx->data = dwapb_read(gpio, offset);
753 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
754 ctx->ext = dwapb_read(gpio, offset);
756 /* Only port A can provide interrupts */
758 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
759 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
760 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
761 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
762 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
764 /* Mask out interrupts */
765 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
768 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
770 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
775 static int dwapb_gpio_resume(struct device *dev)
777 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
778 struct gpio_chip *gc = &gpio->ports[0].gc;
782 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
784 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
788 spin_lock_irqsave(&gc->bgpio_lock, flags);
789 for (i = 0; i < gpio->nr_ports; i++) {
791 unsigned int idx = gpio->ports[i].idx;
792 struct dwapb_context *ctx = gpio->ports[i].ctx;
794 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
795 dwapb_write(gpio, offset, ctx->data);
797 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
798 dwapb_write(gpio, offset, ctx->dir);
800 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
801 dwapb_write(gpio, offset, ctx->ext);
803 /* Only port A can provide interrupts */
805 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
806 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
807 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
808 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
809 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
811 /* Clear out spurious interrupts */
812 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
815 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
821 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
824 static struct platform_driver dwapb_gpio_driver = {
826 .name = DWAPB_DRIVER_NAME,
827 .pm = &dwapb_gpio_pm_ops,
828 .of_match_table = dwapb_of_match,
829 .acpi_match_table = dwapb_acpi_match,
831 .probe = dwapb_gpio_probe,
834 module_platform_driver(dwapb_gpio_driver);
836 MODULE_LICENSE("GPL");
837 MODULE_AUTHOR("Jamie Iles");
838 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
839 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);