1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011 Jamie Iles
5 * All enquiries to support@picochip.com
7 #include <linux/acpi.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
24 #include "gpiolib-acpi.h"
26 #define GPIO_SWPORTA_DR 0x00
27 #define GPIO_SWPORTA_DDR 0x04
28 #define GPIO_SWPORTB_DR 0x0c
29 #define GPIO_SWPORTB_DDR 0x10
30 #define GPIO_SWPORTC_DR 0x18
31 #define GPIO_SWPORTC_DDR 0x1c
32 #define GPIO_SWPORTD_DR 0x24
33 #define GPIO_SWPORTD_DDR 0x28
34 #define GPIO_INTEN 0x30
35 #define GPIO_INTMASK 0x34
36 #define GPIO_INTTYPE_LEVEL 0x38
37 #define GPIO_INT_POLARITY 0x3c
38 #define GPIO_INTSTATUS 0x40
39 #define GPIO_PORTA_DEBOUNCE 0x48
40 #define GPIO_PORTA_EOI 0x4c
41 #define GPIO_EXT_PORTA 0x50
42 #define GPIO_EXT_PORTB 0x54
43 #define GPIO_EXT_PORTC 0x58
44 #define GPIO_EXT_PORTD 0x5c
46 #define DWAPB_DRIVER_NAME "gpio-dwapb"
47 #define DWAPB_MAX_PORTS 4
48 #define DWAPB_MAX_GPIOS 32
50 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
51 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
52 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
54 #define GPIO_REG_OFFSET_V1 0
55 #define GPIO_REG_OFFSET_V2 1
56 #define GPIO_REG_OFFSET_MASK BIT(0)
58 #define GPIO_INTMASK_V2 0x44
59 #define GPIO_INTTYPE_LEVEL_V2 0x34
60 #define GPIO_INT_POLARITY_V2 0x38
61 #define GPIO_INTSTATUS_V2 0x3c
62 #define GPIO_PORTA_EOI_V2 0x40
64 #define DWAPB_NR_CLOCKS 2
68 struct dwapb_port_property {
69 struct fwnode_handle *fwnode;
72 unsigned int gpio_base;
73 int irq[DWAPB_MAX_GPIOS];
76 struct dwapb_platform_data {
77 struct dwapb_port_property *properties;
81 #ifdef CONFIG_PM_SLEEP
82 /* Store GPIO context across system-wide suspend/resume transitions */
83 struct dwapb_context {
96 struct dwapb_gpio_port_irqchip {
98 unsigned int irq[DWAPB_MAX_GPIOS];
101 struct dwapb_gpio_port {
103 struct dwapb_gpio_port_irqchip *pirq;
104 struct dwapb_gpio *gpio;
105 #ifdef CONFIG_PM_SLEEP
106 struct dwapb_context *ctx;
110 #define to_dwapb_gpio(_gc) \
111 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
116 struct dwapb_gpio_port *ports;
117 unsigned int nr_ports;
119 struct reset_control *rst;
120 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
123 static inline u32 gpio_reg_v2_convert(unsigned int offset)
127 return GPIO_INTMASK_V2;
128 case GPIO_INTTYPE_LEVEL:
129 return GPIO_INTTYPE_LEVEL_V2;
130 case GPIO_INT_POLARITY:
131 return GPIO_INT_POLARITY_V2;
133 return GPIO_INTSTATUS_V2;
135 return GPIO_PORTA_EOI_V2;
141 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
143 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
144 return gpio_reg_v2_convert(offset);
149 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
151 struct gpio_chip *gc = &gpio->ports[0].gc;
152 void __iomem *reg_base = gpio->regs;
154 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
157 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
160 struct gpio_chip *gc = &gpio->ports[0].gc;
161 void __iomem *reg_base = gpio->regs;
163 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
166 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
168 struct dwapb_gpio_port *port;
171 for (i = 0; i < gpio->nr_ports; i++) {
172 port = &gpio->ports[i];
173 if (port->idx == offs / DWAPB_MAX_GPIOS)
180 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
182 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
183 struct gpio_chip *gc;
191 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
192 /* Just read the current value right out of the data register */
193 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
199 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
202 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
204 struct gpio_chip *gc = &gpio->ports[0].gc;
205 unsigned long irq_status;
206 irq_hw_number_t hwirq;
208 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
209 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
210 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
211 u32 irq_type = irq_get_trigger_type(gpio_irq);
213 generic_handle_irq(gpio_irq);
215 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
216 dwapb_toggle_trigger(gpio, hwirq);
222 static void dwapb_irq_handler(struct irq_desc *desc)
224 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
225 struct irq_chip *chip = irq_desc_get_chip(desc);
227 chained_irq_enter(chip, desc);
229 chained_irq_exit(chip, desc);
232 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
234 return IRQ_RETVAL(dwapb_do_irq(dev_id));
237 static void dwapb_irq_ack(struct irq_data *d)
239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
240 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
241 u32 val = BIT(irqd_to_hwirq(d));
244 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
245 dwapb_write(gpio, GPIO_PORTA_EOI, val);
246 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
249 static void dwapb_irq_mask(struct irq_data *d)
251 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
252 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
253 irq_hw_number_t hwirq = irqd_to_hwirq(d);
257 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
258 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
259 dwapb_write(gpio, GPIO_INTMASK, val);
260 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
262 gpiochip_disable_irq(gc, hwirq);
265 static void dwapb_irq_unmask(struct irq_data *d)
267 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
268 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
269 irq_hw_number_t hwirq = irqd_to_hwirq(d);
273 gpiochip_enable_irq(gc, hwirq);
275 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
276 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
277 dwapb_write(gpio, GPIO_INTMASK, val);
278 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
281 static void dwapb_irq_enable(struct irq_data *d)
283 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
284 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
285 irq_hw_number_t hwirq = irqd_to_hwirq(d);
289 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
290 val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);
291 dwapb_write(gpio, GPIO_INTEN, val);
292 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
293 dwapb_write(gpio, GPIO_INTMASK, val);
294 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
297 static void dwapb_irq_disable(struct irq_data *d)
299 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
300 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
301 irq_hw_number_t hwirq = irqd_to_hwirq(d);
305 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
306 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
307 dwapb_write(gpio, GPIO_INTMASK, val);
308 val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);
309 dwapb_write(gpio, GPIO_INTEN, val);
310 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
313 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
315 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
316 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
317 irq_hw_number_t bit = irqd_to_hwirq(d);
318 unsigned long level, polarity, flags;
320 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
321 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
322 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
325 case IRQ_TYPE_EDGE_BOTH:
327 dwapb_toggle_trigger(gpio, bit);
329 case IRQ_TYPE_EDGE_RISING:
331 polarity |= BIT(bit);
333 case IRQ_TYPE_EDGE_FALLING:
335 polarity &= ~BIT(bit);
337 case IRQ_TYPE_LEVEL_HIGH:
339 polarity |= BIT(bit);
341 case IRQ_TYPE_LEVEL_LOW:
343 polarity &= ~BIT(bit);
347 if (type & IRQ_TYPE_LEVEL_MASK)
348 irq_set_handler_locked(d, handle_level_irq);
349 else if (type & IRQ_TYPE_EDGE_BOTH)
350 irq_set_handler_locked(d, handle_edge_irq);
352 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
353 if (type != IRQ_TYPE_EDGE_BOTH)
354 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
355 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
360 #ifdef CONFIG_PM_SLEEP
361 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
364 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
365 struct dwapb_context *ctx = gpio->ports[0].ctx;
366 irq_hw_number_t bit = irqd_to_hwirq(d);
369 ctx->wake_en |= BIT(bit);
371 ctx->wake_en &= ~BIT(bit);
376 #define dwapb_irq_set_wake NULL
379 static const struct irq_chip dwapb_irq_chip = {
380 .name = DWAPB_DRIVER_NAME,
381 .irq_ack = dwapb_irq_ack,
382 .irq_mask = dwapb_irq_mask,
383 .irq_unmask = dwapb_irq_unmask,
384 .irq_set_type = dwapb_irq_set_type,
385 .irq_enable = dwapb_irq_enable,
386 .irq_disable = dwapb_irq_disable,
387 .irq_set_wake = dwapb_irq_set_wake,
388 .flags = IRQCHIP_IMMUTABLE,
389 GPIOCHIP_IRQ_RESOURCE_HELPERS,
392 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
393 unsigned offset, unsigned debounce)
395 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
396 struct dwapb_gpio *gpio = port->gpio;
397 unsigned long flags, val_deb;
398 unsigned long mask = BIT(offset);
400 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
402 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
407 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
409 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
414 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
415 unsigned long config)
419 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
422 debounce = pinconf_to_config_argument(config);
423 return dwapb_gpio_set_debounce(gc, offset, debounce);
426 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
427 struct dwapb_port_property *pp)
431 /* Group all available IRQs into an array of parental IRQs. */
432 for (i = 0; i < pp->ngpio; ++i) {
436 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
439 return pirq->nr_irqs ? 0 : -ENOENT;
442 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
443 struct dwapb_gpio_port *port,
444 struct dwapb_port_property *pp)
446 struct dwapb_gpio_port_irqchip *pirq;
447 struct gpio_chip *gc = &port->gc;
448 struct gpio_irq_chip *girq;
451 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
455 if (dwapb_convert_irqs(pirq, pp)) {
456 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
461 girq->handler = handle_bad_irq;
462 girq->default_type = IRQ_TYPE_NONE;
467 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
468 * IRQ lane shared between several devices. In that case the parental
469 * IRQ has to be handled in the shared way so to be properly delivered
470 * to all the connected devices.
472 if (has_acpi_companion(gpio->dev)) {
473 girq->num_parents = 0;
474 girq->parents = NULL;
475 girq->parent_handler = NULL;
477 err = devm_request_irq(gpio->dev, pp->irq[0],
478 dwapb_irq_handler_mfd,
479 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
481 dev_err(gpio->dev, "error requesting IRQ\n");
485 girq->num_parents = pirq->nr_irqs;
486 girq->parents = pirq->irq;
487 girq->parent_handler_data = gpio;
488 girq->parent_handler = dwapb_irq_handler;
491 gpio_irq_chip_set_chip(girq, &dwapb_irq_chip);
496 devm_kfree(gpio->dev, pirq);
499 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
500 struct dwapb_port_property *pp,
503 struct dwapb_gpio_port *port;
504 void __iomem *dat, *set, *dirout;
507 port = &gpio->ports[offs];
511 #ifdef CONFIG_PM_SLEEP
512 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
517 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
518 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
519 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
521 /* This registers 32 GPIO lines per port */
522 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
525 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
530 port->gc.fwnode = pp->fwnode;
531 port->gc.ngpio = pp->ngpio;
532 port->gc.base = pp->gpio_base;
534 /* Only port A support debounce */
536 port->gc.set_config = dwapb_gpio_set_config;
538 /* Only port A can provide interrupts in all configurations of the IP */
540 dwapb_configure_irqs(gpio, port, pp);
542 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
544 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
552 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
553 struct dwapb_port_property *pp)
557 for (j = 0; j < pp->ngpio; j++) {
558 if (has_acpi_companion(dev))
559 irq = platform_get_irq_optional(to_platform_device(dev), j);
561 irq = fwnode_irq_get(fwnode, j);
567 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
569 struct fwnode_handle *fwnode;
570 struct dwapb_platform_data *pdata;
571 struct dwapb_port_property *pp;
575 nports = device_get_child_node_count(dev);
577 return ERR_PTR(-ENODEV);
579 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
581 return ERR_PTR(-ENOMEM);
583 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
584 if (!pdata->properties)
585 return ERR_PTR(-ENOMEM);
587 pdata->nports = nports;
590 device_for_each_child_node(dev, fwnode) {
591 pp = &pdata->properties[i++];
594 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
595 pp->idx >= DWAPB_MAX_PORTS) {
597 "missing/invalid port index for port%d\n", i);
598 fwnode_handle_put(fwnode);
599 return ERR_PTR(-EINVAL);
602 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
603 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
605 "failed to get number of gpios for port%d\n",
607 pp->ngpio = DWAPB_MAX_GPIOS;
612 /* For internal use only, new platforms mustn't exercise this */
613 if (is_software_node(fwnode))
614 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
617 * Only port A can provide interrupts in all configurations of
621 dwapb_get_irq(dev, fwnode, pp);
627 static void dwapb_assert_reset(void *data)
629 struct dwapb_gpio *gpio = data;
631 reset_control_assert(gpio->rst);
634 static int dwapb_get_reset(struct dwapb_gpio *gpio)
638 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
639 if (IS_ERR(gpio->rst))
640 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
641 "Cannot get reset descriptor\n");
643 err = reset_control_deassert(gpio->rst);
645 dev_err(gpio->dev, "Cannot deassert reset lane\n");
649 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
652 static void dwapb_disable_clks(void *data)
654 struct dwapb_gpio *gpio = data;
656 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
659 static int dwapb_get_clks(struct dwapb_gpio *gpio)
663 /* Optional bus and debounce clocks */
664 gpio->clks[0].id = "bus";
665 gpio->clks[1].id = "db";
666 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
669 return dev_err_probe(gpio->dev, err,
670 "Cannot get APB/Debounce clocks\n");
672 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
674 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
678 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
681 static const struct of_device_id dwapb_of_match[] = {
682 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
683 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
686 MODULE_DEVICE_TABLE(of, dwapb_of_match);
688 static const struct acpi_device_id dwapb_acpi_match[] = {
689 {"HISI0181", GPIO_REG_OFFSET_V1},
690 {"APMC0D07", GPIO_REG_OFFSET_V1},
691 {"APMC0D81", GPIO_REG_OFFSET_V2},
694 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
696 static int dwapb_gpio_probe(struct platform_device *pdev)
699 struct dwapb_gpio *gpio;
701 struct dwapb_platform_data *pdata;
702 struct device *dev = &pdev->dev;
704 pdata = dwapb_gpio_get_pdata(dev);
706 return PTR_ERR(pdata);
708 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
712 gpio->dev = &pdev->dev;
713 gpio->nr_ports = pdata->nports;
715 err = dwapb_get_reset(gpio);
719 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
720 sizeof(*gpio->ports), GFP_KERNEL);
724 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
725 if (IS_ERR(gpio->regs))
726 return PTR_ERR(gpio->regs);
728 err = dwapb_get_clks(gpio);
732 gpio->flags = (uintptr_t)device_get_match_data(dev);
734 for (i = 0; i < gpio->nr_ports; i++) {
735 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
740 platform_set_drvdata(pdev, gpio);
745 #ifdef CONFIG_PM_SLEEP
746 static int dwapb_gpio_suspend(struct device *dev)
748 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
749 struct gpio_chip *gc = &gpio->ports[0].gc;
753 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
754 for (i = 0; i < gpio->nr_ports; i++) {
756 unsigned int idx = gpio->ports[i].idx;
757 struct dwapb_context *ctx = gpio->ports[i].ctx;
759 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
760 ctx->dir = dwapb_read(gpio, offset);
762 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
763 ctx->data = dwapb_read(gpio, offset);
765 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
766 ctx->ext = dwapb_read(gpio, offset);
768 /* Only port A can provide interrupts */
770 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
771 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
772 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
773 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
774 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
776 /* Mask out interrupts */
777 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
780 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
782 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
787 static int dwapb_gpio_resume(struct device *dev)
789 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
790 struct gpio_chip *gc = &gpio->ports[0].gc;
794 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
796 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
800 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
801 for (i = 0; i < gpio->nr_ports; i++) {
803 unsigned int idx = gpio->ports[i].idx;
804 struct dwapb_context *ctx = gpio->ports[i].ctx;
806 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
807 dwapb_write(gpio, offset, ctx->data);
809 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
810 dwapb_write(gpio, offset, ctx->dir);
812 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
813 dwapb_write(gpio, offset, ctx->ext);
815 /* Only port A can provide interrupts */
817 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
818 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
819 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
820 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
821 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
823 /* Clear out spurious interrupts */
824 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
827 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
833 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
836 static struct platform_driver dwapb_gpio_driver = {
838 .name = DWAPB_DRIVER_NAME,
839 .pm = &dwapb_gpio_pm_ops,
840 .of_match_table = dwapb_of_match,
841 .acpi_match_table = dwapb_acpi_match,
843 .probe = dwapb_gpio_probe,
846 module_platform_driver(dwapb_gpio_driver);
848 MODULE_LICENSE("GPL");
849 MODULE_AUTHOR("Jamie Iles");
850 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
851 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);