1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011 Jamie Iles
5 * All enquiries to support@picochip.com
7 #include <linux/acpi.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24 #include <linux/reset.h>
25 #include <linux/spinlock.h>
26 #include <linux/platform_data/gpio-dwapb.h>
27 #include <linux/slab.h>
30 #include "gpiolib-acpi.h"
32 #define GPIO_SWPORTA_DR 0x00
33 #define GPIO_SWPORTA_DDR 0x04
34 #define GPIO_SWPORTB_DR 0x0c
35 #define GPIO_SWPORTB_DDR 0x10
36 #define GPIO_SWPORTC_DR 0x18
37 #define GPIO_SWPORTC_DDR 0x1c
38 #define GPIO_SWPORTD_DR 0x24
39 #define GPIO_SWPORTD_DDR 0x28
40 #define GPIO_INTEN 0x30
41 #define GPIO_INTMASK 0x34
42 #define GPIO_INTTYPE_LEVEL 0x38
43 #define GPIO_INT_POLARITY 0x3c
44 #define GPIO_INTSTATUS 0x40
45 #define GPIO_PORTA_DEBOUNCE 0x48
46 #define GPIO_PORTA_EOI 0x4c
47 #define GPIO_EXT_PORTA 0x50
48 #define GPIO_EXT_PORTB 0x54
49 #define GPIO_EXT_PORTC 0x58
50 #define GPIO_EXT_PORTD 0x5c
52 #define DWAPB_DRIVER_NAME "gpio-dwapb"
53 #define DWAPB_MAX_PORTS 4
55 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
56 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
57 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
59 #define GPIO_REG_OFFSET_V2 1
61 #define GPIO_INTMASK_V2 0x44
62 #define GPIO_INTTYPE_LEVEL_V2 0x34
63 #define GPIO_INT_POLARITY_V2 0x38
64 #define GPIO_INTSTATUS_V2 0x3c
65 #define GPIO_PORTA_EOI_V2 0x40
67 #define DWAPB_NR_CLOCKS 2
71 #ifdef CONFIG_PM_SLEEP
72 /* Store GPIO context across system-wide suspend/resume transitions */
73 struct dwapb_context {
86 struct dwapb_gpio_port {
89 struct dwapb_gpio *gpio;
90 #ifdef CONFIG_PM_SLEEP
91 struct dwapb_context *ctx;
99 struct dwapb_gpio_port *ports;
100 unsigned int nr_ports;
101 struct irq_domain *domain;
103 struct reset_control *rst;
104 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
107 static inline u32 gpio_reg_v2_convert(unsigned int offset)
111 return GPIO_INTMASK_V2;
112 case GPIO_INTTYPE_LEVEL:
113 return GPIO_INTTYPE_LEVEL_V2;
114 case GPIO_INT_POLARITY:
115 return GPIO_INT_POLARITY_V2;
117 return GPIO_INTSTATUS_V2;
119 return GPIO_PORTA_EOI_V2;
125 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
127 if (gpio->flags & GPIO_REG_OFFSET_V2)
128 return gpio_reg_v2_convert(offset);
133 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
135 struct gpio_chip *gc = &gpio->ports[0].gc;
136 void __iomem *reg_base = gpio->regs;
138 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
141 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
144 struct gpio_chip *gc = &gpio->ports[0].gc;
145 void __iomem *reg_base = gpio->regs;
147 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
150 static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
152 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
153 struct dwapb_gpio *gpio = port->gpio;
155 return irq_find_mapping(gpio->domain, offset);
158 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
160 struct dwapb_gpio_port *port;
163 for (i = 0; i < gpio->nr_ports; i++) {
164 port = &gpio->ports[i];
165 if (port->idx == offs / 32)
172 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
174 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
175 struct gpio_chip *gc;
183 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
184 /* Just read the current value right out of the data register */
185 val = gc->get(gc, offs % 32);
191 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
194 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
196 unsigned long irq_status;
197 irq_hw_number_t hwirq;
199 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
200 for_each_set_bit(hwirq, &irq_status, 32) {
201 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
202 u32 irq_type = irq_get_trigger_type(gpio_irq);
204 generic_handle_irq(gpio_irq);
206 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
207 dwapb_toggle_trigger(gpio, hwirq);
213 static void dwapb_irq_handler(struct irq_desc *desc)
215 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
216 struct irq_chip *chip = irq_desc_get_chip(desc);
218 chained_irq_enter(chip, desc);
220 chained_irq_exit(chip, desc);
223 static void dwapb_irq_enable(struct irq_data *d)
225 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
226 struct dwapb_gpio *gpio = igc->private;
227 struct gpio_chip *gc = &gpio->ports[0].gc;
231 spin_lock_irqsave(&gc->bgpio_lock, flags);
232 val = dwapb_read(gpio, GPIO_INTEN);
233 val |= BIT(irqd_to_hwirq(d));
234 dwapb_write(gpio, GPIO_INTEN, val);
235 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
238 static void dwapb_irq_disable(struct irq_data *d)
240 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
241 struct dwapb_gpio *gpio = igc->private;
242 struct gpio_chip *gc = &gpio->ports[0].gc;
246 spin_lock_irqsave(&gc->bgpio_lock, flags);
247 val = dwapb_read(gpio, GPIO_INTEN);
248 val &= ~BIT(irqd_to_hwirq(d));
249 dwapb_write(gpio, GPIO_INTEN, val);
250 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
253 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
255 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
256 struct dwapb_gpio *gpio = igc->private;
257 struct gpio_chip *gc = &gpio->ports[0].gc;
258 irq_hw_number_t bit = irqd_to_hwirq(d);
259 unsigned long level, polarity, flags;
261 if (type & ~IRQ_TYPE_SENSE_MASK)
264 spin_lock_irqsave(&gc->bgpio_lock, flags);
265 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
266 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
269 case IRQ_TYPE_EDGE_BOTH:
271 dwapb_toggle_trigger(gpio, bit);
273 case IRQ_TYPE_EDGE_RISING:
275 polarity |= BIT(bit);
277 case IRQ_TYPE_EDGE_FALLING:
279 polarity &= ~BIT(bit);
281 case IRQ_TYPE_LEVEL_HIGH:
283 polarity |= BIT(bit);
285 case IRQ_TYPE_LEVEL_LOW:
287 polarity &= ~BIT(bit);
291 irq_setup_alt_chip(d, type);
293 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
294 if (type != IRQ_TYPE_EDGE_BOTH)
295 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
296 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
301 #ifdef CONFIG_PM_SLEEP
302 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
304 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
305 struct dwapb_gpio *gpio = igc->private;
306 struct dwapb_context *ctx = gpio->ports[0].ctx;
307 irq_hw_number_t bit = irqd_to_hwirq(d);
310 ctx->wake_en |= BIT(bit);
312 ctx->wake_en &= ~BIT(bit);
318 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
319 unsigned offset, unsigned debounce)
321 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
322 struct dwapb_gpio *gpio = port->gpio;
323 unsigned long flags, val_deb;
324 unsigned long mask = BIT(offset);
326 spin_lock_irqsave(&gc->bgpio_lock, flags);
328 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
333 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
335 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
340 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
341 unsigned long config)
345 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
348 debounce = pinconf_to_config_argument(config);
349 return dwapb_gpio_set_debounce(gc, offset, debounce);
352 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
354 return IRQ_RETVAL(dwapb_do_irq(dev_id));
357 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
358 struct dwapb_gpio_port *port,
359 struct dwapb_port_property *pp)
361 struct gpio_chip *gc = &port->gc;
362 struct fwnode_handle *fwnode = pp->fwnode;
363 struct irq_chip_generic *irq_gc = NULL;
364 unsigned int ngpio = gc->ngpio;
365 struct irq_chip_type *ct;
366 irq_hw_number_t hwirq;
369 if (memchr_inv(pp->irq, 0, sizeof(pp->irq)) == NULL) {
370 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
374 gpio->domain = irq_domain_create_linear(fwnode, ngpio,
375 &irq_generic_chip_ops, gpio);
379 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
380 DWAPB_DRIVER_NAME, handle_bad_irq,
382 IRQ_GC_INIT_NESTED_LOCK);
384 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
385 irq_domain_remove(gpio->domain);
390 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
392 irq_domain_remove(gpio->domain);
397 irq_gc->reg_base = gpio->regs;
398 irq_gc->private = gpio;
400 for (i = 0; i < 2; i++) {
401 ct = &irq_gc->chip_types[i];
402 ct->chip.irq_ack = irq_gc_ack_set_bit;
403 ct->chip.irq_mask = irq_gc_mask_set_bit;
404 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
405 ct->chip.irq_set_type = dwapb_irq_set_type;
406 ct->chip.irq_enable = dwapb_irq_enable;
407 ct->chip.irq_disable = dwapb_irq_disable;
408 #ifdef CONFIG_PM_SLEEP
409 ct->chip.irq_set_wake = dwapb_irq_set_wake;
411 ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
412 ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
413 ct->type = IRQ_TYPE_LEVEL_MASK;
416 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
417 irq_gc->chip_types[0].handler = handle_level_irq;
418 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
419 irq_gc->chip_types[1].handler = handle_edge_irq;
421 if (!pp->irq_shared) {
424 for (i = 0; i < pp->ngpio; i++) {
426 irq_set_chained_handler_and_data(pp->irq[i],
427 dwapb_irq_handler, gpio);
431 * Request a shared IRQ since where MFD would have devices
432 * using the same irq pin
434 err = devm_request_irq(gpio->dev, pp->irq[0],
435 dwapb_irq_handler_mfd,
436 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
438 dev_err(gpio->dev, "error requesting IRQ\n");
439 irq_domain_remove(gpio->domain);
445 for (hwirq = 0; hwirq < ngpio; hwirq++)
446 irq_create_mapping(gpio->domain, hwirq);
448 port->gc.to_irq = dwapb_gpio_to_irq;
451 static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
453 struct dwapb_gpio_port *port = &gpio->ports[0];
454 struct gpio_chip *gc = &port->gc;
455 unsigned int ngpio = gc->ngpio;
456 irq_hw_number_t hwirq;
461 for (hwirq = 0; hwirq < ngpio; hwirq++)
462 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
464 irq_domain_remove(gpio->domain);
468 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
469 struct dwapb_port_property *pp,
472 struct dwapb_gpio_port *port;
473 void __iomem *dat, *set, *dirout;
476 port = &gpio->ports[offs];
480 #ifdef CONFIG_PM_SLEEP
481 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
486 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
487 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
488 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
490 /* This registers 32 GPIO lines per port */
491 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
494 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
499 #ifdef CONFIG_OF_GPIO
500 port->gc.of_node = to_of_node(pp->fwnode);
502 port->gc.ngpio = pp->ngpio;
503 port->gc.base = pp->gpio_base;
505 /* Only port A support debounce */
507 port->gc.set_config = dwapb_gpio_set_config;
509 /* Only port A can provide interrupts in all configurations of the IP */
511 dwapb_configure_irqs(gpio, port, pp);
513 err = gpiochip_add_data(&port->gc, port);
515 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
520 /* Add GPIO-signaled ACPI event support */
521 acpi_gpiochip_request_interrupts(&port->gc);
523 port->is_registered = true;
528 static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
532 for (m = 0; m < gpio->nr_ports; ++m) {
533 struct dwapb_gpio_port *port = &gpio->ports[m];
535 if (!port->is_registered)
538 acpi_gpiochip_free_interrupts(&port->gc);
539 gpiochip_remove(&port->gc);
543 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
544 struct dwapb_port_property *pp)
546 struct device_node *np = NULL;
549 if (fwnode_property_read_bool(fwnode, "interrupt-controller"))
550 np = to_of_node(fwnode);
552 for (j = 0; j < pp->ngpio; j++) {
554 irq = of_irq_get(np, j);
555 else if (has_acpi_companion(dev))
556 irq = platform_get_irq_optional(to_platform_device(dev), j);
562 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
564 struct fwnode_handle *fwnode;
565 struct dwapb_platform_data *pdata;
566 struct dwapb_port_property *pp;
570 nports = device_get_child_node_count(dev);
572 return ERR_PTR(-ENODEV);
574 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
576 return ERR_PTR(-ENOMEM);
578 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
579 if (!pdata->properties)
580 return ERR_PTR(-ENOMEM);
582 pdata->nports = nports;
585 device_for_each_child_node(dev, fwnode) {
586 pp = &pdata->properties[i++];
589 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
590 pp->idx >= DWAPB_MAX_PORTS) {
592 "missing/invalid port index for port%d\n", i);
593 fwnode_handle_put(fwnode);
594 return ERR_PTR(-EINVAL);
597 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
599 "failed to get number of gpios for port%d\n",
604 pp->irq_shared = false;
608 * Only port A can provide interrupts in all configurations of
612 dwapb_get_irq(dev, fwnode, pp);
618 static const struct of_device_id dwapb_of_match[] = {
619 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
620 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
623 MODULE_DEVICE_TABLE(of, dwapb_of_match);
625 static const struct acpi_device_id dwapb_acpi_match[] = {
628 {"APMC0D81", GPIO_REG_OFFSET_V2},
631 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
633 static int dwapb_gpio_probe(struct platform_device *pdev)
636 struct dwapb_gpio *gpio;
638 struct device *dev = &pdev->dev;
639 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
642 pdata = dwapb_gpio_get_pdata(dev);
644 return PTR_ERR(pdata);
650 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
654 gpio->dev = &pdev->dev;
655 gpio->nr_ports = pdata->nports;
657 gpio->rst = devm_reset_control_get_optional_shared(dev, NULL);
658 if (IS_ERR(gpio->rst))
659 return PTR_ERR(gpio->rst);
661 reset_control_deassert(gpio->rst);
663 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
664 sizeof(*gpio->ports), GFP_KERNEL);
668 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
669 if (IS_ERR(gpio->regs))
670 return PTR_ERR(gpio->regs);
672 /* Optional bus and debounce clocks */
673 gpio->clks[0].id = "bus";
674 gpio->clks[1].id = "db";
675 err = devm_clk_bulk_get_optional(&pdev->dev, DWAPB_NR_CLOCKS,
678 dev_err(&pdev->dev, "Cannot get APB/Debounce clocks\n");
682 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
684 dev_err(&pdev->dev, "Cannot enable APB/Debounce clocks\n");
688 gpio->flags = (uintptr_t)device_get_match_data(dev);
690 for (i = 0; i < gpio->nr_ports; i++) {
691 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
695 platform_set_drvdata(pdev, gpio);
700 dwapb_gpio_unregister(gpio);
701 dwapb_irq_teardown(gpio);
702 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
707 static int dwapb_gpio_remove(struct platform_device *pdev)
709 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
711 dwapb_gpio_unregister(gpio);
712 dwapb_irq_teardown(gpio);
713 reset_control_assert(gpio->rst);
714 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
719 #ifdef CONFIG_PM_SLEEP
720 static int dwapb_gpio_suspend(struct device *dev)
722 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
723 struct gpio_chip *gc = &gpio->ports[0].gc;
727 spin_lock_irqsave(&gc->bgpio_lock, flags);
728 for (i = 0; i < gpio->nr_ports; i++) {
730 unsigned int idx = gpio->ports[i].idx;
731 struct dwapb_context *ctx = gpio->ports[i].ctx;
733 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
734 ctx->dir = dwapb_read(gpio, offset);
736 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
737 ctx->data = dwapb_read(gpio, offset);
739 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
740 ctx->ext = dwapb_read(gpio, offset);
742 /* Only port A can provide interrupts */
744 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
745 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
746 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
747 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
748 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
750 /* Mask out interrupts */
751 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
754 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
756 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
761 static int dwapb_gpio_resume(struct device *dev)
763 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
764 struct gpio_chip *gc = &gpio->ports[0].gc;
768 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
770 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
774 spin_lock_irqsave(&gc->bgpio_lock, flags);
775 for (i = 0; i < gpio->nr_ports; i++) {
777 unsigned int idx = gpio->ports[i].idx;
778 struct dwapb_context *ctx = gpio->ports[i].ctx;
780 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
781 dwapb_write(gpio, offset, ctx->data);
783 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
784 dwapb_write(gpio, offset, ctx->dir);
786 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
787 dwapb_write(gpio, offset, ctx->ext);
789 /* Only port A can provide interrupts */
791 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
792 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
793 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
794 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
795 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
797 /* Clear out spurious interrupts */
798 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
801 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
807 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
810 static struct platform_driver dwapb_gpio_driver = {
812 .name = DWAPB_DRIVER_NAME,
813 .pm = &dwapb_gpio_pm_ops,
814 .of_match_table = dwapb_of_match,
815 .acpi_match_table = dwapb_acpi_match,
817 .probe = dwapb_gpio_probe,
818 .remove = dwapb_gpio_remove,
821 module_platform_driver(dwapb_gpio_driver);
823 MODULE_LICENSE("GPL");
824 MODULE_AUTHOR("Jamie Iles");
825 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
826 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);