2 * A FSI master controller, using a simple GPIO bit-banging interface
5 #include <linux/crc4.h>
6 #include <linux/delay.h>
7 #include <linux/device.h>
9 #include <linux/gpio/consumer.h>
11 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
17 #include "fsi-master.h"
19 #define FSI_GPIO_STD_DLY 1 /* Standard pin delay in nS */
20 #define FSI_ECHO_DELAY_CLOCKS 16 /* Number clocks for echo delay */
21 #define FSI_PRE_BREAK_CLOCKS 50 /* Number clocks to prep for break */
22 #define FSI_BREAK_CLOCKS 256 /* Number of clocks to issue break */
23 #define FSI_POST_BREAK_CLOCKS 16000 /* Number clocks to set up cfam */
24 #define FSI_INIT_CLOCKS 5000 /* Clock out any old data */
25 #define FSI_GPIO_DPOLL_CLOCKS 50 /* < 21 will cause slave to hang */
26 #define FSI_GPIO_EPOLL_CLOCKS 50 /* Number of clocks for E_POLL retry */
27 #define FSI_GPIO_STD_DELAY 10 /* Standard GPIO delay in nS */
28 /* todo: adjust down as low as */
29 /* possible or eliminate */
30 #define FSI_CRC_ERR_RETRIES 10
32 #define FSI_GPIO_CMD_DPOLL 0x2
33 #define FSI_GPIO_CMD_EPOLL 0x3
34 #define FSI_GPIO_CMD_TERM 0x3f
35 #define FSI_GPIO_CMD_ABS_AR 0x4
36 #define FSI_GPIO_CMD_REL_AR 0x5
37 #define FSI_GPIO_CMD_SAME_AR 0x3 /* but only a 2-bit opcode... */
40 #define FSI_GPIO_RESP_ACK 0 /* Success */
41 #define FSI_GPIO_RESP_BUSY 1 /* Slave busy */
42 #define FSI_GPIO_RESP_ERRA 2 /* Any (misc) Error */
43 #define FSI_GPIO_RESP_ERRC 3 /* Slave reports master CRC error */
44 #define FSI_GPIO_MTOE 4 /* Master time out error */
45 #define FSI_GPIO_CRC_INVAL 5 /* Master reports slave CRC error */
47 /* Normal slave responses */
48 #define FSI_GPIO_RESP_BUSY 1
49 #define FSI_GPIO_RESP_ACK 0
50 #define FSI_GPIO_RESP_ACKD 4
52 #define FSI_GPIO_MAX_BUSY 200
53 #define FSI_GPIO_MTOE_COUNT 1000
54 #define FSI_GPIO_DRAIN_BITS 20
55 #define FSI_GPIO_CRC_SIZE 4
56 #define FSI_GPIO_MSG_ID_SIZE 2
57 #define FSI_GPIO_MSG_RESPID_SIZE 2
58 #define FSI_GPIO_PRIME_SLAVE_CLOCKS 20
60 #define LAST_ADDR_INVALID 0x1
62 struct fsi_master_gpio {
63 struct fsi_master master;
65 struct mutex cmd_lock; /* mutex for command ordering */
66 spinlock_t bit_lock; /* lock for clocking bits out */
67 struct gpio_desc *gpio_clk;
68 struct gpio_desc *gpio_data;
69 struct gpio_desc *gpio_trans; /* Voltage translator */
70 struct gpio_desc *gpio_enable; /* FSI enable */
71 struct gpio_desc *gpio_mux; /* Mux control */
77 #define CREATE_TRACE_POINTS
78 #include <trace/events/fsi_master_gpio.h>
80 #define to_fsi_master_gpio(m) container_of(m, struct fsi_master_gpio, master)
87 static void clock_toggle(struct fsi_master_gpio *master, int count)
91 for (i = 0; i < count; i++) {
92 if (!master->no_delays)
93 ndelay(FSI_GPIO_STD_DLY);
94 gpiod_set_value(master->gpio_clk, 0);
95 if (!master->no_delays)
96 ndelay(FSI_GPIO_STD_DLY);
97 gpiod_set_value(master->gpio_clk, 1);
101 static int sda_clock_in(struct fsi_master_gpio *master)
105 if (!master->no_delays)
106 ndelay(FSI_GPIO_STD_DLY);
107 gpiod_set_value(master->gpio_clk, 0);
109 /* Dummy read to feed the synchronizers */
110 gpiod_get_value(master->gpio_data);
112 /* Actual data read */
113 in = gpiod_get_value(master->gpio_data);
114 if (!master->no_delays)
115 ndelay(FSI_GPIO_STD_DLY);
116 gpiod_set_value(master->gpio_clk, 1);
120 static void sda_out(struct fsi_master_gpio *master, int value)
122 gpiod_set_value(master->gpio_data, value);
125 static void set_sda_input(struct fsi_master_gpio *master)
127 gpiod_direction_input(master->gpio_data);
128 gpiod_set_value(master->gpio_trans, 0);
131 static void set_sda_output(struct fsi_master_gpio *master, int value)
133 gpiod_set_value(master->gpio_trans, 1);
134 gpiod_direction_output(master->gpio_data, value);
137 static void clock_zeros(struct fsi_master_gpio *master, int count)
139 set_sda_output(master, 1);
140 clock_toggle(master, count);
143 static void serial_in(struct fsi_master_gpio *master, struct fsi_gpio_msg *msg,
148 set_sda_input(master);
150 for (bit = 0; bit < num_bits; bit++) {
151 in_bit = sda_clock_in(master);
153 msg->msg |= ~in_bit & 0x1; /* Data is active low */
155 msg->bits += num_bits;
157 trace_fsi_master_gpio_in(master, num_bits, msg->msg);
160 static void serial_out(struct fsi_master_gpio *master,
161 const struct fsi_gpio_msg *cmd)
164 uint64_t msg = ~cmd->msg; /* Data is active low */
165 uint64_t sda_mask = 0x1ULL << (cmd->bits - 1);
166 uint64_t last_bit = ~0;
169 trace_fsi_master_gpio_out(master, cmd->bits, cmd->msg);
172 dev_warn(master->dev, "trying to output 0 bits\n");
175 set_sda_output(master, 0);
177 /* Send the start bit */
179 clock_toggle(master, 1);
181 /* Send the message */
182 for (bit = 0; bit < cmd->bits; bit++) {
183 next_bit = (msg & sda_mask) >> (cmd->bits - 1);
184 if (last_bit ^ next_bit) {
185 sda_out(master, next_bit);
188 clock_toggle(master, 1);
193 static void msg_push_bits(struct fsi_gpio_msg *msg, uint64_t data, int bits)
196 msg->msg |= data & ((1ull << bits) - 1);
200 static void msg_push_crc(struct fsi_gpio_msg *msg)
205 top = msg->bits & 0x3;
207 /* start bit, and any non-aligned top bits */
208 crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1);
211 crc = crc4(crc, msg->msg, msg->bits - top);
213 msg_push_bits(msg, crc, 4);
216 static bool check_same_address(struct fsi_master_gpio *master, int id,
219 /* this will also handle LAST_ADDR_INVALID */
220 return master->last_addr == (((id & 0x3) << 21) | (addr & ~0x3));
223 static bool check_relative_address(struct fsi_master_gpio *master, int id,
224 uint32_t addr, uint32_t *rel_addrp)
226 uint32_t last_addr = master->last_addr;
229 if (last_addr == LAST_ADDR_INVALID)
232 /* We may be in 23-bit addressing mode, which uses the id as the
233 * top two address bits. So, if we're referencing a different ID,
234 * use absolute addresses.
236 if (((last_addr >> 21) & 0x3) != id)
239 /* remove the top two bits from any 23-bit addressing */
240 last_addr &= (1 << 21) - 1;
242 /* We know that the addresses are limited to 21 bits, so this won't
243 * overflow the signed rel_addr */
244 rel_addr = addr - last_addr;
245 if (rel_addr > 255 || rel_addr < -256)
248 *rel_addrp = (uint32_t)rel_addr;
253 static void last_address_update(struct fsi_master_gpio *master,
254 int id, bool valid, uint32_t addr)
257 master->last_addr = LAST_ADDR_INVALID;
259 master->last_addr = ((id & 0x3) << 21) | (addr & ~0x3);
263 * Encode an Absolute/Relative/Same Address command
265 static void build_ar_command(struct fsi_master_gpio *master,
266 struct fsi_gpio_msg *cmd, uint8_t id,
267 uint32_t addr, size_t size, const void *data)
269 int i, addr_bits, opcode_bits;
277 /* we have 21 bits of address max */
278 addr &= ((1 << 21) - 1);
280 /* cmd opcodes are variable length - SAME_AR is only two bits */
283 if (check_same_address(master, id, addr)) {
284 /* we still address the byte offset within the word */
287 opcode = FSI_GPIO_CMD_SAME_AR;
289 } else if (check_relative_address(master, id, addr, &rel_addr)) {
290 /* 8 bits plus sign */
293 opcode = FSI_GPIO_CMD_REL_AR;
297 opcode = FSI_GPIO_CMD_ABS_AR;
301 * The read/write size is encoded in the lower bits of the address
302 * (as it must be naturally-aligned), and the following ds bit.
304 * size addr:1 addr:0 ds
310 ds = size > 1 ? 1 : 0;
315 msg_push_bits(cmd, id, 2);
316 msg_push_bits(cmd, opcode, opcode_bits);
317 msg_push_bits(cmd, write ? 0 : 1, 1);
318 msg_push_bits(cmd, addr, addr_bits);
319 msg_push_bits(cmd, ds, 1);
320 for (i = 0; write && i < size; i++)
321 msg_push_bits(cmd, ((uint8_t *)data)[i], 8);
326 static void build_dpoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
331 msg_push_bits(cmd, slave_id, 2);
332 msg_push_bits(cmd, FSI_GPIO_CMD_DPOLL, 3);
336 static void build_epoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
341 msg_push_bits(cmd, slave_id, 2);
342 msg_push_bits(cmd, FSI_GPIO_CMD_EPOLL, 3);
346 static void echo_delay(struct fsi_master_gpio *master)
348 set_sda_output(master, 1);
349 clock_toggle(master, FSI_ECHO_DELAY_CLOCKS);
352 static void build_term_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
357 msg_push_bits(cmd, slave_id, 2);
358 msg_push_bits(cmd, FSI_GPIO_CMD_TERM, 6);
363 * Store information on master errors so handler can detect and clean
366 static void fsi_master_gpio_error(struct fsi_master_gpio *master, int error)
372 * Note: callers rely specifically on this returning -EAGAIN for
373 * a CRC error detected in the response. Use other error code
374 * for other situations. It will be converted to something else
375 * higher up the stack before it reaches userspace.
377 static int read_one_response(struct fsi_master_gpio *master,
378 uint8_t data_size, struct fsi_gpio_msg *msgp, uint8_t *tagp)
380 struct fsi_gpio_msg msg;
386 spin_lock_irqsave(&master->bit_lock, flags);
388 /* wait for the start bit */
389 for (i = 0; i < FSI_GPIO_MTOE_COUNT; i++) {
392 serial_in(master, &msg, 1);
396 if (i == FSI_GPIO_MTOE_COUNT) {
398 "Master time out waiting for response\n");
399 fsi_master_gpio_error(master, FSI_GPIO_MTOE);
400 spin_unlock_irqrestore(&master->bit_lock, flags);
407 /* Read slave ID & response tag */
408 serial_in(master, &msg, 4);
412 /* If we have an ACK and we're expecting data, clock the data in too */
413 if (tag == FSI_GPIO_RESP_ACK && data_size)
414 serial_in(master, &msg, data_size * 8);
417 serial_in(master, &msg, FSI_GPIO_CRC_SIZE);
419 spin_unlock_irqrestore(&master->bit_lock, flags);
421 /* we have a whole message now; check CRC */
423 crc = crc4(crc, msg.msg, msg.bits);
425 dev_dbg(master->dev, "ERR response CRC\n");
426 fsi_master_gpio_error(master, FSI_GPIO_CRC_INVAL);
438 static int issue_term(struct fsi_master_gpio *master, uint8_t slave)
440 struct fsi_gpio_msg cmd;
445 build_term_command(&cmd, slave);
447 spin_lock_irqsave(&master->bit_lock, flags);
448 serial_out(master, &cmd);
450 spin_unlock_irqrestore(&master->bit_lock, flags);
452 rc = read_one_response(master, 0, NULL, &tag);
455 "TERM failed; lost communication with slave\n");
457 } else if (tag != FSI_GPIO_RESP_ACK) {
458 dev_err(master->dev, "TERM failed; response %d\n", tag);
465 static int poll_for_response(struct fsi_master_gpio *master,
466 uint8_t slave, uint8_t size, void *data)
468 struct fsi_gpio_msg response, cmd;
469 int busy_count = 0, rc, i;
472 uint8_t *data_byte = data;
473 int crc_err_retries = 0;
475 rc = read_one_response(master, size, &response, &tag);
477 /* Handle retries on CRC errors */
479 /* Too many retries ? */
480 if (crc_err_retries++ > FSI_CRC_ERR_RETRIES) {
482 * Pass it up as a -EIO otherwise upper level will retry
483 * the whole command which isn't what we want here.
489 "CRC error retry %d\n", crc_err_retries);
490 trace_fsi_master_gpio_crc_rsp_error(master);
491 build_epoll_command(&cmd, slave);
492 spin_lock_irqsave(&master->bit_lock, flags);
493 clock_zeros(master, FSI_GPIO_EPOLL_CLOCKS);
494 serial_out(master, &cmd);
496 spin_unlock_irqrestore(&master->bit_lock, flags);
502 case FSI_GPIO_RESP_ACK:
504 uint64_t val = response.msg;
505 /* clear crc & mask */
507 val &= (1ull << (size * 8)) - 1;
509 for (i = 0; i < size; i++) {
510 data_byte[size-i-1] = val;
515 case FSI_GPIO_RESP_BUSY:
517 * Its necessary to clock slave before issuing
518 * d-poll, not indicated in the hardware protocol
519 * spec. < 20 clocks causes slave to hang, 21 ok.
521 if (busy_count++ < FSI_GPIO_MAX_BUSY) {
522 build_dpoll_command(&cmd, slave);
523 spin_lock_irqsave(&master->bit_lock, flags);
524 clock_zeros(master, FSI_GPIO_DPOLL_CLOCKS);
525 serial_out(master, &cmd);
527 spin_unlock_irqrestore(&master->bit_lock, flags);
530 dev_warn(master->dev,
531 "ERR slave is stuck in busy state, issuing TERM\n");
532 spin_lock_irqsave(&master->bit_lock, flags);
533 clock_zeros(master, FSI_GPIO_DPOLL_CLOCKS);
534 spin_unlock_irqrestore(&master->bit_lock, flags);
535 issue_term(master, slave);
539 case FSI_GPIO_RESP_ERRA:
540 dev_dbg(master->dev, "ERRA received: 0x%x\n", (int)response.msg);
541 fsi_master_gpio_error(master, response.msg);
544 case FSI_GPIO_RESP_ERRC:
545 dev_dbg(master->dev, "ERRC received: 0x%x\n", (int)response.msg);
546 fsi_master_gpio_error(master, response.msg);
547 trace_fsi_master_gpio_crc_cmd_error(master);
553 trace_fsi_master_gpio_poll_response_busy(master, busy_count);
555 /* Clock the slave enough to be ready for next operation */
556 spin_lock_irqsave(&master->bit_lock, flags);
557 clock_zeros(master, FSI_GPIO_PRIME_SLAVE_CLOCKS);
558 spin_unlock_irqrestore(&master->bit_lock, flags);
562 static int send_request(struct fsi_master_gpio *master,
563 struct fsi_gpio_msg *cmd)
567 spin_lock_irqsave(&master->bit_lock, flags);
568 if (master->external_mode) {
569 spin_unlock_irqrestore(&master->bit_lock, flags);
573 serial_out(master, cmd);
575 spin_unlock_irqrestore(&master->bit_lock, flags);
580 static int fsi_master_gpio_xfer(struct fsi_master_gpio *master, uint8_t slave,
581 struct fsi_gpio_msg *cmd, size_t resp_len, void *resp)
583 int rc = -EAGAIN, retries = 0;
585 while ((retries++) < FSI_CRC_ERR_RETRIES) {
586 rc = send_request(master, cmd);
589 rc = poll_for_response(master, slave, resp_len, resp);
593 dev_warn(master->dev, "ECRC retry %d\n", retries);
595 /* Pace it a bit before retry */
602 static int fsi_master_gpio_read(struct fsi_master *_master, int link,
603 uint8_t id, uint32_t addr, void *val, size_t size)
605 struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
606 struct fsi_gpio_msg cmd;
612 mutex_lock(&master->cmd_lock);
613 build_ar_command(master, &cmd, id, addr, size, NULL);
614 rc = fsi_master_gpio_xfer(master, id, &cmd, size, val);
615 last_address_update(master, id, rc == 0, addr);
616 mutex_unlock(&master->cmd_lock);
621 static int fsi_master_gpio_write(struct fsi_master *_master, int link,
622 uint8_t id, uint32_t addr, const void *val, size_t size)
624 struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
625 struct fsi_gpio_msg cmd;
631 mutex_lock(&master->cmd_lock);
632 build_ar_command(master, &cmd, id, addr, size, val);
633 rc = fsi_master_gpio_xfer(master, id, &cmd, 0, NULL);
634 last_address_update(master, id, rc == 0, addr);
635 mutex_unlock(&master->cmd_lock);
640 static int fsi_master_gpio_term(struct fsi_master *_master,
641 int link, uint8_t id)
643 struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
644 struct fsi_gpio_msg cmd;
650 mutex_lock(&master->cmd_lock);
651 build_term_command(&cmd, id);
652 rc = fsi_master_gpio_xfer(master, id, &cmd, 0, NULL);
653 last_address_update(master, id, false, 0);
654 mutex_unlock(&master->cmd_lock);
659 static int fsi_master_gpio_break(struct fsi_master *_master, int link)
661 struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
667 trace_fsi_master_gpio_break(master);
669 mutex_lock(&master->cmd_lock);
670 if (master->external_mode) {
671 mutex_unlock(&master->cmd_lock);
675 spin_lock_irqsave(&master->bit_lock, flags);
677 set_sda_output(master, 1);
679 clock_toggle(master, FSI_PRE_BREAK_CLOCKS);
681 clock_toggle(master, FSI_BREAK_CLOCKS);
684 clock_toggle(master, FSI_POST_BREAK_CLOCKS);
686 spin_unlock_irqrestore(&master->bit_lock, flags);
687 last_address_update(master, 0, false, 0);
688 mutex_unlock(&master->cmd_lock);
690 /* Wait for logic reset to take effect */
696 static void fsi_master_gpio_init(struct fsi_master_gpio *master)
700 gpiod_direction_output(master->gpio_mux, 1);
701 gpiod_direction_output(master->gpio_trans, 1);
702 gpiod_direction_output(master->gpio_enable, 1);
703 gpiod_direction_output(master->gpio_clk, 1);
704 gpiod_direction_output(master->gpio_data, 1);
706 /* todo: evaluate if clocks can be reduced */
707 spin_lock_irqsave(&master->bit_lock, flags);
708 clock_zeros(master, FSI_INIT_CLOCKS);
709 spin_unlock_irqrestore(&master->bit_lock, flags);
712 static void fsi_master_gpio_init_external(struct fsi_master_gpio *master)
714 gpiod_direction_output(master->gpio_mux, 0);
715 gpiod_direction_output(master->gpio_trans, 0);
716 gpiod_direction_output(master->gpio_enable, 1);
717 gpiod_direction_input(master->gpio_clk);
718 gpiod_direction_input(master->gpio_data);
721 static int fsi_master_gpio_link_enable(struct fsi_master *_master, int link)
723 struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
729 mutex_lock(&master->cmd_lock);
730 if (!master->external_mode) {
731 gpiod_set_value(master->gpio_enable, 1);
734 mutex_unlock(&master->cmd_lock);
739 static ssize_t external_mode_show(struct device *dev,
740 struct device_attribute *attr, char *buf)
742 struct fsi_master_gpio *master = dev_get_drvdata(dev);
744 return snprintf(buf, PAGE_SIZE - 1, "%u\n",
745 master->external_mode ? 1 : 0);
748 static ssize_t external_mode_store(struct device *dev,
749 struct device_attribute *attr, const char *buf, size_t count)
751 struct fsi_master_gpio *master = dev_get_drvdata(dev);
756 err = kstrtoul(buf, 0, &val);
760 external_mode = !!val;
762 mutex_lock(&master->cmd_lock);
764 if (external_mode == master->external_mode) {
765 mutex_unlock(&master->cmd_lock);
769 master->external_mode = external_mode;
770 if (master->external_mode)
771 fsi_master_gpio_init_external(master);
773 fsi_master_gpio_init(master);
775 mutex_unlock(&master->cmd_lock);
777 fsi_master_rescan(&master->master);
782 static DEVICE_ATTR(external_mode, 0664,
783 external_mode_show, external_mode_store);
785 static int fsi_master_gpio_probe(struct platform_device *pdev)
787 struct fsi_master_gpio *master;
788 struct gpio_desc *gpio;
791 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
795 master->dev = &pdev->dev;
796 master->master.dev.parent = master->dev;
797 master->master.dev.of_node = of_node_get(dev_of_node(master->dev));
798 master->last_addr = LAST_ADDR_INVALID;
800 gpio = devm_gpiod_get(&pdev->dev, "clock", 0);
802 dev_err(&pdev->dev, "failed to get clock gpio\n");
803 return PTR_ERR(gpio);
805 master->gpio_clk = gpio;
807 gpio = devm_gpiod_get(&pdev->dev, "data", 0);
809 dev_err(&pdev->dev, "failed to get data gpio\n");
810 return PTR_ERR(gpio);
812 master->gpio_data = gpio;
815 gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0);
817 dev_err(&pdev->dev, "failed to get trans gpio\n");
818 return PTR_ERR(gpio);
820 master->gpio_trans = gpio;
822 gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0);
824 dev_err(&pdev->dev, "failed to get enable gpio\n");
825 return PTR_ERR(gpio);
827 master->gpio_enable = gpio;
829 gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0);
831 dev_err(&pdev->dev, "failed to get mux gpio\n");
832 return PTR_ERR(gpio);
834 master->gpio_mux = gpio;
837 * Check if GPIO block is slow enought that no extra delays
838 * are necessary. This improves performance on ast2500 by
839 * an order of magnitude.
841 master->no_delays = device_property_present(&pdev->dev, "no-gpio-delays");
843 master->master.n_links = 1;
844 master->master.flags = FSI_MASTER_FLAG_SWCLOCK;
845 master->master.read = fsi_master_gpio_read;
846 master->master.write = fsi_master_gpio_write;
847 master->master.term = fsi_master_gpio_term;
848 master->master.send_break = fsi_master_gpio_break;
849 master->master.link_enable = fsi_master_gpio_link_enable;
850 platform_set_drvdata(pdev, master);
851 spin_lock_init(&master->bit_lock);
852 mutex_init(&master->cmd_lock);
854 fsi_master_gpio_init(master);
856 rc = device_create_file(&pdev->dev, &dev_attr_external_mode);
860 return fsi_master_register(&master->master);
864 static int fsi_master_gpio_remove(struct platform_device *pdev)
866 struct fsi_master_gpio *master = platform_get_drvdata(pdev);
868 devm_gpiod_put(&pdev->dev, master->gpio_clk);
869 devm_gpiod_put(&pdev->dev, master->gpio_data);
870 if (master->gpio_trans)
871 devm_gpiod_put(&pdev->dev, master->gpio_trans);
872 if (master->gpio_enable)
873 devm_gpiod_put(&pdev->dev, master->gpio_enable);
874 if (master->gpio_mux)
875 devm_gpiod_put(&pdev->dev, master->gpio_mux);
876 fsi_master_unregister(&master->master);
878 of_node_put(master->master.dev.of_node);
883 static const struct of_device_id fsi_master_gpio_match[] = {
884 { .compatible = "fsi-master-gpio" },
888 static struct platform_driver fsi_master_gpio_driver = {
890 .name = "fsi-master-gpio",
891 .of_match_table = fsi_master_gpio_match,
893 .probe = fsi_master_gpio_probe,
894 .remove = fsi_master_gpio_remove,
897 module_platform_driver(fsi_master_gpio_driver);
898 MODULE_LICENSE("GPL");