1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Device Feature List (DFL) PCIe device
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
8 * Zhang Yi <Yi.Z.Zhang@intel.com>
9 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
10 * Joseph Grecco <joe.grecco@intel.com>
11 * Enno Luebbers <enno.luebbers@intel.com>
12 * Tim Whisonant <tim.whisonant@intel.com>
13 * Ananda Ravuri <ananda.ravuri@intel.com>
14 * Henry Mitchel <henry.mitchel@intel.com>
17 #include <linux/pci.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/stddef.h>
23 #include <linux/errno.h>
24 #include <linux/aer.h>
28 #define DRV_VERSION "0.8"
29 #define DRV_NAME "dfl-pci"
31 #define PCI_VSEC_ID_INTEL_DFLS 0x43
33 #define PCI_VNDR_DFLS_CNT 0x8
34 #define PCI_VNDR_DFLS_RES 0xc
36 #define PCI_VNDR_DFLS_RES_BAR_MASK GENMASK(2, 0)
37 #define PCI_VNDR_DFLS_RES_OFF_MASK GENMASK(31, 3)
40 struct dfl_fpga_cdev *cdev; /* container device */
43 static void __iomem *cci_pci_ioremap_bar0(struct pci_dev *pcidev)
45 if (pcim_iomap_regions(pcidev, BIT(0), DRV_NAME))
48 return pcim_iomap_table(pcidev)[0];
51 static int cci_pci_alloc_irq(struct pci_dev *pcidev)
53 int ret, nvec = pci_msix_vec_count(pcidev);
56 dev_dbg(&pcidev->dev, "fpga interrupt not supported\n");
60 ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX);
67 static void cci_pci_free_irq(struct pci_dev *pcidev)
69 pci_free_irq_vectors(pcidev);
73 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
74 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
75 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
76 #define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30
77 #define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B
78 #define PCIE_DEVICE_ID_SILICOM_PAC_N5010 0x1000
79 #define PCIE_DEVICE_ID_SILICOM_PAC_N5011 0x1001
82 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
83 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
84 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
85 #define PCIE_DEVICE_ID_INTEL_PAC_D5005_VF 0x0B2C
87 static struct pci_device_id cci_pcie_id_tbl[] = {
88 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
89 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
90 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
91 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
92 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
93 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
94 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
95 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
96 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
97 {PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),},
98 {PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),},
101 MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
103 static int cci_init_drvdata(struct pci_dev *pcidev)
105 struct cci_drvdata *drvdata;
107 drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
111 pci_set_drvdata(pcidev, drvdata);
116 static void cci_remove_feature_devs(struct pci_dev *pcidev)
118 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
120 /* remove all children feature devices */
121 dfl_fpga_feature_devs_remove(drvdata->cdev);
122 cci_pci_free_irq(pcidev);
125 static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec)
130 table = kcalloc(nvec, sizeof(int), GFP_KERNEL);
134 for (i = 0; i < nvec; i++)
135 table[i] = pci_irq_vector(pcidev, i);
140 static int find_dfls_by_vsec(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info)
142 u32 bir, offset, vndr_hdr, dfl_cnt, dfl_res;
143 int dfl_res_off, i, bars, voff = 0;
144 resource_size_t start, len;
146 while ((voff = pci_find_next_ext_capability(pcidev, voff, PCI_EXT_CAP_ID_VNDR))) {
148 pci_read_config_dword(pcidev, voff + PCI_VNDR_HEADER, &vndr_hdr);
150 if (PCI_VNDR_HEADER_ID(vndr_hdr) == PCI_VSEC_ID_INTEL_DFLS &&
151 pcidev->vendor == PCI_VENDOR_ID_INTEL)
156 dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__);
161 pci_read_config_dword(pcidev, voff + PCI_VNDR_DFLS_CNT, &dfl_cnt);
162 if (dfl_cnt > PCI_STD_NUM_BARS) {
163 dev_err(&pcidev->dev, "%s too many DFLs %d > %d\n",
164 __func__, dfl_cnt, PCI_STD_NUM_BARS);
168 dfl_res_off = voff + PCI_VNDR_DFLS_RES;
169 if (dfl_res_off + (dfl_cnt * sizeof(u32)) > PCI_CFG_SPACE_EXP_SIZE) {
170 dev_err(&pcidev->dev, "%s DFL VSEC too big for PCIe config space\n",
175 for (i = 0, bars = 0; i < dfl_cnt; i++, dfl_res_off += sizeof(u32)) {
176 dfl_res = GENMASK(31, 0);
177 pci_read_config_dword(pcidev, dfl_res_off, &dfl_res);
179 bir = dfl_res & PCI_VNDR_DFLS_RES_BAR_MASK;
180 if (bir >= PCI_STD_NUM_BARS) {
181 dev_err(&pcidev->dev, "%s bad bir number %d\n",
186 if (bars & BIT(bir)) {
187 dev_err(&pcidev->dev, "%s DFL for BAR %d already specified\n",
194 len = pci_resource_len(pcidev, bir);
195 offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK;
197 dev_err(&pcidev->dev, "%s bad offset %u >= %pa\n",
198 __func__, offset, &len);
202 dev_dbg(&pcidev->dev, "%s BAR %d offset 0x%x\n", __func__, bir, offset);
206 start = pci_resource_start(pcidev, bir) + offset;
208 dfl_fpga_enum_info_add_dfl(info, start, len);
214 /* default method of finding dfls starting at offset 0 of bar 0 */
215 static int find_dfls_by_default(struct pci_dev *pcidev,
216 struct dfl_fpga_enum_info *info)
218 int port_num, bar, i, ret = 0;
219 resource_size_t start, len;
224 /* start to find Device Feature List from Bar 0 */
225 base = cci_pci_ioremap_bar0(pcidev);
230 * PF device has FME and Ports/AFUs, and VF device only has one
231 * Port/AFU. Check them and add related "Device Feature List" info
232 * for the next step enumeration.
234 if (dfl_feature_is_fme(base)) {
235 start = pci_resource_start(pcidev, 0);
236 len = pci_resource_len(pcidev, 0);
238 dfl_fpga_enum_info_add_dfl(info, start, len);
241 * find more Device Feature Lists (e.g. Ports) per information
242 * indicated by FME module.
244 v = readq(base + FME_HDR_CAP);
245 port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
247 WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);
249 for (i = 0; i < port_num; i++) {
250 v = readq(base + FME_HDR_PORT_OFST(i));
252 /* skip ports which are not implemented. */
253 if (!(v & FME_PORT_OFST_IMP))
257 * add Port's Device Feature List information for next
260 bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
261 offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
262 start = pci_resource_start(pcidev, bar) + offset;
263 len = pci_resource_len(pcidev, bar) - offset;
265 dfl_fpga_enum_info_add_dfl(info, start, len);
267 } else if (dfl_feature_is_port(base)) {
268 start = pci_resource_start(pcidev, 0);
269 len = pci_resource_len(pcidev, 0);
271 dfl_fpga_enum_info_add_dfl(info, start, len);
276 /* release I/O mappings for next step enumeration */
277 pcim_iounmap_regions(pcidev, BIT(0));
282 /* enumerate feature devices under pci device */
283 static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
285 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
286 struct dfl_fpga_enum_info *info;
287 struct dfl_fpga_cdev *cdev;
291 /* allocate enumeration info via pci_dev */
292 info = dfl_fpga_enum_info_alloc(&pcidev->dev);
296 /* add irq info for enumeration if the device support irq */
297 nvec = cci_pci_alloc_irq(pcidev);
299 dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);
301 goto enum_info_free_exit;
303 irq_table = cci_pci_create_irq_table(pcidev, nvec);
309 ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table);
315 ret = find_dfls_by_vsec(pcidev, info);
317 ret = find_dfls_by_default(pcidev, info);
322 /* start enumeration with prepared enumeration information */
323 cdev = dfl_fpga_feature_devs_enumerate(info);
325 dev_err(&pcidev->dev, "Enumeration failure\n");
330 drvdata->cdev = cdev;
334 cci_pci_free_irq(pcidev);
336 dfl_fpga_enum_info_free(info);
342 int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
346 ret = pcim_enable_device(pcidev);
348 dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
352 ret = pci_enable_pcie_error_reporting(pcidev);
353 if (ret && ret != -EINVAL)
354 dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);
356 pci_set_master(pcidev);
358 ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64));
360 ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32));
362 dev_err(&pcidev->dev, "No suitable DMA support available.\n");
363 goto disable_error_report_exit;
366 ret = cci_init_drvdata(pcidev);
368 dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
369 goto disable_error_report_exit;
372 ret = cci_enumerate_feature_devs(pcidev);
376 dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
378 disable_error_report_exit:
379 pci_disable_pcie_error_reporting(pcidev);
383 static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
385 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
386 struct dfl_fpga_cdev *cdev = drvdata->cdev;
390 * disable SRIOV and then put released ports back to default
393 pci_disable_sriov(pcidev);
395 dfl_fpga_cdev_config_ports_pf(cdev);
401 * before enable SRIOV, put released ports into VF access mode
404 ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs);
408 ret = pci_enable_sriov(pcidev, num_vfs);
410 dfl_fpga_cdev_config_ports_pf(cdev);
418 static void cci_pci_remove(struct pci_dev *pcidev)
420 if (dev_is_pf(&pcidev->dev))
421 cci_pci_sriov_configure(pcidev, 0);
423 cci_remove_feature_devs(pcidev);
424 pci_disable_pcie_error_reporting(pcidev);
427 static struct pci_driver cci_pci_driver = {
429 .id_table = cci_pcie_id_tbl,
430 .probe = cci_pci_probe,
431 .remove = cci_pci_remove,
432 .sriov_configure = cci_pci_sriov_configure,
435 module_pci_driver(cci_pci_driver);
437 MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
438 MODULE_AUTHOR("Intel Corporation");
439 MODULE_LICENSE("GPL v2");