1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
8 * Kang Luwei <luwei.kang@intel.com>
9 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
10 * Joseph Grecco <joe.grecco@intel.com>
11 * Enno Luebbers <enno.luebbers@intel.com>
12 * Tim Whisonant <tim.whisonant@intel.com>
13 * Ananda Ravuri <ananda.ravuri@intel.com>
14 * Henry Mitchel <henry.mitchel@intel.com>
17 #include <linux/hwmon.h>
18 #include <linux/hwmon-sysfs.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/uaccess.h>
22 #include <linux/fpga-dfl.h>
27 static ssize_t ports_num_show(struct device *dev,
28 struct device_attribute *attr, char *buf)
33 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
35 v = readq(base + FME_HDR_CAP);
37 return scnprintf(buf, PAGE_SIZE, "%u\n",
38 (unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v));
40 static DEVICE_ATTR_RO(ports_num);
43 * Bitstream (static FPGA region) identifier number. It contains the
44 * detailed version and other information of this static FPGA region.
46 static ssize_t bitstream_id_show(struct device *dev,
47 struct device_attribute *attr, char *buf)
52 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
54 v = readq(base + FME_HDR_BITSTREAM_ID);
56 return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
58 static DEVICE_ATTR_RO(bitstream_id);
61 * Bitstream (static FPGA region) meta data. It contains the synthesis
62 * date, seed and other information of this static FPGA region.
64 static ssize_t bitstream_metadata_show(struct device *dev,
65 struct device_attribute *attr, char *buf)
70 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
72 v = readq(base + FME_HDR_BITSTREAM_MD);
74 return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
76 static DEVICE_ATTR_RO(bitstream_metadata);
78 static ssize_t cache_size_show(struct device *dev,
79 struct device_attribute *attr, char *buf)
84 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
86 v = readq(base + FME_HDR_CAP);
88 return sprintf(buf, "%u\n",
89 (unsigned int)FIELD_GET(FME_CAP_CACHE_SIZE, v));
91 static DEVICE_ATTR_RO(cache_size);
93 static ssize_t fabric_version_show(struct device *dev,
94 struct device_attribute *attr, char *buf)
99 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
101 v = readq(base + FME_HDR_CAP);
103 return sprintf(buf, "%u\n",
104 (unsigned int)FIELD_GET(FME_CAP_FABRIC_VERID, v));
106 static DEVICE_ATTR_RO(fabric_version);
108 static ssize_t socket_id_show(struct device *dev,
109 struct device_attribute *attr, char *buf)
114 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
116 v = readq(base + FME_HDR_CAP);
118 return sprintf(buf, "%u\n",
119 (unsigned int)FIELD_GET(FME_CAP_SOCKET_ID, v));
121 static DEVICE_ATTR_RO(socket_id);
123 static struct attribute *fme_hdr_attrs[] = {
124 &dev_attr_ports_num.attr,
125 &dev_attr_bitstream_id.attr,
126 &dev_attr_bitstream_metadata.attr,
127 &dev_attr_cache_size.attr,
128 &dev_attr_fabric_version.attr,
129 &dev_attr_socket_id.attr,
133 static const struct attribute_group fme_hdr_group = {
134 .attrs = fme_hdr_attrs,
137 static long fme_hdr_ioctl_release_port(struct dfl_feature_platform_data *pdata,
140 struct dfl_fpga_cdev *cdev = pdata->dfl_cdev;
143 if (get_user(port_id, (int __user *)arg))
146 return dfl_fpga_cdev_release_port(cdev, port_id);
149 static long fme_hdr_ioctl_assign_port(struct dfl_feature_platform_data *pdata,
152 struct dfl_fpga_cdev *cdev = pdata->dfl_cdev;
155 if (get_user(port_id, (int __user *)arg))
158 return dfl_fpga_cdev_assign_port(cdev, port_id);
161 static long fme_hdr_ioctl(struct platform_device *pdev,
162 struct dfl_feature *feature,
163 unsigned int cmd, unsigned long arg)
165 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
168 case DFL_FPGA_FME_PORT_RELEASE:
169 return fme_hdr_ioctl_release_port(pdata, arg);
170 case DFL_FPGA_FME_PORT_ASSIGN:
171 return fme_hdr_ioctl_assign_port(pdata, arg);
177 static const struct dfl_feature_id fme_hdr_id_table[] = {
178 {.id = FME_FEATURE_ID_HEADER,},
182 static const struct dfl_feature_ops fme_hdr_ops = {
183 .ioctl = fme_hdr_ioctl,
186 #define FME_THERM_THRESHOLD 0x8
187 #define TEMP_THRESHOLD1 GENMASK_ULL(6, 0)
188 #define TEMP_THRESHOLD1_EN BIT_ULL(7)
189 #define TEMP_THRESHOLD2 GENMASK_ULL(14, 8)
190 #define TEMP_THRESHOLD2_EN BIT_ULL(15)
191 #define TRIP_THRESHOLD GENMASK_ULL(30, 24)
192 #define TEMP_THRESHOLD1_STATUS BIT_ULL(32) /* threshold1 reached */
193 #define TEMP_THRESHOLD2_STATUS BIT_ULL(33) /* threshold2 reached */
194 /* threshold1 policy: 0 - AP2 (90% throttle) / 1 - AP1 (50% throttle) */
195 #define TEMP_THRESHOLD1_POLICY BIT_ULL(44)
197 #define FME_THERM_RDSENSOR_FMT1 0x10
198 #define FPGA_TEMPERATURE GENMASK_ULL(6, 0)
200 #define FME_THERM_CAP 0x20
201 #define THERM_NO_THROTTLE BIT_ULL(0)
205 static bool fme_thermal_throttle_support(void __iomem *base)
207 u64 v = readq(base + FME_THERM_CAP);
209 return FIELD_GET(THERM_NO_THROTTLE, v) ? false : true;
212 static umode_t thermal_hwmon_attrs_visible(const void *drvdata,
213 enum hwmon_sensor_types type,
214 u32 attr, int channel)
216 const struct dfl_feature *feature = drvdata;
218 /* temperature is always supported, and check hardware cap for others */
219 if (attr == hwmon_temp_input)
222 return fme_thermal_throttle_support(feature->ioaddr) ? 0444 : 0;
225 static int thermal_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
226 u32 attr, int channel, long *val)
228 struct dfl_feature *feature = dev_get_drvdata(dev);
232 case hwmon_temp_input:
233 v = readq(feature->ioaddr + FME_THERM_RDSENSOR_FMT1);
234 *val = (long)(FIELD_GET(FPGA_TEMPERATURE, v) * 1000);
237 v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
238 *val = (long)(FIELD_GET(TEMP_THRESHOLD1, v) * 1000);
240 case hwmon_temp_crit:
241 v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
242 *val = (long)(FIELD_GET(TEMP_THRESHOLD2, v) * 1000);
244 case hwmon_temp_emergency:
245 v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
246 *val = (long)(FIELD_GET(TRIP_THRESHOLD, v) * 1000);
248 case hwmon_temp_max_alarm:
249 v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
250 *val = (long)FIELD_GET(TEMP_THRESHOLD1_STATUS, v);
252 case hwmon_temp_crit_alarm:
253 v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
254 *val = (long)FIELD_GET(TEMP_THRESHOLD2_STATUS, v);
263 static const struct hwmon_ops thermal_hwmon_ops = {
264 .is_visible = thermal_hwmon_attrs_visible,
265 .read = thermal_hwmon_read,
268 static const struct hwmon_channel_info *thermal_hwmon_info[] = {
269 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_EMERGENCY |
270 HWMON_T_MAX | HWMON_T_MAX_ALARM |
271 HWMON_T_CRIT | HWMON_T_CRIT_ALARM),
275 static const struct hwmon_chip_info thermal_hwmon_chip_info = {
276 .ops = &thermal_hwmon_ops,
277 .info = thermal_hwmon_info,
280 static ssize_t temp1_max_policy_show(struct device *dev,
281 struct device_attribute *attr, char *buf)
283 struct dfl_feature *feature = dev_get_drvdata(dev);
286 v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
288 return sprintf(buf, "%u\n",
289 (unsigned int)FIELD_GET(TEMP_THRESHOLD1_POLICY, v));
292 static DEVICE_ATTR_RO(temp1_max_policy);
294 static struct attribute *thermal_extra_attrs[] = {
295 &dev_attr_temp1_max_policy.attr,
299 static umode_t thermal_extra_attrs_visible(struct kobject *kobj,
300 struct attribute *attr, int index)
302 struct device *dev = kobj_to_dev(kobj);
303 struct dfl_feature *feature = dev_get_drvdata(dev);
305 return fme_thermal_throttle_support(feature->ioaddr) ? attr->mode : 0;
308 static const struct attribute_group thermal_extra_group = {
309 .attrs = thermal_extra_attrs,
310 .is_visible = thermal_extra_attrs_visible,
312 __ATTRIBUTE_GROUPS(thermal_extra);
314 static int fme_thermal_mgmt_init(struct platform_device *pdev,
315 struct dfl_feature *feature)
317 struct device *hwmon;
320 * create hwmon to allow userspace monitoring temperature and other
321 * threshold information.
323 * temp1_input -> FPGA device temperature
324 * temp1_max -> hardware threshold 1 -> 50% or 90% throttling
325 * temp1_crit -> hardware threshold 2 -> 100% throttling
326 * temp1_emergency -> hardware trip_threshold to shutdown FPGA
327 * temp1_max_alarm -> hardware threshold 1 alarm
328 * temp1_crit_alarm -> hardware threshold 2 alarm
330 * create device specific sysfs interfaces, e.g. read temp1_max_policy
331 * to understand the actual hardware throttling action (50% vs 90%).
333 * If hardware doesn't support automatic throttling per thresholds,
334 * then all above sysfs interfaces are not visible except temp1_input
337 hwmon = devm_hwmon_device_register_with_info(&pdev->dev,
338 "dfl_fme_thermal", feature,
339 &thermal_hwmon_chip_info,
340 thermal_extra_groups);
342 dev_err(&pdev->dev, "Fail to register thermal hwmon\n");
343 return PTR_ERR(hwmon);
349 static const struct dfl_feature_id fme_thermal_mgmt_id_table[] = {
350 {.id = FME_FEATURE_ID_THERMAL_MGMT,},
354 static const struct dfl_feature_ops fme_thermal_mgmt_ops = {
355 .init = fme_thermal_mgmt_init,
358 static struct dfl_feature_driver fme_feature_drvs[] = {
360 .id_table = fme_hdr_id_table,
364 .id_table = fme_pr_mgmt_id_table,
365 .ops = &fme_pr_mgmt_ops,
368 .id_table = fme_global_err_id_table,
369 .ops = &fme_global_err_ops,
372 .id_table = fme_thermal_mgmt_id_table,
373 .ops = &fme_thermal_mgmt_ops,
380 static long fme_ioctl_check_extension(struct dfl_feature_platform_data *pdata,
383 /* No extension support for now */
387 static int fme_open(struct inode *inode, struct file *filp)
389 struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode);
390 struct dfl_feature_platform_data *pdata = dev_get_platdata(&fdev->dev);
396 ret = dfl_feature_dev_use_begin(pdata);
400 dev_dbg(&fdev->dev, "Device File Open\n");
401 filp->private_data = pdata;
406 static int fme_release(struct inode *inode, struct file *filp)
408 struct dfl_feature_platform_data *pdata = filp->private_data;
409 struct platform_device *pdev = pdata->dev;
411 dev_dbg(&pdev->dev, "Device File Release\n");
412 dfl_feature_dev_use_end(pdata);
417 static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
419 struct dfl_feature_platform_data *pdata = filp->private_data;
420 struct platform_device *pdev = pdata->dev;
421 struct dfl_feature *f;
424 dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
427 case DFL_FPGA_GET_API_VERSION:
428 return DFL_FPGA_API_VERSION;
429 case DFL_FPGA_CHECK_EXTENSION:
430 return fme_ioctl_check_extension(pdata, arg);
433 * Let sub-feature's ioctl function to handle the cmd.
434 * Sub-feature's ioctl returns -ENODEV when cmd is not
435 * handled in this sub feature, and returns 0 or other
436 * error code if cmd is handled.
438 dfl_fpga_dev_for_each_feature(pdata, f) {
439 if (f->ops && f->ops->ioctl) {
440 ret = f->ops->ioctl(pdev, f, cmd, arg);
450 static int fme_dev_init(struct platform_device *pdev)
452 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
455 fme = devm_kzalloc(&pdev->dev, sizeof(*fme), GFP_KERNEL);
461 mutex_lock(&pdata->lock);
462 dfl_fpga_pdata_set_private(pdata, fme);
463 mutex_unlock(&pdata->lock);
468 static void fme_dev_destroy(struct platform_device *pdev)
470 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
473 mutex_lock(&pdata->lock);
474 fme = dfl_fpga_pdata_get_private(pdata);
475 dfl_fpga_pdata_set_private(pdata, NULL);
476 mutex_unlock(&pdata->lock);
479 static const struct file_operations fme_fops = {
480 .owner = THIS_MODULE,
482 .release = fme_release,
483 .unlocked_ioctl = fme_ioctl,
486 static int fme_probe(struct platform_device *pdev)
490 ret = fme_dev_init(pdev);
494 ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs);
498 ret = dfl_fpga_dev_ops_register(pdev, &fme_fops, THIS_MODULE);
505 dfl_fpga_dev_feature_uinit(pdev);
507 fme_dev_destroy(pdev);
512 static int fme_remove(struct platform_device *pdev)
514 dfl_fpga_dev_ops_unregister(pdev);
515 dfl_fpga_dev_feature_uinit(pdev);
516 fme_dev_destroy(pdev);
521 static const struct attribute_group *fme_dev_groups[] = {
523 &fme_global_err_group,
527 static struct platform_driver fme_driver = {
529 .name = DFL_FPGA_FEATURE_DEV_FME,
530 .dev_groups = fme_dev_groups,
533 .remove = fme_remove,
536 module_platform_driver(fme_driver);
538 MODULE_DESCRIPTION("FPGA Management Engine driver");
539 MODULE_AUTHOR("Intel Corporation");
540 MODULE_LICENSE("GPL v2");
541 MODULE_ALIAS("platform:dfl-fme");