1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Texas Instruments System Control Interface (TISCI) Protocol
5 * Communication protocol with TI SCI hardware
6 * The system works in a message response protocol
7 * See: http://processors.wiki.ti.com/index.php/TISCI for details
9 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
15 /* Generic Messages */
16 #define TI_SCI_MSG_ENABLE_WDT 0x0000
17 #define TI_SCI_MSG_WAKE_RESET 0x0001
18 #define TI_SCI_MSG_VERSION 0x0002
19 #define TI_SCI_MSG_WAKE_REASON 0x0003
20 #define TI_SCI_MSG_GOODBYE 0x0004
21 #define TI_SCI_MSG_SYS_RESET 0x0005
24 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
25 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
26 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
29 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
30 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
31 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
32 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
33 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
34 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
35 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
36 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
38 /* Resource Management Requests */
39 #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
42 #define TI_SCI_MSG_SET_IRQ 0x1000
43 #define TI_SCI_MSG_FREE_IRQ 0x1001
45 /* NAVSS resource management */
46 /* Ringacc requests */
47 #define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100
48 #define TI_SCI_MSG_RM_RING_FREE 0x1101
49 #define TI_SCI_MSG_RM_RING_RECONFIG 0x1102
50 #define TI_SCI_MSG_RM_RING_RESET 0x1103
51 #define TI_SCI_MSG_RM_RING_CFG 0x1110
54 #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
55 #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
57 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
58 #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
59 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
60 #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
61 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
62 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
64 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
65 #define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206
66 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
67 #define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216
68 #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
69 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
70 #define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232
71 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233
73 /* Processor Control requests */
74 #define TI_SCI_MSG_PROC_REQUEST 0xc000
75 #define TI_SCI_MSG_PROC_RELEASE 0xc001
76 #define TI_SCI_MSG_PROC_HANDOVER 0xc005
77 #define TI_SCI_MSG_SET_CONFIG 0xc100
78 #define TI_SCI_MSG_SET_CTRL 0xc101
79 #define TI_SCI_MSG_GET_STATUS 0xc400
82 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
83 * @type: Type of messages: One of TI_SCI_MSG* values
84 * @host: Host of the message
85 * @seq: Message identifier indicating a transfer sequence
86 * @flags: Flag for the message
88 struct ti_sci_msg_hdr {
92 #define TI_SCI_MSG_FLAG(val) (1 << (val))
93 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
94 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
95 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
96 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
97 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
98 /* Additional Flags */
103 * struct ti_sci_msg_resp_version - Response for a message
104 * @hdr: Generic header
105 * @firmware_description: String describing the firmware
106 * @firmware_revision: Firmware revision
107 * @abi_major: Major version of the ABI that firmware supports
108 * @abi_minor: Minor version of the ABI that firmware supports
110 * In general, ABI version changes follow the rule that minor version increments
111 * are backward compatible. Major revision changes in ABI may not be
112 * backward compatible.
114 * Response to a generic message with message type TI_SCI_MSG_VERSION
116 struct ti_sci_msg_resp_version {
117 struct ti_sci_msg_hdr hdr;
118 char firmware_description[32];
119 u16 firmware_revision;
125 * struct ti_sci_msg_req_reboot - Reboot the SoC
126 * @hdr: Generic Header
128 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
131 struct ti_sci_msg_req_reboot {
132 struct ti_sci_msg_hdr hdr;
136 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
137 * @hdr: Generic header
138 * @id: Indicates which device to modify
139 * @reserved: Reserved space in message, must be 0 for backward compatibility
140 * @state: The desired state of the device.
142 * Certain flags can also be set to alter the device state:
143 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
144 * The meaning of this flag will vary slightly from device to device and from
145 * SoC to SoC but it generally allows the device to wake the SoC out of deep
147 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
148 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
149 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
150 * If another host already has this device set to STATE_RETENTION or STATE_ON,
151 * the message will fail. Once successful, other hosts attempting to set
152 * STATE_RETENTION or STATE_ON will fail.
154 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
157 struct ti_sci_msg_req_set_device_state {
158 /* Additional hdr->flags options */
159 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
160 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
161 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
162 struct ti_sci_msg_hdr hdr;
166 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0
167 #define MSG_DEVICE_SW_STATE_RETENTION 1
168 #define MSG_DEVICE_SW_STATE_ON 2
173 * struct ti_sci_msg_req_get_device_state - Request to get device.
174 * @hdr: Generic header
175 * @id: Device Identifier
177 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
180 struct ti_sci_msg_req_get_device_state {
181 struct ti_sci_msg_hdr hdr;
186 * struct ti_sci_msg_resp_get_device_state - Response to get device request.
187 * @hdr: Generic header
188 * @context_loss_count: Indicates how many times the device has lost context. A
189 * driver can use this monotonic counter to determine if the device has
190 * lost context since the last time this message was exchanged.
191 * @resets: Programmed state of the reset lines.
192 * @programmed_state: The state as programmed by set_device.
193 * - Uses the MSG_DEVICE_SW_* macros
194 * @current_state: The actual state of the hardware.
196 * Response to request TI_SCI_MSG_GET_DEVICE_STATE.
198 struct ti_sci_msg_resp_get_device_state {
199 struct ti_sci_msg_hdr hdr;
200 u32 context_loss_count;
203 #define MSG_DEVICE_HW_STATE_OFF 0
204 #define MSG_DEVICE_HW_STATE_ON 1
205 #define MSG_DEVICE_HW_STATE_TRANS 2
210 * struct ti_sci_msg_req_set_device_resets - Set the desired resets
211 * configuration of the device
212 * @hdr: Generic header
213 * @id: Indicates which device to modify
214 * @resets: A bit field of resets for the device. The meaning, behavior,
215 * and usage of the reset flags are device specific. 0 for a bit
216 * indicates releasing the reset represented by that bit while 1
217 * indicates keeping it held.
219 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
222 struct ti_sci_msg_req_set_device_resets {
223 struct ti_sci_msg_hdr hdr;
229 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
230 * @hdr: Generic Header, Certain flags can be set specific to the clocks:
231 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
232 * via spread spectrum clocking.
233 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
234 * frequency to be changed while it is running so long as it
235 * is within the min/max limits.
236 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
237 * is only applicable to clock inputs on the SoC pseudo-device.
238 * @dev_id: Device identifier this request is for
239 * @clk_id: Clock identifier for the device for this request.
240 * Each device has it's own set of clock inputs. This indexes
241 * which clock input to modify. Set to 255 if clock ID is
242 * greater than or equal to 255.
243 * @request_state: Request the state for the clock to be set to.
244 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
245 * it can be disabled, regardless of the state of the device
246 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
247 * automatically manage the state of this clock. If the device
248 * is enabled, then the clock is enabled. If the device is set
249 * to off or retention, then the clock is internally set as not
250 * being required by the device.(default)
251 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
252 * regardless of the state of the device.
253 * @clk_id_32: Clock identifier for the device for this request.
254 * Only to be used if the clock ID is greater than or equal to
257 * Normally, all required clocks are managed by TISCI entity, this is used
258 * only for specific control *IF* required. Auto managed state is
259 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
260 * will explicitly control.
262 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
263 * ACK or NACK message.
265 struct ti_sci_msg_req_set_clock_state {
266 /* Additional hdr->flags options */
267 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
268 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
269 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
270 struct ti_sci_msg_hdr hdr;
273 #define MSG_CLOCK_SW_STATE_UNREQ 0
274 #define MSG_CLOCK_SW_STATE_AUTO 1
275 #define MSG_CLOCK_SW_STATE_REQ 2
281 * struct ti_sci_msg_req_get_clock_state - Request for clock state
282 * @hdr: Generic Header
283 * @dev_id: Device identifier this request is for
284 * @clk_id: Clock identifier for the device for this request.
285 * Each device has it's own set of clock inputs. This indexes
286 * which clock input to get state of. Set to 255 if the clock
287 * ID is greater than or equal to 255.
288 * @clk_id_32: Clock identifier for the device for the request.
289 * Only to be used if the clock ID is greater than or equal to
292 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
295 struct ti_sci_msg_req_get_clock_state {
296 struct ti_sci_msg_hdr hdr;
303 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
304 * @hdr: Generic Header
305 * @programmed_state: Any programmed state of the clock. This is one of
306 * MSG_CLOCK_SW_STATE* values.
307 * @current_state: Current state of the clock. This is one of:
308 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
309 * MSG_CLOCK_HW_STATE_READY: Clock is ready
311 * Response to TI_SCI_MSG_GET_CLOCK_STATE.
313 struct ti_sci_msg_resp_get_clock_state {
314 struct ti_sci_msg_hdr hdr;
316 #define MSG_CLOCK_HW_STATE_NOT_READY 0
317 #define MSG_CLOCK_HW_STATE_READY 1
322 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
323 * @hdr: Generic Header
324 * @dev_id: Device identifier this request is for
325 * @clk_id: Clock identifier for the device for this request.
326 * Each device has it's own set of clock inputs. This indexes
327 * which clock input to modify. Set to 255 if clock ID is
328 * greater than or equal to 255.
329 * @parent_id: The new clock parent is selectable by an index via this
330 * parameter. Set to 255 if clock ID is greater than or
332 * @clk_id_32: Clock identifier if @clk_id field is 255.
333 * @parent_id_32: Parent identifier if @parent_id is 255.
335 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
336 * ACK / NACK message.
338 struct ti_sci_msg_req_set_clock_parent {
339 struct ti_sci_msg_hdr hdr;
348 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
349 * @hdr: Generic Header
350 * @dev_id: Device identifier this request is for
351 * @clk_id: Clock identifier for the device for this request.
352 * Each device has it's own set of clock inputs. This indexes
353 * which clock input to get the parent for. If this field
354 * contains 255, the actual clock identifier is stored in
356 * @clk_id_32: Clock identifier if the @clk_id field contains 255.
358 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
360 struct ti_sci_msg_req_get_clock_parent {
361 struct ti_sci_msg_hdr hdr;
368 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
369 * @hdr: Generic Header
370 * @parent_id: The current clock parent. If set to 255, the current parent
371 * ID can be found from the @parent_id_32 field.
372 * @parent_id_32: Current clock parent if @parent_id field is set to
375 * Response to TI_SCI_MSG_GET_CLOCK_PARENT.
377 struct ti_sci_msg_resp_get_clock_parent {
378 struct ti_sci_msg_hdr hdr;
384 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
385 * @hdr: Generic header
386 * @dev_id: Device identifier this request is for
387 * @clk_id: Clock identifier for the device for this request. Set to
388 * 255 if clock ID is greater than or equal to 255.
389 * @clk_id_32: Clock identifier if the @clk_id field contains 255.
391 * This request provides information about how many clock parent options
392 * are available for a given clock to a device. This is typically used
395 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
396 * message, or NACK in case of inability to satisfy request.
398 struct ti_sci_msg_req_get_clock_num_parents {
399 struct ti_sci_msg_hdr hdr;
406 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
407 * @hdr: Generic header
408 * @num_parents: Number of clock parents. If set to 255, the actual
409 * number of parents is stored into @num_parents_32
411 * @num_parents_32: Number of clock parents if @num_parents field is
414 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
416 struct ti_sci_msg_resp_get_clock_num_parents {
417 struct ti_sci_msg_hdr hdr;
423 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
424 * @hdr: Generic Header
425 * @dev_id: Device identifier this request is for
426 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
427 * allowable programmed frequency and does not account for clock
428 * tolerances and jitter.
429 * @target_freq_hz: The target clock frequency. A frequency will be found
430 * as close to this target frequency as possible.
431 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
432 * allowable programmed frequency and does not account for clock
433 * tolerances and jitter.
434 * @clk_id: Clock identifier for the device for this request. Set to
435 * 255 if clock identifier is greater than or equal to 255.
436 * @clk_id_32: Clock identifier if @clk_id is set to 255.
438 * NOTE: Normally clock frequency management is automatically done by TISCI
439 * entity. In case of specific requests, TISCI evaluates capability to achieve
440 * requested frequency within provided range and responds with
443 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
444 * or NACK in case of inability to satisfy request.
446 struct ti_sci_msg_req_query_clock_freq {
447 struct ti_sci_msg_hdr hdr;
457 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
458 * @hdr: Generic Header
459 * @freq_hz: Frequency that is the best match in Hz.
461 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
462 * cannot be satisfied, the message will be of type NACK.
464 struct ti_sci_msg_resp_query_clock_freq {
465 struct ti_sci_msg_hdr hdr;
470 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
471 * @hdr: Generic Header
472 * @dev_id: Device identifier this request is for
473 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
474 * allowable programmed frequency and does not account for clock
475 * tolerances and jitter.
476 * @target_freq_hz: The target clock frequency. The clock will be programmed
477 * at a rate as close to this target frequency as possible.
478 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
479 * allowable programmed frequency and does not account for clock
480 * tolerances and jitter.
481 * @clk_id: Clock identifier for the device for this request. Set to
482 * 255 if clock ID is greater than or equal to 255.
483 * @clk_id_32: Clock identifier if @clk_id field is set to 255.
485 * NOTE: Normally clock frequency management is automatically done by TISCI
486 * entity. In case of specific requests, TISCI evaluates capability to achieve
487 * requested range and responds with success/failure message.
489 * This sets the desired frequency for a clock within an allowable
490 * range. This message will fail on an enabled clock unless
491 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
492 * if other clocks have their frequency modified due to this message,
493 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
495 * Calling set frequency on a clock input to the SoC pseudo-device will
496 * inform the PMMC of that clock's frequency. Setting a frequency of
497 * zero will indicate the clock is disabled.
499 * Calling set frequency on clock outputs from the SoC pseudo-device will
500 * function similarly to setting the clock frequency on a device.
502 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
505 struct ti_sci_msg_req_set_clock_freq {
506 struct ti_sci_msg_hdr hdr;
516 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
517 * @hdr: Generic Header
518 * @dev_id: Device identifier this request is for
519 * @clk_id: Clock identifier for the device for this request. Set to
520 * 255 if clock ID is greater than or equal to 255.
521 * @clk_id_32: Clock identifier if @clk_id field is set to 255.
523 * NOTE: Normally clock frequency management is automatically done by TISCI
524 * entity. In some cases, clock frequencies are configured by host.
526 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
527 * that the clock is currently at.
529 struct ti_sci_msg_req_get_clock_freq {
530 struct ti_sci_msg_hdr hdr;
537 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
538 * @hdr: Generic Header
539 * @freq_hz: Frequency that the clock is currently on, in Hz.
541 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
543 struct ti_sci_msg_resp_get_clock_freq {
544 struct ti_sci_msg_hdr hdr;
548 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
551 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
552 * range of resources.
553 * @hdr: Generic Header
554 * @type: Unique resource assignment type
555 * @subtype: Resource assignment subtype within the resource type.
556 * @secondary_host: Host processing entity to which the resources are
557 * allocated. This is required only when the destination
558 * host id id different from ti sci interface host id,
559 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
561 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
562 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
564 struct ti_sci_msg_req_get_resource_range {
565 struct ti_sci_msg_hdr hdr;
566 #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
567 #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
574 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
575 * @hdr: Generic Header
576 * @range_start: Start index of the first resource range.
577 * @range_num: Number of resources in the first range.
578 * @range_start_sec: Start index of the second resource range.
579 * @range_num_sec: Number of resources in the second range.
581 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
583 struct ti_sci_msg_resp_get_resource_range {
584 struct ti_sci_msg_hdr hdr;
592 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route
593 * between the dev and the host.
594 * @hdr: Generic Header
595 * @valid_params: Bit fields defining the validity of interrupt source
596 * parameters. If a bit is not set, then corresponding
597 * field is not valid and will not be used for route set.
598 * Bit field definitions:
599 * 0 - Valid bit for @dst_id
600 * 1 - Valid bit for @dst_host_irq
601 * 2 - Valid bit for @ia_id
602 * 3 - Valid bit for @vint
603 * 4 - Valid bit for @global_event
604 * 5 - Valid bit for @vint_status_bit_index
605 * 31 - Valid bit for @secondary_host
606 * @src_id: IRQ source peripheral ID.
607 * @src_index: IRQ source index within the peripheral
608 * @dst_id: IRQ Destination ID. Based on the architecture it can be
609 * IRQ controller or host processor ID.
610 * @dst_host_irq: IRQ number of the destination host IRQ controller
611 * @ia_id: Device ID of the interrupt aggregator in which the
613 * @vint: Virtual interrupt number if the interrupt route
614 * is through an interrupt aggregator.
615 * @global_event: Global event that is to be mapped to interrupt
616 * aggregator virtual interrupt status bit.
617 * @vint_status_bit: Virtual interrupt status bit if the interrupt route
618 * utilizes an interrupt aggregator status bit.
619 * @secondary_host: Host ID of the IRQ destination computing entity. This is
620 * required only when destination host id is different
621 * from ti sci interface host id.
623 * Request type is TI_SCI_MSG_SET/RELEASE_IRQ.
624 * Response is generic ACK / NACK message.
626 struct ti_sci_msg_req_manage_irq {
627 struct ti_sci_msg_hdr hdr;
628 #define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0)
629 #define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1)
630 #define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2)
631 #define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3)
632 #define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4)
633 #define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5)
634 #define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31)
648 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
650 * Configures the non-real-time registers of a Navigator Subsystem ring.
651 * @hdr: Generic Header
652 * @valid_params: Bitfield defining validity of ring configuration parameters.
653 * The ring configuration fields are not valid, and will not be used for
654 * ring configuration, if their corresponding valid bit is zero.
656 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
657 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
658 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
659 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
660 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
661 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
662 * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid
663 * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL
664 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
665 * @index: ring index to be configured.
666 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
667 * RING_BA_LO register
668 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
669 * RING_BA_HI register.
670 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
672 * @mode: Specifies the mode the ring is to be configured.
673 * @size: Specifies encoded ring element size. To calculate the encoded size use
674 * the formula (log2(size_bytes) - 2), where size_bytes cannot be
676 * @order_id: Specifies the ring's bus order ID.
677 * @virtid: Ring virt ID value
678 * @asel: Ring ASEL (address select) value to be set into the ASEL field of the
679 * ring's RING_BA_HI register.
681 struct ti_sci_msg_rm_ring_cfg_req {
682 struct ti_sci_msg_hdr hdr;
697 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
699 * @hdr: Generic Header
700 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
701 * used to pair the source and destination threads.
702 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
704 * UDMAP transmit channels mapped to source threads will have their
705 * TCHAN_THRD_ID register programmed with the destination thread if the pairing
708 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
709 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
710 * the destination thread is not greater than or equal to 0x8000.
712 * UDMAP receive channels mapped to destination threads will have their
713 * RCHAN_THRD_ID register programmed with the source thread if the pairing
716 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
719 struct ti_sci_msg_psil_pair {
720 struct ti_sci_msg_hdr hdr;
727 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
729 * @hdr: Generic Header
730 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
731 * used to unpair the source and destination threads.
732 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
734 * UDMAP transmit channels mapped to source threads will have their
735 * TCHAN_THRD_ID register cleared if the unpairing is successful.
737 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
738 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
739 * the destination thread is not greater than or equal to 0x8000.
741 * UDMAP receive channels mapped to destination threads will have their
742 * RCHAN_THRD_ID register cleared if the unpairing is successful.
744 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
747 struct ti_sci_msg_psil_unpair {
748 struct ti_sci_msg_hdr hdr;
755 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration
757 * @hdr: Generic Header
758 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
760 * @flow_index: UDMAP receive flow index for non-optional configuration.
761 * @rx_ch_index: Specifies the index of the receive channel using the flow_index
762 * @rx_einfo_present: UDMAP receive flow extended packet info present.
763 * @rx_psinfo_present: UDMAP receive flow PS words present.
764 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid
765 * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY.
766 * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of
767 * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO.
768 * @rx_sop_offset: UDMAP receive flow start of packet offset.
769 * @rx_dest_qnum: UDMAP receive flow destination queue number.
770 * @rx_ps_location: UDMAP receive flow PS words location.
771 * 0 - end of packet descriptor
772 * 1 - Beginning of the data buffer
773 * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant
774 * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant
775 * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant
776 * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant
777 * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector
778 * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector
779 * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector
780 * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector
781 * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue
782 * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be
783 * configured and sent.
784 * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0.
785 * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1.
786 * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2.
787 * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3.
789 * For detailed information on the settings, see the UDMAP section of the TRM.
791 struct ti_sci_msg_udmap_rx_flow_cfg {
792 struct ti_sci_msg_hdr hdr;
797 u8 rx_psinfo_present;
798 u8 rx_error_handling;
807 u8 rx_src_tag_hi_sel;
808 u8 rx_src_tag_lo_sel;
809 u8 rx_dest_tag_hi_sel;
810 u8 rx_dest_tag_lo_sel;
811 u8 rx_size_thresh_en;
812 u16 rx_fdq0_sz0_qnum;
819 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive
820 * flow optional configuration
821 * @hdr: Generic Header
822 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
824 * @flow_index: UDMAP receive flow index for optional configuration.
825 * @rx_ch_index: Specifies the index of the receive channel using the flow_index
826 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0.
827 * @rx_size_thresh1: UDMAP receive flow packet size threshold 1.
828 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2.
829 * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size
831 * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size
833 * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size
836 * For detailed information on the settings, see the UDMAP section of the TRM.
838 struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
839 struct ti_sci_msg_hdr hdr;
846 u16 rx_fdq0_sz1_qnum;
847 u16 rx_fdq0_sz2_qnum;
848 u16 rx_fdq0_sz3_qnum;
852 * Configures a Navigator Subsystem UDMAP transmit channel
854 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
855 * transmit channel. The channel index must be assigned to the host defined
856 * in the TISCI header via the RM board configuration resource assignment
859 * @hdr: Generic Header
861 * @valid_params: Bitfield defining validity of tx channel configuration
862 * parameters. The tx channel configuration fields are not valid, and will not
863 * be used for ch configuration, if their corresponding valid bit is zero.
865 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
866 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
867 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
868 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
869 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
870 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
871 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
872 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
873 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
874 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
875 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
876 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
877 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
878 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
879 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
880 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
881 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
883 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
885 * @index: UDMAP transmit channel index.
887 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
888 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
891 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
892 * configuration to be programmed into the tx_filt_einfo field of the
893 * channel's TCHAN_TCFG register.
895 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
896 * configuration to be programmed into the tx_filt_pswords field of the
897 * channel's TCHAN_TCFG register.
899 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
900 * interpretation configuration to be programmed into the tx_atype field of
901 * the channel's TCHAN_TCFG register.
903 * @tx_chan_type: UDMAP transmit channel functional channel type and work
904 * passing mechanism configuration to be programmed into the tx_chan_type
905 * field of the channel's TCHAN_TCFG register.
907 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
908 * configuration to be programmed into the tx_supr_tdpkt field of the channel's
909 * TCHAN_TCFG register.
911 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
912 * fetch configuration to be programmed into the tx_fetch_size field of the
913 * channel's TCHAN_TCFG register. The user must make sure to set the maximum
914 * word count that can pass through the channel f