1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs_dsp.c -- Cirrus Logic DSP firmware support
5 * Based on sound/soc/codecs/wm_adsp.c
7 * Copyright 2012 Wolfson Microelectronics plc
8 * Copyright (C) 2015-2021 Cirrus Logic, Inc. and
9 * Cirrus Logic International Semiconductor Ltd.
12 #include <linux/ctype.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
20 #include <linux/firmware/cirrus/cs_dsp.h>
21 #include <linux/firmware/cirrus/wmfw.h>
23 #define cs_dsp_err(_dsp, fmt, ...) \
24 dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
25 #define cs_dsp_warn(_dsp, fmt, ...) \
26 dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
27 #define cs_dsp_info(_dsp, fmt, ...) \
28 dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
29 #define cs_dsp_dbg(_dsp, fmt, ...) \
30 dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
32 #define ADSP1_CONTROL_1 0x00
33 #define ADSP1_CONTROL_2 0x02
34 #define ADSP1_CONTROL_3 0x03
35 #define ADSP1_CONTROL_4 0x04
36 #define ADSP1_CONTROL_5 0x06
37 #define ADSP1_CONTROL_6 0x07
38 #define ADSP1_CONTROL_7 0x08
39 #define ADSP1_CONTROL_8 0x09
40 #define ADSP1_CONTROL_9 0x0A
41 #define ADSP1_CONTROL_10 0x0B
42 #define ADSP1_CONTROL_11 0x0C
43 #define ADSP1_CONTROL_12 0x0D
44 #define ADSP1_CONTROL_13 0x0F
45 #define ADSP1_CONTROL_14 0x10
46 #define ADSP1_CONTROL_15 0x11
47 #define ADSP1_CONTROL_16 0x12
48 #define ADSP1_CONTROL_17 0x13
49 #define ADSP1_CONTROL_18 0x14
50 #define ADSP1_CONTROL_19 0x16
51 #define ADSP1_CONTROL_20 0x17
52 #define ADSP1_CONTROL_21 0x18
53 #define ADSP1_CONTROL_22 0x1A
54 #define ADSP1_CONTROL_23 0x1B
55 #define ADSP1_CONTROL_24 0x1C
56 #define ADSP1_CONTROL_25 0x1E
57 #define ADSP1_CONTROL_26 0x20
58 #define ADSP1_CONTROL_27 0x21
59 #define ADSP1_CONTROL_28 0x22
60 #define ADSP1_CONTROL_29 0x23
61 #define ADSP1_CONTROL_30 0x24
62 #define ADSP1_CONTROL_31 0x26
67 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
68 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
69 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
74 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
75 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
76 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
77 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
78 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
79 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
80 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
81 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
82 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
83 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
84 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
85 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
86 #define ADSP1_START 0x0001 /* DSP1_START */
87 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
88 #define ADSP1_START_SHIFT 0 /* DSP1_START */
89 #define ADSP1_START_WIDTH 1 /* DSP1_START */
94 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
95 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
96 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
98 #define ADSP2_CONTROL 0x0
99 #define ADSP2_CLOCKING 0x1
100 #define ADSP2V2_CLOCKING 0x2
101 #define ADSP2_STATUS1 0x4
102 #define ADSP2_WDMA_CONFIG_1 0x30
103 #define ADSP2_WDMA_CONFIG_2 0x31
104 #define ADSP2V2_WDMA_CONFIG_2 0x32
105 #define ADSP2_RDMA_CONFIG_1 0x34
107 #define ADSP2_SCRATCH0 0x40
108 #define ADSP2_SCRATCH1 0x41
109 #define ADSP2_SCRATCH2 0x42
110 #define ADSP2_SCRATCH3 0x43
112 #define ADSP2V2_SCRATCH0_1 0x40
113 #define ADSP2V2_SCRATCH2_3 0x42
118 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
119 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
120 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
121 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
122 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
123 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
124 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
125 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
126 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
127 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
128 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
129 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
130 #define ADSP2_START 0x0001 /* DSP1_START */
131 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
132 #define ADSP2_START_SHIFT 0 /* DSP1_START */
133 #define ADSP2_START_WIDTH 1 /* DSP1_START */
138 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
139 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
140 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
145 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */
146 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */
147 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
149 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */
150 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */
151 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */
156 #define ADSP2_RAM_RDY 0x0001
157 #define ADSP2_RAM_RDY_MASK 0x0001
158 #define ADSP2_RAM_RDY_SHIFT 0
159 #define ADSP2_RAM_RDY_WIDTH 1
164 #define ADSP2_LOCK_CODE_0 0x5555
165 #define ADSP2_LOCK_CODE_1 0xAAAA
167 #define ADSP2_WATCHDOG 0x0A
168 #define ADSP2_BUS_ERR_ADDR 0x52
169 #define ADSP2_REGION_LOCK_STATUS 0x64
170 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66
171 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68
172 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A
173 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C
174 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E
175 #define ADSP2_LOCK_REGION_CTRL 0x7A
176 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C
178 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000
179 #define ADSP2_ADDR_ERR_MASK 0x4000
180 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
181 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002
182 #define ADSP2_CTRL_ERR_EINT 0x0001
184 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF
185 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF
186 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000
187 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16
188 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD
190 #define ADSP2_LOCK_REGION_SHIFT 16
193 * Event control messages
195 #define CS_DSP_FW_EVENT_SHUTDOWN 0x000001
200 #define HALO_AHBM_WINDOW_DEBUG_0 0x02040
201 #define HALO_AHBM_WINDOW_DEBUG_1 0x02044
206 #define HALO_SCRATCH1 0x005c0
207 #define HALO_SCRATCH2 0x005c8
208 #define HALO_SCRATCH3 0x005d0
209 #define HALO_SCRATCH4 0x005d8
210 #define HALO_CCM_CORE_CONTROL 0x41000
211 #define HALO_CORE_SOFT_RESET 0x00010
212 #define HALO_WDT_CONTROL 0x47000
217 #define HALO_MPU_XMEM_ACCESS_0 0x43000
218 #define HALO_MPU_YMEM_ACCESS_0 0x43004
219 #define HALO_MPU_WINDOW_ACCESS_0 0x43008
220 #define HALO_MPU_XREG_ACCESS_0 0x4300C
221 #define HALO_MPU_YREG_ACCESS_0 0x43014
222 #define HALO_MPU_XMEM_ACCESS_1 0x43018
223 #define HALO_MPU_YMEM_ACCESS_1 0x4301C
224 #define HALO_MPU_WINDOW_ACCESS_1 0x43020
225 #define HALO_MPU_XREG_ACCESS_1 0x43024
226 #define HALO_MPU_YREG_ACCESS_1 0x4302C
227 #define HALO_MPU_XMEM_ACCESS_2 0x43030
228 #define HALO_MPU_YMEM_ACCESS_2 0x43034
229 #define HALO_MPU_WINDOW_ACCESS_2 0x43038
230 #define HALO_MPU_XREG_ACCESS_2 0x4303C
231 #define HALO_MPU_YREG_ACCESS_2 0x43044
232 #define HALO_MPU_XMEM_ACCESS_3 0x43048
233 #define HALO_MPU_YMEM_ACCESS_3 0x4304C
234 #define HALO_MPU_WINDOW_ACCESS_3 0x43050
235 #define HALO_MPU_XREG_ACCESS_3 0x43054
236 #define HALO_MPU_YREG_ACCESS_3 0x4305C
237 #define HALO_MPU_XM_VIO_ADDR 0x43100
238 #define HALO_MPU_XM_VIO_STATUS 0x43104
239 #define HALO_MPU_YM_VIO_ADDR 0x43108
240 #define HALO_MPU_YM_VIO_STATUS 0x4310C
241 #define HALO_MPU_PM_VIO_ADDR 0x43110
242 #define HALO_MPU_PM_VIO_STATUS 0x43114
243 #define HALO_MPU_LOCK_CONFIG 0x43140
246 * HALO_AHBM_WINDOW_DEBUG_1
248 #define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00
249 #define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8
250 #define HALO_AHBM_FLAGS_ERR_MASK 0x000000ff
253 * HALO_CCM_CORE_CONTROL
255 #define HALO_CORE_RESET 0x00000200
256 #define HALO_CORE_EN 0x00000001
259 * HALO_CORE_SOFT_RESET
261 #define HALO_CORE_SOFT_RESET_MASK 0x00000001
266 #define HALO_WDT_EN_MASK 0x00000001
269 * HALO_MPU_?M_VIO_STATUS
271 #define HALO_MPU_VIO_STS_MASK 0x007e0000
272 #define HALO_MPU_VIO_STS_SHIFT 17
273 #define HALO_MPU_VIO_ERR_WR_MASK 0x00008000
274 #define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff
275 #define HALO_MPU_VIO_ERR_SRC_SHIFT 0
278 bool (*validate_version)(struct cs_dsp *dsp, unsigned int version);
279 unsigned int (*parse_sizes)(struct cs_dsp *dsp,
280 const char * const file,
282 const struct firmware *firmware);
283 int (*setup_algs)(struct cs_dsp *dsp);
284 unsigned int (*region_to_reg)(struct cs_dsp_region const *mem,
285 unsigned int offset);
287 void (*show_fw_status)(struct cs_dsp *dsp);
288 void (*stop_watchdog)(struct cs_dsp *dsp);
290 int (*enable_memory)(struct cs_dsp *dsp);
291 void (*disable_memory)(struct cs_dsp *dsp);
292 int (*lock_memory)(struct cs_dsp *dsp, unsigned int lock_regions);
294 int (*enable_core)(struct cs_dsp *dsp);
295 void (*disable_core)(struct cs_dsp *dsp);
297 int (*start_core)(struct cs_dsp *dsp);
298 void (*stop_core)(struct cs_dsp *dsp);
301 static const struct cs_dsp_ops cs_dsp_adsp1_ops;
302 static const struct cs_dsp_ops cs_dsp_adsp2_ops[];
303 static const struct cs_dsp_ops cs_dsp_halo_ops;
306 struct list_head list;
310 static struct cs_dsp_buf *cs_dsp_buf_alloc(const void *src, size_t len,
311 struct list_head *list)
313 struct cs_dsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
318 buf->buf = vmalloc(len);
323 memcpy(buf->buf, src, len);
326 list_add_tail(&buf->list, list);
331 static void cs_dsp_buf_free(struct list_head *list)
333 while (!list_empty(list)) {
334 struct cs_dsp_buf *buf = list_first_entry(list,
337 list_del(&buf->list);
344 * cs_dsp_mem_region_name() - Return a name string for a memory type
345 * @type: the memory type to match
347 * Return: A const string identifying the memory region.
349 const char *cs_dsp_mem_region_name(unsigned int type)
354 case WMFW_HALO_PM_PACKED:
360 case WMFW_HALO_XM_PACKED:
364 case WMFW_HALO_YM_PACKED:
372 EXPORT_SYMBOL_GPL(cs_dsp_mem_region_name);
374 #ifdef CONFIG_DEBUG_FS
375 static void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, const char *s)
377 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
379 kfree(dsp->wmfw_file_name);
380 dsp->wmfw_file_name = tmp;
383 static void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, const char *s)
385 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
387 kfree(dsp->bin_file_name);
388 dsp->bin_file_name = tmp;
391 static void cs_dsp_debugfs_clear(struct cs_dsp *dsp)
393 kfree(dsp->wmfw_file_name);
394 kfree(dsp->bin_file_name);
395 dsp->wmfw_file_name = NULL;
396 dsp->bin_file_name = NULL;
399 static ssize_t cs_dsp_debugfs_wmfw_read(struct file *file,
400 char __user *user_buf,
401 size_t count, loff_t *ppos)
403 struct cs_dsp *dsp = file->private_data;
406 mutex_lock(&dsp->pwr_lock);
408 if (!dsp->wmfw_file_name || !dsp->booted)
411 ret = simple_read_from_buffer(user_buf, count, ppos,
413 strlen(dsp->wmfw_file_name));
415 mutex_unlock(&dsp->pwr_lock);
419 static ssize_t cs_dsp_debugfs_bin_read(struct file *file,
420 char __user *user_buf,
421 size_t count, loff_t *ppos)
423 struct cs_dsp *dsp = file->private_data;
426 mutex_lock(&dsp->pwr_lock);
428 if (!dsp->bin_file_name || !dsp->booted)
431 ret = simple_read_from_buffer(user_buf, count, ppos,
433 strlen(dsp->bin_file_name));
435 mutex_unlock(&dsp->pwr_lock);
439 static const struct {
441 const struct file_operations fops;
442 } cs_dsp_debugfs_fops[] = {
444 .name = "wmfw_file_name",
447 .read = cs_dsp_debugfs_wmfw_read,
451 .name = "bin_file_name",
454 .read = cs_dsp_debugfs_bin_read,
460 * cs_dsp_init_debugfs() - Create and populate DSP representation in debugfs
461 * @dsp: pointer to DSP structure
462 * @debugfs_root: pointer to debugfs directory in which to create this DSP
465 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root)
467 struct dentry *root = NULL;
470 root = debugfs_create_dir(dsp->name, debugfs_root);
472 debugfs_create_bool("booted", 0444, root, &dsp->booted);
473 debugfs_create_bool("running", 0444, root, &dsp->running);
474 debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id);
475 debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version);
477 for (i = 0; i < ARRAY_SIZE(cs_dsp_debugfs_fops); ++i)
478 debugfs_create_file(cs_dsp_debugfs_fops[i].name, 0444, root,
479 dsp, &cs_dsp_debugfs_fops[i].fops);
481 dsp->debugfs_root = root;
483 EXPORT_SYMBOL_GPL(cs_dsp_init_debugfs);
486 * cs_dsp_cleanup_debugfs() - Removes DSP representation from debugfs
487 * @dsp: pointer to DSP structure
489 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp)
491 cs_dsp_debugfs_clear(dsp);
492 debugfs_remove_recursive(dsp->debugfs_root);
493 dsp->debugfs_root = NULL;
495 EXPORT_SYMBOL_GPL(cs_dsp_cleanup_debugfs);
497 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root)
500 EXPORT_SYMBOL_GPL(cs_dsp_init_debugfs);
502 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp)
505 EXPORT_SYMBOL_GPL(cs_dsp_cleanup_debugfs);
507 static inline void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp,
512 static inline void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp,
517 static inline void cs_dsp_debugfs_clear(struct cs_dsp *dsp)
522 static const struct cs_dsp_region *cs_dsp_find_region(struct cs_dsp *dsp,
527 for (i = 0; i < dsp->num_mems; i++)
528 if (dsp->mem[i].type == type)
534 static unsigned int cs_dsp_region_to_reg(struct cs_dsp_region const *mem,
539 return mem->base + (offset * 3);
544 return mem->base + (offset * 2);
546 WARN(1, "Unknown memory region type");
551 static unsigned int cs_dsp_halo_region_to_reg(struct cs_dsp_region const *mem,
557 return mem->base + (offset * 4);
558 case WMFW_HALO_XM_PACKED:
559 case WMFW_HALO_YM_PACKED:
560 return (mem->base + (offset * 3)) & ~0x3;
561 case WMFW_HALO_PM_PACKED:
562 return mem->base + (offset * 5);
564 WARN(1, "Unknown memory region type");
569 static void cs_dsp_read_fw_status(struct cs_dsp *dsp,
570 int noffs, unsigned int *offs)
575 for (i = 0; i < noffs; ++i) {
576 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]);
578 cs_dsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret);
584 static void cs_dsp_adsp2_show_fw_status(struct cs_dsp *dsp)
586 unsigned int offs[] = {
587 ADSP2_SCRATCH0, ADSP2_SCRATCH1, ADSP2_SCRATCH2, ADSP2_SCRATCH3,
590 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
592 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
593 offs[0], offs[1], offs[2], offs[3]);
596 static void cs_dsp_adsp2v2_show_fw_status(struct cs_dsp *dsp)
598 unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 };
600 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
602 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
603 offs[0] & 0xFFFF, offs[0] >> 16,
604 offs[1] & 0xFFFF, offs[1] >> 16);
607 static void cs_dsp_halo_show_fw_status(struct cs_dsp *dsp)
609 unsigned int offs[] = {
610 HALO_SCRATCH1, HALO_SCRATCH2, HALO_SCRATCH3, HALO_SCRATCH4,
613 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
615 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
616 offs[0], offs[1], offs[2], offs[3]);
619 static int cs_dsp_coeff_base_reg(struct cs_dsp_coeff_ctl *ctl, unsigned int *reg,
622 const struct cs_dsp_alg_region *alg_region = &ctl->alg_region;
623 struct cs_dsp *dsp = ctl->dsp;
624 const struct cs_dsp_region *mem;
626 mem = cs_dsp_find_region(dsp, alg_region->type);
628 cs_dsp_err(dsp, "No base for region %x\n",
633 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset + off);
639 * cs_dsp_coeff_write_acked_control() - Sends event_id to the acked control
640 * @ctl: pointer to acked coefficient control
641 * @event_id: the value to write to the given acked control
643 * Once the value has been written to the control the function shall block
644 * until the running firmware acknowledges the write or timeout is exceeded.
646 * Must be called with pwr_lock held.
648 * Return: Zero for success, a negative number on error.
650 int cs_dsp_coeff_write_acked_control(struct cs_dsp_coeff_ctl *ctl, unsigned int event_id)
652 struct cs_dsp *dsp = ctl->dsp;
653 __be32 val = cpu_to_be32(event_id);
657 lockdep_assert_held(&dsp->pwr_lock);
662 ret = cs_dsp_coeff_base_reg(ctl, ®, 0);
666 cs_dsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
667 event_id, ctl->alg_region.alg,
668 cs_dsp_mem_region_name(ctl->alg_region.type), ctl->offset);
670 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
672 cs_dsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
677 * Poll for ack, we initially poll at ~1ms intervals for firmwares
678 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
679 * to ack instantly so we do the first 1ms delay before reading the
680 * control to avoid a pointless bus transaction
682 for (i = 0; i < CS_DSP_ACKED_CTL_TIMEOUT_MS;) {
684 case 0 ... CS_DSP_ACKED_CTL_N_QUICKPOLLS - 1:
685 usleep_range(1000, 2000);
689 usleep_range(10000, 20000);
694 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
696 cs_dsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
701 cs_dsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
706 cs_dsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
707 reg, ctl->alg_region.alg,
708 cs_dsp_mem_region_name(ctl->alg_region.type),
713 EXPORT_SYMBOL_GPL(cs_dsp_coeff_write_acked_control);
715 static int cs_dsp_coeff_write_ctrl_raw(struct cs_dsp_coeff_ctl *ctl,
716 unsigned int off, const void *buf, size_t len)
718 struct cs_dsp *dsp = ctl->dsp;
723 ret = cs_dsp_coeff_base_reg(ctl, ®, off);
727 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
731 ret = regmap_raw_write(dsp->regmap, reg, scratch,
734 cs_dsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
739 cs_dsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
747 * cs_dsp_coeff_write_ctrl() - Writes the given buffer to the given coefficient control
748 * @ctl: pointer to coefficient control
749 * @off: word offset at which data should be written
750 * @buf: the buffer to write to the given control
751 * @len: the length of the buffer in bytes
753 * Must be called with pwr_lock held.
755 * Return: Zero for success, a negative number on error.
757 int cs_dsp_coeff_write_ctrl(struct cs_dsp_coeff_ctl *ctl,
758 unsigned int off, const void *buf, size_t len)
765 lockdep_assert_held(&ctl->dsp->pwr_lock);
767 if (len + off * sizeof(u32) > ctl->len)
770 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
772 else if (buf != ctl->cache)
773 memcpy(ctl->cache + off * sizeof(u32), buf, len);
776 if (ctl->enabled && ctl->dsp->running)
777 ret = cs_dsp_coeff_write_ctrl_raw(ctl, off, buf, len);
781 EXPORT_SYMBOL_GPL(cs_dsp_coeff_write_ctrl);
783 static int cs_dsp_coeff_read_ctrl_raw(struct cs_dsp_coeff_ctl *ctl,
784 unsigned int off, void *buf, size_t len)
786 struct cs_dsp *dsp = ctl->dsp;
791 ret = cs_dsp_coeff_base_reg(ctl, ®, off);
795 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
799 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
801 cs_dsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
806 cs_dsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
808 memcpy(buf, scratch, len);
815 * cs_dsp_coeff_read_ctrl() - Reads the given coefficient control into the given buffer
816 * @ctl: pointer to coefficient control
817 * @off: word offset at which data should be read
818 * @buf: the buffer to store to the given control
819 * @len: the length of the buffer in bytes
821 * Must be called with pwr_lock held.
823 * Return: Zero for success, a negative number on error.
825 int cs_dsp_coeff_read_ctrl(struct cs_dsp_coeff_ctl *ctl,
826 unsigned int off, void *buf, size_t len)
833 lockdep_assert_held(&ctl->dsp->pwr_lock);
835 if (len + off * sizeof(u32) > ctl->len)
838 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
839 if (ctl->enabled && ctl->dsp->running)
840 return cs_dsp_coeff_read_ctrl_raw(ctl, off, buf, len);
844 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
845 ret = cs_dsp_coeff_read_ctrl_raw(ctl, 0, ctl->cache, ctl->len);
847 if (buf != ctl->cache)
848 memcpy(buf, ctl->cache + off * sizeof(u32), len);
853 EXPORT_SYMBOL_GPL(cs_dsp_coeff_read_ctrl);
855 static int cs_dsp_coeff_init_control_caches(struct cs_dsp *dsp)
857 struct cs_dsp_coeff_ctl *ctl;
860 list_for_each_entry(ctl, &dsp->ctl_list, list) {
861 if (!ctl->enabled || ctl->set)
863 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
867 * For readable controls populate the cache from the DSP memory.
868 * For non-readable controls the cache was zero-filled when
869 * created so we don't need to do anything.
871 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
872 ret = cs_dsp_coeff_read_ctrl_raw(ctl, 0, ctl->cache, ctl->len);
881 static int cs_dsp_coeff_sync_controls(struct cs_dsp *dsp)
883 struct cs_dsp_coeff_ctl *ctl;
886 list_for_each_entry(ctl, &dsp->ctl_list, list) {
889 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
890 ret = cs_dsp_coeff_write_ctrl_raw(ctl, 0, ctl->cache,
900 static void cs_dsp_signal_event_controls(struct cs_dsp *dsp,
903 struct cs_dsp_coeff_ctl *ctl;
906 list_for_each_entry(ctl, &dsp->ctl_list, list) {
907 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
913 ret = cs_dsp_coeff_write_acked_control(ctl, event);
916 "Failed to send 0x%x event to alg 0x%x (%d)\n",
917 event, ctl->alg_region.alg, ret);
921 static void cs_dsp_free_ctl_blk(struct cs_dsp_coeff_ctl *ctl)
928 static int cs_dsp_create_control(struct cs_dsp *dsp,
929 const struct cs_dsp_alg_region *alg_region,
930 unsigned int offset, unsigned int len,
931 const char *subname, unsigned int subname_len,
932 unsigned int flags, unsigned int type)
934 struct cs_dsp_coeff_ctl *ctl;
937 list_for_each_entry(ctl, &dsp->ctl_list, list) {
938 if (ctl->fw_name == dsp->fw_name &&
939 ctl->alg_region.alg == alg_region->alg &&
940 ctl->alg_region.type == alg_region->type) {
941 if ((!subname && !ctl->subname) ||
942 (subname && !strncmp(ctl->subname, subname, ctl->subname_len))) {
950 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
954 ctl->fw_name = dsp->fw_name;
955 ctl->alg_region = *alg_region;
956 if (subname && dsp->fw_ver >= 2) {
957 ctl->subname_len = subname_len;
958 ctl->subname = kmemdup(subname,
959 strlen(subname) + 1, GFP_KERNEL);
971 ctl->offset = offset;
973 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
976 goto err_ctl_subname;
979 list_add(&ctl->list, &dsp->ctl_list);
981 if (dsp->client_ops->control_add) {
982 ret = dsp->client_ops->control_add(ctl);
990 list_del(&ctl->list);
1000 struct cs_dsp_coeff_parsed_alg {
1007 struct cs_dsp_coeff_parsed_coeff {
1012 unsigned int ctl_type;
1017 static int cs_dsp_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1026 length = le16_to_cpu(*((__le16 *)*pos));
1033 *str = *pos + bytes;
1035 *pos += ((length + bytes) + 3) & ~0x03;
1040 static int cs_dsp_coeff_parse_int(int bytes, const u8 **pos)
1046 val = le16_to_cpu(*((__le16 *)*pos));
1049 val = le32_to_cpu(*((__le32 *)*pos));
1060 static inline void cs_dsp_coeff_parse_alg(struct cs_dsp *dsp, const u8 **data,
1061 struct cs_dsp_coeff_parsed_alg *blk)
1063 const struct wmfw_adsp_alg_data *raw;
1065 switch (dsp->fw_ver) {
1068 raw = (const struct wmfw_adsp_alg_data *)*data;
1071 blk->id = le32_to_cpu(raw->id);
1072 blk->name = raw->name;
1073 blk->name_len = strlen(raw->name);
1074 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1077 blk->id = cs_dsp_coeff_parse_int(sizeof(raw->id), data);
1078 blk->name_len = cs_dsp_coeff_parse_string(sizeof(u8), data,
1080 cs_dsp_coeff_parse_string(sizeof(u16), data, NULL);
1081 blk->ncoeff = cs_dsp_coeff_parse_int(sizeof(raw->ncoeff), data);
1085 cs_dsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1086 cs_dsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1087 cs_dsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1090 static inline void cs_dsp_coeff_parse_coeff(struct cs_dsp *dsp, const u8 **data,
1091 struct cs_dsp_coeff_parsed_coeff *blk)
1093 const struct wmfw_adsp_coeff_data *raw;
1097 switch (dsp->fw_ver) {
1100 raw = (const struct wmfw_adsp_coeff_data *)*data;
1101 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1103 blk->offset = le16_to_cpu(raw->hdr.offset);
1104 blk->mem_type = le16_to_cpu(raw->hdr.type);
1105 blk->name = raw->name;
1106 blk->name_len = strlen(raw->name);
1107 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1108 blk->flags = le16_to_cpu(raw->flags);
1109 blk->len = le32_to_cpu(raw->len);
1113 blk->offset = cs_dsp_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1114 blk->mem_type = cs_dsp_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1115 length = cs_dsp_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1116 blk->name_len = cs_dsp_coeff_parse_string(sizeof(u8), &tmp,
1118 cs_dsp_coeff_parse_string(sizeof(u8), &tmp, NULL);
1119 cs_dsp_coeff_parse_string(sizeof(u16), &tmp, NULL);
1120 blk->ctl_type = cs_dsp_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1121 blk->flags = cs_dsp_coeff_parse_int(sizeof(raw->flags), &tmp);
1122 blk->len = cs_dsp_coeff_parse_int(sizeof(raw->len), &tmp);
1124 *data = *data + sizeof(raw->hdr) + length;
1128 cs_dsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1129 cs_dsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1130 cs_dsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1131 cs_dsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1132 cs_dsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1133 cs_dsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1136 static int cs_dsp_check_coeff_flags(struct cs_dsp *dsp,
1137 const struct cs_dsp_coeff_parsed_coeff *coeff_blk,
1138 unsigned int f_required,
1139 unsigned int f_illegal)
1141 if ((coeff_blk->flags & f_illegal) ||
1142 ((coeff_blk->flags & f_required) != f_required)) {
1143 cs_dsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1144 coeff_blk->flags, coeff_blk->ctl_type);
1151 static int cs_dsp_parse_coeff(struct cs_dsp *dsp,
1152 const struct wmfw_region *region)
1154 struct cs_dsp_alg_region alg_region = {};
1155 struct cs_dsp_coeff_parsed_alg alg_blk;
1156 struct cs_dsp_coeff_parsed_coeff coeff_blk;
1157 const u8 *data = region->data;
1160 cs_dsp_coeff_parse_alg(dsp, &data, &alg_blk);
1161 for (i = 0; i < alg_blk.ncoeff; i++) {
1162 cs_dsp_coeff_parse_coeff(dsp, &data, &coeff_blk);
1164 switch (coeff_blk.ctl_type) {
1165 case WMFW_CTL_TYPE_BYTES:
1167 case WMFW_CTL_TYPE_ACKED:
1168 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1169 continue; /* ignore */
1171 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk,
1172 WMFW_CTL_FLAG_VOLATILE |
1173 WMFW_CTL_FLAG_WRITEABLE |
1174 WMFW_CTL_FLAG_READABLE,
1179 case WMFW_CTL_TYPE_HOSTEVENT:
1180 case WMFW_CTL_TYPE_FWEVENT:
1181 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk,
1183 WMFW_CTL_FLAG_VOLATILE |
1184 WMFW_CTL_FLAG_WRITEABLE |
1185 WMFW_CTL_FLAG_READABLE,
1190 case WMFW_CTL_TYPE_HOST_BUFFER:
1191 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk,
1193 WMFW_CTL_FLAG_VOLATILE |
1194 WMFW_CTL_FLAG_READABLE,
1200 cs_dsp_err(dsp, "Unknown control type: %d\n",
1201 coeff_blk.ctl_type);
1205 alg_region.type = coeff_blk.mem_type;
1206 alg_region.alg = alg_blk.id;
1208 ret = cs_dsp_create_control(dsp, &alg_region,
1214 coeff_blk.ctl_type);
1216 cs_dsp_err(dsp, "Failed to create control: %.*s, %d\n",
1217 coeff_blk.name_len, coeff_blk.name, ret);
1223 static unsigned int cs_dsp_adsp1_parse_sizes(struct cs_dsp *dsp,
1224 const char * const file,
1226 const struct firmware *firmware)
1228 const struct wmfw_adsp1_sizes *adsp1_sizes;
1230 adsp1_sizes = (void *)&firmware->data[pos];
1232 cs_dsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file,
1233 le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm),
1234 le32_to_cpu(adsp1_sizes->zm));
1236 return pos + sizeof(*adsp1_sizes);
1239 static unsigned int cs_dsp_adsp2_parse_sizes(struct cs_dsp *dsp,
1240 const char * const file,
1242 const struct firmware *firmware)
1244 const struct wmfw_adsp2_sizes *adsp2_sizes;
1246 adsp2_sizes = (void *)&firmware->data[pos];
1248 cs_dsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file,
1249 le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym),
1250 le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm));
1252 return pos + sizeof(*adsp2_sizes);
1255 static bool cs_dsp_validate_version(struct cs_dsp *dsp, unsigned int version)
1259 cs_dsp_warn(dsp, "Deprecated file format %d\n", version);
1269 static bool cs_dsp_halo_validate_version(struct cs_dsp *dsp, unsigned int version)
1279 static int cs_dsp_load(struct cs_dsp *dsp, const struct firmware *firmware,
1282 LIST_HEAD(buf_list);
1283 struct regmap *regmap = dsp->regmap;
1284 unsigned int pos = 0;
1285 const struct wmfw_header *header;
1286 const struct wmfw_adsp1_sizes *adsp1_sizes;
1287 const struct wmfw_footer *footer;
1288 const struct wmfw_region *region;
1289 const struct cs_dsp_region *mem;
1290 const char *region_name;
1292 struct cs_dsp_buf *buf;
1295 int ret, offset, type;
1299 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1300 if (pos >= firmware->size) {
1301 cs_dsp_err(dsp, "%s: file too short, %zu bytes\n",
1302 file, firmware->size);
1306 header = (void *)&firmware->data[0];
1308 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1309 cs_dsp_err(dsp, "%s: invalid magic\n", file);
1313 if (!dsp->ops->validate_version(dsp, header->ver)) {
1314 cs_dsp_err(dsp, "%s: unknown file format %d\n",
1319 cs_dsp_info(dsp, "Firmware version: %d\n", header->ver);
1320 dsp->fw_ver = header->ver;
1322 if (header->core != dsp->type) {
1323 cs_dsp_err(dsp, "%s: invalid core %d != %d\n",
1324 file, header->core, dsp->type);
1328 pos = sizeof(*header);
1329 pos = dsp->ops->parse_sizes(dsp, file, pos, firmware);
1331 footer = (void *)&firmware->data[pos];
1332 pos += sizeof(*footer);
1334 if (le32_to_cpu(header->len) != pos) {
1335 cs_dsp_err(dsp, "%s: unexpected header length %d\n",
1336 file, le32_to_cpu(header->len));
1340 cs_dsp_dbg(dsp, "%s: timestamp %llu\n", file,
1341 le64_to_cpu(footer->timestamp));
1343 while (pos < firmware->size &&
1344 sizeof(*region) < firmware->size - pos) {
1345 region = (void *)&(firmware->data[pos]);
1346 region_name = "Unknown";
1349 offset = le32_to_cpu(region->offset) & 0xffffff;
1350 type = be32_to_cpu(region->type) & 0xff;
1353 case WMFW_NAME_TEXT:
1354 region_name = "Firmware name";
1355 text = kzalloc(le32_to_cpu(region->len) + 1,
1358 case WMFW_ALGORITHM_DATA:
1359 region_name = "Algorithm";
1360 ret = cs_dsp_parse_coeff(dsp, region);
1364 case WMFW_INFO_TEXT:
1365 region_name = "Information";
1366 text = kzalloc(le32_to_cpu(region->len) + 1,
1370 region_name = "Absolute";
1378 case WMFW_HALO_PM_PACKED:
1379 case WMFW_HALO_XM_PACKED:
1380 case WMFW_HALO_YM_PACKED:
1381 mem = cs_dsp_find_region(dsp, type);
1383 cs_dsp_err(dsp, "No region of type: %x\n", type);
1388 region_name = cs_dsp_mem_region_name(type);
1389 reg = dsp->ops->region_to_reg(mem, offset);
1393 "%s.%d: Unknown region type %x at %d(%x)\n",
1394 file, regions, type, pos, pos);
1398 cs_dsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1399 regions, le32_to_cpu(region->len), offset,
1402 if (le32_to_cpu(region->len) >
1403 firmware->size - pos - sizeof(*region)) {
1405 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1406 file, regions, region_name,
1407 le32_to_cpu(region->len), firmware->size);
1413 memcpy(text, region->data, le32_to_cpu(region->len));
1414 cs_dsp_info(dsp, "%s: %s\n", file, text);
1420 buf = cs_dsp_buf_alloc(region->data,
1421 le32_to_cpu(region->len),
1424 cs_dsp_err(dsp, "Out of memory\n");
1429 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1430 le32_to_cpu(region->len));
1433 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1435 le32_to_cpu(region->len), offset,
1441 pos += le32_to_cpu(region->len) + sizeof(*region);
1445 ret = regmap_async_complete(regmap);
1447 cs_dsp_err(dsp, "Failed to complete async write: %d\n", ret);
1451 if (pos > firmware->size)
1452 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1453 file, regions, pos - firmware->size);
1455 cs_dsp_debugfs_save_wmfwname(dsp, file);
1458 regmap_async_complete(regmap);
1459 cs_dsp_buf_free(&buf_list);
1466 * cs_dsp_get_ctl() - Finds a matching coefficient control
1467 * @dsp: pointer to DSP structure
1468 * @name: pointer to string to match with a control's subname
1469 * @type: the algorithm type to match
1470 * @alg: the algorithm id to match
1472 * Find cs_dsp_coeff_ctl with input name as its subname
1474 * Return: pointer to the control on success, NULL if not found
1476 struct cs_dsp_coeff_ctl *cs_dsp_get_ctl(struct cs_dsp *dsp, const char *name, int type,
1479 struct cs_dsp_coeff_ctl *pos, *rslt = NULL;
1481 lockdep_assert_held(&dsp->pwr_lock);
1483 list_for_each_entry(pos, &dsp->ctl_list, list) {
1486 if (strncmp(pos->subname, name, pos->subname_len) == 0 &&
1487 pos->fw_name == dsp->fw_name &&
1488 pos->alg_region.alg == alg &&
1489 pos->alg_region.type == type) {
1497 EXPORT_SYMBOL_GPL(cs_dsp_get_ctl);
1499 static void cs_dsp_ctl_fixup_base(struct cs_dsp *dsp,
1500 const struct cs_dsp_alg_region *alg_region)
1502 struct cs_dsp_coeff_ctl *ctl;
1504 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1505 if (ctl->fw_name == dsp->fw_name &&
1506 alg_region->alg == ctl->alg_region.alg &&
1507 alg_region->type == ctl->alg_region.type) {
1508 ctl->alg_region.base = alg_region->base;
1513 static void *cs_dsp_read_algs(struct cs_dsp *dsp, size_t n_algs,
1514 const struct cs_dsp_region *mem,
1515 unsigned int pos, unsigned int len)
1523 cs_dsp_err(dsp, "No algorithms\n");
1524 return ERR_PTR(-EINVAL);
1527 if (n_algs > 1024) {
1528 cs_dsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
1529 return ERR_PTR(-EINVAL);
1532 /* Read the terminator first to validate the length */
1533 reg = dsp->ops->region_to_reg(mem, pos + len);
1535 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
1537 cs_dsp_err(dsp, "Failed to read algorithm list end: %d\n",
1539 return ERR_PTR(ret);
1542 if (be32_to_cpu(val) != 0xbedead)
1543 cs_dsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
1544 reg, be32_to_cpu(val));
1546 /* Convert length from DSP words to bytes */
1549 alg = kzalloc(len, GFP_KERNEL | GFP_DMA);
1551 return ERR_PTR(-ENOMEM);
1553 reg = dsp->ops->region_to_reg(mem, pos);
1555 ret = regmap_raw_read(dsp->regmap, reg, alg, len);
1557 cs_dsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
1559 return ERR_PTR(ret);
1566 * cs_dsp_find_alg_region() - Finds a matching algorithm region
1567 * @dsp: pointer to DSP structure
1568 * @type: the algorithm type to match
1569 * @id: the algorithm id to match
1571 * Return: Pointer to matching algorithm region, or NULL if not found.
1573 struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp,
1574 int type, unsigned int id)
1576 struct cs_dsp_alg_region *alg_region;
1578 lockdep_assert_held(&dsp->pwr_lock);
1580 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1581 if (id == alg_region->alg && type == alg_region->type)
1587 EXPORT_SYMBOL_GPL(cs_dsp_find_alg_region);
1589 static struct cs_dsp_alg_region *cs_dsp_create_region(struct cs_dsp *dsp,
1590 int type, __be32 id,
1591 __be32 ver, __be32 base)
1593 struct cs_dsp_alg_region *alg_region;
1595 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1597 return ERR_PTR(-ENOMEM);
1599 alg_region->type = type;
1600 alg_region->alg = be32_to_cpu(id);
1601 alg_region->ver = be32_to_cpu(ver);
1602 alg_region->base = be32_to_cpu(base);
1604 list_add_tail(&alg_region->list, &dsp->alg_regions);
1606 if (dsp->fw_ver > 0)
1607 cs_dsp_ctl_fixup_base(dsp, alg_region);
1612 static void cs_dsp_free_alg_regions(struct cs_dsp *dsp)
1614 struct cs_dsp_alg_region *alg_region;
1616 while (!list_empty(&dsp->alg_regions)) {
1617 alg_region = list_first_entry(&dsp->alg_regions,
1618 struct cs_dsp_alg_region,
1620 list_del(&alg_region->list);
1625 static void cs_dsp_parse_wmfw_id_header(struct cs_dsp *dsp,
1626 struct wmfw_id_hdr *fw, int nalgs)
1628 dsp->fw_id = be32_to_cpu(fw->id);
1629 dsp->fw_id_version = be32_to_cpu(fw->ver);
1631 cs_dsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n",
1632 dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16,
1633 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
1637 static void cs_dsp_parse_wmfw_v3_id_header(struct cs_dsp *dsp,
1638 struct wmfw_v3_id_hdr *fw, int nalgs)
1640 dsp->fw_id = be32_to_cpu(fw->id);
1641 dsp->fw_id_version = be32_to_cpu(fw->ver);
1642 dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id);
1644 cs_dsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n",
1645 dsp->fw_id, dsp->fw_vendor_id,
1646 (dsp->fw_id_version & 0xff0000) >> 16,
1647 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
1651 static int cs_dsp_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver,
1652 int nregions, const int *type, __be32 *base)
1654 struct cs_dsp_alg_region *alg_region;
1657 for (i = 0; i < nregions; i++) {
1658 alg_region = cs_dsp_create_region(dsp, type[i], id, ver, base[i]);
1659 if (IS_ERR(alg_region))
1660 return PTR_ERR(alg_region);
1666 static int cs_dsp_adsp1_setup_algs(struct cs_dsp *dsp)
1668 struct wmfw_adsp1_id_hdr adsp1_id;
1669 struct wmfw_adsp1_alg_hdr *adsp1_alg;
1670 struct cs_dsp_alg_region *alg_region;
1671 const struct cs_dsp_region *mem;
1672 unsigned int pos, len;
1676 mem = cs_dsp_find_region(dsp, WMFW_ADSP1_DM);
1680 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1683 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n",
1688 n_algs = be32_to_cpu(adsp1_id.n_algs);
1690 cs_dsp_parse_wmfw_id_header(dsp, &adsp1_id.fw, n_algs);
1692 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM,
1693 adsp1_id.fw.id, adsp1_id.fw.ver,
1695 if (IS_ERR(alg_region))
1696 return PTR_ERR(alg_region);
1698 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM,
1699 adsp1_id.fw.id, adsp1_id.fw.ver,
1701 if (IS_ERR(alg_region))
1702 return PTR_ERR(alg_region);
1704 /* Calculate offset and length in DSP words */
1705 pos = sizeof(adsp1_id) / sizeof(u32);
1706 len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32);
1708 adsp1_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len);
1709 if (IS_ERR(adsp1_alg))
1710 return PTR_ERR(adsp1_alg);
1712 for (i = 0; i < n_algs; i++) {
1713 cs_dsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1714 i, be32_to_cpu(adsp1_alg[i].alg.id),
1715 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1716 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1717 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1718 be32_to_cpu(adsp1_alg[i].dm),
1719 be32_to_cpu(adsp1_alg[i].zm));
1721 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM,
1722 adsp1_alg[i].alg.id,
1723 adsp1_alg[i].alg.ver,
1725 if (IS_ERR(alg_region)) {
1726 ret = PTR_ERR(alg_region);
1729 if (dsp->fw_ver == 0) {
1730 if (i + 1 < n_algs) {
1731 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1732 len -= be32_to_cpu(adsp1_alg[i].dm);
1734 cs_dsp_create_control(dsp, alg_region, 0,
1736 WMFW_CTL_TYPE_BYTES);
1738 cs_dsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1739 be32_to_cpu(adsp1_alg[i].alg.id));
1743 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM,
1744 adsp1_alg[i].alg.id,
1745 adsp1_alg[i].alg.ver,
1747 if (IS_ERR(alg_region)) {
1748 ret = PTR_ERR(alg_region);
1751 if (dsp->fw_ver == 0) {
1752 if (i + 1 < n_algs) {
1753 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1754 len -= be32_to_cpu(adsp1_alg[i].zm);
1756 cs_dsp_create_control(dsp, alg_region, 0,
1758 WMFW_CTL_TYPE_BYTES);
1760 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1761 be32_to_cpu(adsp1_alg[i].alg.id));
1771 static int cs_dsp_adsp2_setup_algs(struct cs_dsp *dsp)
1773 struct wmfw_adsp2_id_hdr adsp2_id;
1774 struct wmfw_adsp2_alg_hdr *adsp2_alg;
1775 struct cs_dsp_alg_region *alg_region;
1776 const struct cs_dsp_region *mem;
1777 unsigned int pos, len;
1781 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM);
1785 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1788 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n",
1793 n_algs = be32_to_cpu(adsp2_id.n_algs);
1795 cs_dsp_parse_wmfw_id_header(dsp, &adsp2_id.fw, n_algs);
1797 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM,
1798 adsp2_id.fw.id, adsp2_id.fw.ver,
1800 if (IS_ERR(alg_region))
1801 return PTR_ERR(alg_region);
1803 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM,
1804 adsp2_id.fw.id, adsp2_id.fw.ver,
1806 if (IS_ERR(alg_region))
1807 return PTR_ERR(alg_region);
1809 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM,
1810 adsp2_id.fw.id, adsp2_id.fw.ver,
1812 if (IS_ERR(alg_region))
1813 return PTR_ERR(alg_region);
1815 /* Calculate offset and length in DSP words */
1816 pos = sizeof(adsp2_id) / sizeof(u32);
1817 len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32);
1819 adsp2_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len);
1820 if (IS_ERR(adsp2_alg))
1821 return PTR_ERR(adsp2_alg);
1823 for (i = 0; i < n_algs; i++) {
1825 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1826 i, be32_to_cpu(adsp2_alg[i].alg.id),
1827 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1828 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1829 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1830 be32_to_cpu(adsp2_alg[i].xm),
1831 be32_to_cpu(adsp2_alg[i].ym),
1832 be32_to_cpu(adsp2_alg[i].zm));
1834 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM,
1835 adsp2_alg[i].alg.id,
1836 adsp2_alg[i].alg.ver,
1838 if (IS_ERR(alg_region)) {
1839 ret = PTR_ERR(alg_region);
1842 if (dsp->fw_ver == 0) {
1843 if (i + 1 < n_algs) {
1844 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1845 len -= be32_to_cpu(adsp2_alg[i].xm);
1847 cs_dsp_create_control(dsp, alg_region, 0,
1849 WMFW_CTL_TYPE_BYTES);
1851 cs_dsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1852 be32_to_cpu(adsp2_alg[i].alg.id));
1856 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM,
1857 adsp2_alg[i].alg.id,
1858 adsp2_alg[i].alg.ver,
1860 if (IS_ERR(alg_region)) {
1861 ret = PTR_ERR(alg_region);
1864 if (dsp->fw_ver == 0) {
1865 if (i + 1 < n_algs) {
1866 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1867 len -= be32_to_cpu(adsp2_alg[i].ym);
1869 cs_dsp_create_control(dsp, alg_region, 0,
1871 WMFW_CTL_TYPE_BYTES);
1873 cs_dsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1874 be32_to_cpu(adsp2_alg[i].alg.id));
1878 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM,
1879 adsp2_alg[i].alg.id,
1880 adsp2_alg[i].alg.ver,
1882 if (IS_ERR(alg_region)) {
1883 ret = PTR_ERR(alg_region);
1886 if (dsp->fw_ver == 0) {
1887 if (i + 1 < n_algs) {
1888 len = be32_to_cpu(adsp2_alg[i + 1].zm);
1889 len -= be32_to_cpu(adsp2_alg[i].zm);
1891 cs_dsp_create_control(dsp, alg_region, 0,
1893 WMFW_CTL_TYPE_BYTES);
1895 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1896 be32_to_cpu(adsp2_alg[i].alg.id));
1906 static int cs_dsp_halo_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver,
1907 __be32 xm_base, __be32 ym_base)
1909 static const int types[] = {
1910 WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED,
1911 WMFW_ADSP2_YM, WMFW_HALO_YM_PACKED
1913 __be32 bases[] = { xm_base, xm_base, ym_base, ym_base };
1915 return cs_dsp_create_regions(dsp, id, ver, ARRAY_SIZE(types), types, bases);
1918 static int cs_dsp_halo_setup_algs(struct cs_dsp *dsp)
1920 struct wmfw_halo_id_hdr halo_id;
1921 struct wmfw_halo_alg_hdr *halo_alg;
1922 const struct cs_dsp_region *mem;
1923 unsigned int pos, len;
1927 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM);
1931 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id,
1934 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n",
1939 n_algs = be32_to_cpu(halo_id.n_algs);
1941 cs_dsp_parse_wmfw_v3_id_header(dsp, &halo_id.fw, n_algs);
1943 ret = cs_dsp_halo_create_regions(dsp, halo_id.fw.id, halo_id.fw.ver,
1944 halo_id.xm_base, halo_id.ym_base);
1948 /* Calculate offset and length in DSP words */
1949 pos = sizeof(halo_id) / sizeof(u32);
1950 len = (sizeof(*halo_alg) * n_algs) / sizeof(u32);
1952 halo_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len);
1953 if (IS_ERR(halo_alg))
1954 return PTR_ERR(halo_alg);
1956 for (i = 0; i < n_algs; i++) {
1958 "%d: ID %x v%d.%d.%d XM@%x YM@%x\n",
1959 i, be32_to_cpu(halo_alg[i].alg.id),
1960 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16,
1961 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8,
1962 be32_to_cpu(halo_alg[i].alg.ver) & 0xff,
1963 be32_to_cpu(halo_alg[i].xm_base),
1964 be32_to_cpu(halo_alg[i].ym_base));
1966 ret = cs_dsp_halo_create_regions(dsp, halo_alg[i].alg.id,
1967 halo_alg[i].alg.ver,
1968 halo_alg[i].xm_base,
1969 halo_alg[i].ym_base);
1979 static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware,
1982 LIST_HEAD(buf_list);
1983 struct regmap *regmap = dsp->regmap;
1984 struct wmfw_coeff_hdr *hdr;
1985 struct wmfw_coeff_item *blk;
1986 const struct cs_dsp_region *mem;
1987 struct cs_dsp_alg_region *alg_region;
1988 const char *region_name;
1989 int ret, pos, blocks, type, offset, reg, version;
1991 struct cs_dsp_buf *buf;
1998 if (sizeof(*hdr) >= firmware->size) {
1999 cs_dsp_err(dsp, "%s: coefficient file too short, %zu bytes\n",
2000 file, firmware->size);
2004 hdr = (void *)&firmware->data[0];
2005 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2006 cs_dsp_err(dsp, "%s: invalid coefficient magic\n", file);
2010 switch (be32_to_cpu(hdr->rev) & 0xff) {
2015 cs_dsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2016 file, be32_to_cpu(hdr->rev) & 0xff);
2021 cs_dsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2022 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2023 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2024 le32_to_cpu(hdr->ver) & 0xff);
2026 pos = le32_to_cpu(hdr->len);
2029 while (pos < firmware->size &&
2030 sizeof(*blk) < firmware->size - pos) {
2031 blk = (void *)(&firmware->data[pos]);
2033 type = le16_to_cpu(blk->type);
2034 offset = le16_to_cpu(blk->offset);
2035 version = le32_to_cpu(blk->ver) >> 8;
2037 cs_dsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2038 file, blocks, le32_to_cpu(blk->id),
2039 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2040 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2041 le32_to_cpu(blk->ver) & 0xff);
2042 cs_dsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2043 file, blocks, le32_to_cpu(blk->len), offset, type);
2046 region_name = "Unknown";
2048 case (WMFW_NAME_TEXT << 8):
2049 text = kzalloc(le32_to_cpu(blk->len) + 1, GFP_KERNEL);
2051 case (WMFW_INFO_TEXT << 8):
2052 case (WMFW_METADATA << 8):
2054 case (WMFW_ABSOLUTE << 8):
2056 * Old files may use this for global
2059 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2061 region_name = "global coefficients";
2062 mem = cs_dsp_find_region(dsp, type);
2064 cs_dsp_err(dsp, "No ZM\n");
2067 reg = dsp->ops->region_to_reg(mem, 0);
2070 region_name = "register";
2079 case WMFW_HALO_XM_PACKED:
2080 case WMFW_HALO_YM_PACKED:
2081 case WMFW_HALO_PM_PACKED:
2082 cs_dsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2083 file, blocks, le32_to_cpu(blk->len),
2084 type, le32_to_cpu(blk->id));
2086 mem = cs_dsp_find_region(dsp, type);
2088 cs_dsp_err(dsp, "No base for region %x\n", type);
2092 alg_region = cs_dsp_find_alg_region(dsp, type,
2093 le32_to_cpu(blk->id));
2095 if (version != alg_region->ver)
2097 "Algorithm coefficient version %d.%d.%d but expected %d.%d.%d\n",
2098 (version >> 16) & 0xFF,
2099 (version >> 8) & 0xFF,
2101 (alg_region->ver >> 16) & 0xFF,
2102 (alg_region->ver >> 8) & 0xFF,
2103 alg_region->ver & 0xFF);
2105 reg = alg_region->base;
2106 reg = dsp->ops->region_to_reg(mem, reg);
2109 cs_dsp_err(dsp, "No %x for algorithm %x\n",
2110 type, le32_to_cpu(blk->id));
2115 cs_dsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2116 file, blocks, type, pos);
2121 memcpy(text, blk->data, le32_to_cpu(blk->len));
2122 cs_dsp_info(dsp, "%s: %s\n", dsp->fw_name, text);
2128 if (le32_to_cpu(blk->len) >
2129 firmware->size - pos - sizeof(*blk)) {
2131 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2132 file, blocks, region_name,
2133 le32_to_cpu(blk->len),
2139 buf = cs_dsp_buf_alloc(blk->data,
2140 le32_to_cpu(blk->len),
2143 cs_dsp_err(dsp, "Out of memory\n");
2148 cs_dsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2149 file, blocks, le32_to_cpu(blk->len),
2151 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2152 le32_to_cpu(blk->len));
2155 "%s.%d: Failed to write to %x in %s: %d\n",
2156 file, blocks, reg, region_name, ret);
2160 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2164 ret = regmap_async_complete(regmap);
2166 cs_dsp_err(dsp, "Failed to complete async write: %d\n", ret);
2168 if (pos > firmware->size)
2169 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2170 file, blocks, pos - firmware->size);
2172 cs_dsp_debugfs_save_binname(dsp, file);
2175 regmap_async_complete(regmap);
2176 cs_dsp_buf_free(&buf_list);
2181 static int cs_dsp_create_name(struct cs_dsp *dsp)
2184 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d",
2193 static int cs_dsp_common_init(struct cs_dsp *dsp)
2197 ret = cs_dsp_create_name(dsp);
2201 INIT_LIST_HEAD(&dsp->alg_regions);
2202 INIT_LIST_HEAD(&dsp->ctl_list);
2204 mutex_init(&dsp->pwr_lock);
2210 * cs_dsp_adsp1_init() - Initialise a cs_dsp structure representing a ADSP1 device
2211 * @dsp: pointer to DSP structure
2213 * Return: Zero for success, a negative number on error.
2215 int cs_dsp_adsp1_init(struct cs_dsp *dsp)
2217 dsp->ops = &cs_dsp_adsp1_ops;
2219 return cs_dsp_common_init(dsp);
2221 EXPORT_SYMBOL_GPL(cs_dsp_adsp1_init);
2224 * cs_dsp_adsp1_power_up() - Load and start the named firmware
2225 * @dsp: pointer to DSP structure
2226 * @wmfw_firmware: the firmware to be sent
2227 * @wmfw_filename: file name of firmware to be sent
2228 * @coeff_firmware: the coefficient data to be sent
2229 * @coeff_filename: file name of coefficient to data be sent
2230 * @fw_name: the user-friendly firmware name
2232 * Return: Zero for success, a negative number on error.
2234 int cs_dsp_adsp1_power_up(struct cs_dsp *dsp,
2235 const struct firmware *wmfw_firmware, char *wmfw_filename,
2236 const struct firmware *coeff_firmware, char *coeff_filename,
2237 const char *fw_name)
2242 mutex_lock(&dsp->pwr_lock);
2244 dsp->fw_name = fw_name;
2246 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2247 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2250 * For simplicity set the DSP clock rate to be the
2251 * SYSCLK rate rather than making it configurable.
2253 if (dsp->sysclk_reg) {
2254 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2256 cs_dsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
2260 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
2262 ret = regmap_update_bits(dsp->regmap,
2263 dsp->base + ADSP1_CONTROL_31,
2264 ADSP1_CLK_SEL_MASK, val);
2266 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2271 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename);
2275 ret = cs_dsp_adsp1_setup_algs(dsp);
2279 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename);
2283 /* Initialize caches for enabled and unset controls */
2284 ret = cs_dsp_coeff_init_control_caches(dsp);
2288 /* Sync set controls */
2289 ret = cs_dsp_coeff_sync_controls(dsp);
2295 /* Start the core running */
2296 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2297 ADSP1_CORE_ENA | ADSP1_START,
2298 ADSP1_CORE_ENA | ADSP1_START);
2300 dsp->running = true;
2302 mutex_unlock(&dsp->pwr_lock);
2307 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2310 mutex_unlock(&dsp->pwr_lock);
2313 EXPORT_SYMBOL_GPL(cs_dsp_adsp1_power_up);
2316 * cs_dsp_adsp1_power_down() - Halts the DSP
2317 * @dsp: pointer to DSP structure
2319 void cs_dsp_adsp1_power_down(struct cs_dsp *dsp)
2321 struct cs_dsp_coeff_ctl *ctl;
2323 mutex_lock(&dsp->pwr_lock);
2325 dsp->running = false;
2326 dsp->booted = false;
2329 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2330 ADSP1_CORE_ENA | ADSP1_START, 0);
2332 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2333 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2335 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2338 list_for_each_entry(ctl, &dsp->ctl_list, list)
2341 cs_dsp_free_alg_regions(dsp);
2343 mutex_unlock(&dsp->pwr_lock);
2345 EXPORT_SYMBOL_GPL(cs_dsp_adsp1_power_down);
2347 static int cs_dsp_adsp2v2_enable_core(struct cs_dsp *dsp)
2352 /* Wait for the RAM to start, should be near instantaneous */
2353 for (count = 0; count < 10; ++count) {
2354 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2358 if (val & ADSP2_RAM_RDY)
2361 usleep_range(250, 500);
2364 if (!(val & ADSP2_RAM_RDY)) {
2365 cs_dsp_err(dsp, "Failed to start DSP RAM\n");
2369 cs_dsp_dbg(dsp, "RAM ready after %d polls\n", count);
2374 static int cs_dsp_adsp2_enable_core(struct cs_dsp *dsp)
2378 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2379 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2383 return cs_dsp_adsp2v2_enable_core(dsp);
2386 static int cs_dsp_adsp2_lock(struct cs_dsp *dsp, unsigned int lock_regions)
2388 struct regmap *regmap = dsp->regmap;
2389 unsigned int code0, code1, lock_reg;
2391 if (!(lock_regions & CS_ADSP2_REGION_ALL))
2394 lock_regions &= CS_ADSP2_REGION_ALL;
2395 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
2397 while (lock_regions) {
2399 if (lock_regions & BIT(0)) {
2400 code0 = ADSP2_LOCK_CODE_0;
2401 code1 = ADSP2_LOCK_CODE_1;
2403 if (lock_regions & BIT(1)) {
2404 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
2405 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
2407 regmap_write(regmap, lock_reg, code0);
2408 regmap_write(regmap, lock_reg, code1);
2416 static int cs_dsp_adsp2_enable_memory(struct cs_dsp *dsp)
2418 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2419 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2422 static void cs_dsp_adsp2_disable_memory(struct cs_dsp *dsp)
2424 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2428 static void cs_dsp_adsp2_disable_core(struct cs_dsp *dsp)
2430 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2431 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2432 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2434 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2438 static void cs_dsp_adsp2v2_disable_core(struct cs_dsp *dsp)
2440 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2441 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2442 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
2445 static int cs_dsp_halo_configure_mpu(struct cs_dsp *dsp, unsigned int lock_regions)
2447 struct reg_sequence config[] = {
2448 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 },
2449 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA },
2450 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF },
2451 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF },
2452 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions },
2453 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions },
2454 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions },
2455 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF },
2456 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF },
2457 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions },
2458 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions },
2459 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions },
2460 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF },
2461 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF },
2462 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions },
2463 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions },
2464 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions },
2465 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF },
2466 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF },
2467 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions },
2468 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions },
2469 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions },
2470 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 },
2473 return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config));
2477 * cs_dsp_set_dspclk() - Applies the given frequency to the given cs_dsp
2478 * @dsp: pointer to DSP structure
2479 * @freq: clock rate to set
2481 * This is only for use on ADSP2 cores.
2483 * Return: Zero for success, a negative number on error.
2485 int cs_dsp_set_dspclk(struct cs_dsp *dsp, unsigned int freq)
2489 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING,
2491 freq << ADSP2_CLK_SEL_SHIFT);
2493 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2497 EXPORT_SYMBOL_GPL(cs_dsp_set_dspclk);
2499 static void cs_dsp_stop_watchdog(struct cs_dsp *dsp)
2501 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
2502 ADSP2_WDT_ENA_MASK, 0);
2505 static void cs_dsp_halo_stop_watchdog(struct cs_dsp *dsp)
2507 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL,
2508 HALO_WDT_EN_MASK, 0);
2512 * cs_dsp_power_up() - Downloads firmware to the DSP
2513 * @dsp: pointer to DSP structure
2514 * @wmfw_firmware: the firmware to be sent
2515 * @wmfw_filename: file name of firmware to be sent
2516 * @coeff_firmware: the coefficient data to be sent
2517 * @coeff_filename: file name of coefficient to data be sent
2518 * @fw_name: the user-friendly firmware name
2520 * This function is used on ADSP2 and Halo DSP cores, it powers-up the DSP core
2521 * and downloads the firmware but does not start the firmware running. The
2522 * cs_dsp booted flag will be set once completed and if the core has a low-power
2523 * memory retention mode it will be put into this state after the firmware is
2526 * Return: Zero for success, a negative number on error.
2528 int cs_dsp_power_up(struct cs_dsp *dsp,
2529 const struct firmware *wmfw_firmware, char *wmfw_filename,
2530 const struct firmware *coeff_firmware, char *coeff_filename,
2531 const char *fw_name)
2535 mutex_lock(&dsp->pwr_lock);
2537 dsp->fw_name = fw_name;
2539 if (dsp->ops->enable_memory) {
2540 ret = dsp->ops->enable_memory(dsp);
2545 if (dsp->ops->enable_core) {
2546 ret = dsp->ops->enable_core(dsp);
2551 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename);
2555 ret = dsp->ops->setup_algs(dsp);
2559 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename);
2563 /* Initialize caches for enabled and unset controls */
2564 ret = cs_dsp_coeff_init_control_caches(dsp);
2568 if (dsp->ops->disable_core)
2569 dsp->ops->disable_core(dsp);
2573 mutex_unlock(&dsp->pwr_lock);
2577 if (dsp->ops->disable_core)
2578 dsp->ops->disable_core(dsp);
2580 if (dsp->ops->disable_memory)
2581 dsp->ops->disable_memory(dsp);
2583 mutex_unlock(&dsp->pwr_lock);
2587 EXPORT_SYMBOL_GPL(cs_dsp_power_up);
2590 * cs_dsp_power_down() - Powers-down the DSP
2591 * @dsp: pointer to DSP structure
2593 * cs_dsp_stop() must have been called before this function. The core will be
2594 * fully powered down and so the memory will not be retained.
2596 void cs_dsp_power_down(struct cs_dsp *dsp)
2598 struct cs_dsp_coeff_ctl *ctl;
2600 mutex_lock(&dsp->pwr_lock);
2602 cs_dsp_debugfs_clear(dsp);
2605 dsp->fw_id_version = 0;
2607 dsp->booted = false;
2609 if (dsp->ops->disable_memory)
2610 dsp->ops->disable_memory(dsp);
2612 list_for_each_entry(ctl, &dsp->ctl_list, list)
2615 cs_dsp_free_alg_regions(dsp);
2617 mutex_unlock(&dsp->pwr_lock);
2619 cs_dsp_dbg(dsp, "Shutdown complete\n");
2621 EXPORT_SYMBOL_GPL(cs_dsp_power_down);
2623 static int cs_dsp_adsp2_start_core(struct cs_dsp *dsp)
2625 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2626 ADSP2_CORE_ENA | ADSP2_START,
2627 ADSP2_CORE_ENA | ADSP2_START);
2630 static void cs_dsp_adsp2_stop_core(struct cs_dsp *dsp)
2632 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2633 ADSP2_CORE_ENA | ADSP2_START, 0);
2637 * cs_dsp_run() - Starts the firmware running
2638 * @dsp: pointer to DSP structure
2640 * cs_dsp_power_up() must have previously been called successfully.
2642 * Return: Zero for success, a negative number on error.
2644 int cs_dsp_run(struct cs_dsp *dsp)
2648 mutex_lock(&dsp->pwr_lock);
2655 if (dsp->ops->enable_core) {
2656 ret = dsp->ops->enable_core(dsp);
2661 if (dsp->client_ops->pre_run) {
2662 ret = dsp->client_ops->pre_run(dsp);
2667 /* Sync set controls */
2668 ret = cs_dsp_coeff_sync_controls(dsp);
2672 if (dsp->ops->lock_memory) {
2673 ret = dsp->ops->lock_memory(dsp, dsp->lock_regions);
2675 cs_dsp_err(dsp, "Error configuring MPU: %d\n", ret);
2680 if (dsp->ops->start_core) {
2681 ret = dsp->ops->start_core(dsp);
2686 dsp->running = true;
2688 if (dsp->client_ops->post_run) {
2689 ret = dsp->client_ops->post_run(dsp);
2694 mutex_unlock(&dsp->pwr_lock);
2699 if (dsp->ops->stop_core)
2700 dsp->ops->stop_core(dsp);
2701 if (dsp->ops->disable_core)
2702 dsp->ops->disable_core(dsp);
2703 mutex_unlock(&dsp->pwr_lock);
2707 EXPORT_SYMBOL_GPL(cs_dsp_run);
2710 * cs_dsp_stop() - Stops the firmware
2711 * @dsp: pointer to DSP structure
2713 * Memory will not be disabled so firmware will remain loaded.
2715 void cs_dsp_stop(struct cs_dsp *dsp)
2717 /* Tell the firmware to cleanup */
2718 cs_dsp_signal_event_controls(dsp, CS_DSP_FW_EVENT_SHUTDOWN);
2720 if (dsp->ops->stop_watchdog)
2721 dsp->ops->stop_watchdog(dsp);
2723 /* Log firmware state, it can be useful for analysis */
2724 if (dsp->ops->show_fw_status)
2725 dsp->ops->show_fw_status(dsp);
2727 mutex_lock(&dsp->pwr_lock);
2729 dsp->running = false;
2731 if (dsp->ops->stop_core)
2732 dsp->ops->stop_core(dsp);
2733 if (dsp->ops->disable_core)
2734 dsp->ops->disable_core(dsp);
2736 if (dsp->client_ops->post_stop)
2737 dsp->client_ops->post_stop(dsp);
2739 mutex_unlock(&dsp->pwr_lock);
2741 cs_dsp_dbg(dsp, "Execution stopped\n");
2743 EXPORT_SYMBOL_GPL(cs_dsp_stop);
2745 static int cs_dsp_halo_start_core(struct cs_dsp *dsp)
2749 ret = regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
2750 HALO_CORE_RESET | HALO_CORE_EN,
2751 HALO_CORE_RESET | HALO_CORE_EN);
2755 return regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
2756 HALO_CORE_RESET, 0);
2759 static void cs_dsp_halo_stop_core(struct cs_dsp *dsp)
2761 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
2764 /* reset halo core with CORE_SOFT_RESET */
2765 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET,
2766 HALO_CORE_SOFT_RESET_MASK, 1);
2770 * cs_dsp_adsp2_init() - Initialise a cs_dsp structure representing a ADSP2 core
2771 * @dsp: pointer to DSP structure
2773 * Return: Zero for success, a negative number on error.
2775 int cs_dsp_adsp2_init(struct cs_dsp *dsp)
2782 * Disable the DSP memory by default when in reset for a small
2785 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2789 "Failed to clear memory retention: %d\n", ret);
2793 dsp->ops = &cs_dsp_adsp2_ops[0];
2796 dsp->ops = &cs_dsp_adsp2_ops[1];
2799 dsp->ops = &cs_dsp_adsp2_ops[2];
2803 return cs_dsp_common_init(dsp);
2805 EXPORT_SYMBOL_GPL(cs_dsp_adsp2_init);
2808 * cs_dsp_halo_init() - Initialise a cs_dsp structure representing a HALO Core DSP
2809 * @dsp: pointer to DSP structure
2811 * Return: Zero for success, a negative number on error.
2813 int cs_dsp_halo_init(struct cs_dsp *dsp)
2815 dsp->ops = &cs_dsp_halo_ops;
2817 return cs_dsp_common_init(dsp);
2819 EXPORT_SYMBOL_GPL(cs_dsp_halo_init);
2822 * cs_dsp_remove() - Clean a cs_dsp before deletion
2823 * @dsp: pointer to DSP structure
2825 void cs_dsp_remove(struct cs_dsp *dsp)
2827 struct cs_dsp_coeff_ctl *ctl;
2829 while (!list_empty(&dsp->ctl_list)) {
2830 ctl = list_first_entry(&dsp->ctl_list, struct cs_dsp_coeff_ctl, list);
2832 if (dsp->client_ops->control_remove)
2833 dsp->client_ops->control_remove(ctl);
2835 list_del(&ctl->list);
2836 cs_dsp_free_ctl_blk(ctl);
2839 EXPORT_SYMBOL_GPL(cs_dsp_remove);
2842 * cs_dsp_read_raw_data_block() - Reads a block of data from DSP memory
2843 * @dsp: pointer to DSP structure
2844 * @mem_type: the type of DSP memory containing the data to be read
2845 * @mem_addr: the address of the data within the memory region
2846 * @num_words: the length of the data to read
2847 * @data: a buffer to store the fetched data
2849 * If this is used to read unpacked 24-bit memory, each 24-bit DSP word will
2850 * occupy 32-bits in data (MSbyte will be 0). This padding can be removed using
2851 * cs_dsp_remove_padding()
2853 * Return: Zero for success, a negative number on error.
2855 int cs_dsp_read_raw_data_block(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr,
2856 unsigned int num_words, __be32 *data)
2858 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type);
2862 lockdep_assert_held(&dsp->pwr_lock);
2867 reg = dsp->ops->region_to_reg(mem, mem_addr);
2869 ret = regmap_raw_read(dsp->regmap, reg, data,
2870 sizeof(*data) * num_words);
2876 EXPORT_SYMBOL_GPL(cs_dsp_read_raw_data_block);
2879 * cs_dsp_read_data_word() - Reads a word from DSP memory
2880 * @dsp: pointer to DSP structure
2881 * @mem_type: the type of DSP memory containing the data to be read
2882 * @mem_addr: the address of the data within the memory region
2883 * @data: a buffer to store the fetched data
2885 * Return: Zero for success, a negative number on error.
2887 int cs_dsp_read_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 *data)
2892 ret = cs_dsp_read_raw_data_block(dsp, mem_type, mem_addr, 1, &raw);
2896 *data = be32_to_cpu(raw) & 0x00ffffffu;
2900 EXPORT_SYMBOL_GPL(cs_dsp_read_data_word);
2903 * cs_dsp_write_data_word() - Writes a word to DSP memory
2904 * @dsp: pointer to DSP structure
2905 * @mem_type: the type of DSP memory containing the data to be written
2906 * @mem_addr: the address of the data within the memory region
2907 * @data: the data to be written
2909 * Return: Zero for success, a negative number on error.
2911 int cs_dsp_write_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 data)
2913 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type);
2914 __be32 val = cpu_to_be32(data & 0x00ffffffu);
2917 lockdep_assert_held(&dsp->pwr_lock);
2922 reg = dsp->ops->region_to_reg(mem, mem_addr);
2924 return regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
2926 EXPORT_SYMBOL_GPL(cs_dsp_write_data_word);
2929 * cs_dsp_remove_padding() - Convert unpacked words to packed bytes
2930 * @buf: buffer containing DSP words read from DSP memory
2931 * @nwords: number of words to convert
2933 * DSP words from the register map have pad bytes and the data bytes
2934 * are in swapped order. This swaps to the native endian order and
2935 * strips the pad bytes.
2937 void cs_dsp_remove_padding(u32 *buf, int nwords)
2939 const __be32 *pack_in = (__be32 *)buf;
2940 u8 *pack_out = (u8 *)buf;
2943 for (i = 0; i < nwords; i++) {
2944 u32 word = be32_to_cpu(*pack_in++);
2945 *pack_out++ = (u8)word;
2946 *pack_out++ = (u8)(word >> 8);
2947 *pack_out++ = (u8)(word >> 16);
2950 EXPORT_SYMBOL_GPL(cs_dsp_remove_padding);
2953 * cs_dsp_adsp2_bus_error() - Handle a DSP bus error interrupt
2954 * @dsp: pointer to DSP structure
2956 * The firmware and DSP state will be logged for future analysis.
2958 void cs_dsp_adsp2_bus_error(struct cs_dsp *dsp)
2961 struct regmap *regmap = dsp->regmap;
2964 mutex_lock(&dsp->pwr_lock);
2966 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
2969 "Failed to read Region Lock Ctrl register: %d\n", ret);
2973 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
2974 cs_dsp_err(dsp, "watchdog timeout error\n");
2975 dsp->ops->stop_watchdog(dsp);
2976 if (dsp->client_ops->watchdog_expired)
2977 dsp->client_ops->watchdog_expired(dsp);
2980 if (val & (ADSP2_ADDR_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
2981 if (val & ADSP2_ADDR_ERR_MASK)
2982 cs_dsp_err(dsp, "bus error: address error\n");
2984 cs_dsp_err(dsp, "bus error: region lock error\n");
2986 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
2989 "Failed to read Bus Err Addr register: %d\n",
2994 cs_dsp_err(dsp, "bus error address = 0x%x\n",
2995 val & ADSP2_BUS_ERR_ADDR_MASK);
2997 ret = regmap_read(regmap,
2998 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
3002 "Failed to read Pmem Xmem Err Addr register: %d\n",
3007 cs_dsp_err(dsp, "xmem error address = 0x%x\n",
3008 val & ADSP2_XMEM_ERR_ADDR_MASK);
3009 cs_dsp_err(dsp, "pmem error address = 0x%x\n",
3010 (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
3011 ADSP2_PMEM_ERR_ADDR_SHIFT);
3014 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
3015 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
3018 mutex_unlock(&dsp->pwr_lock);
3020 EXPORT_SYMBOL_GPL(cs_dsp_adsp2_bus_error);
3023 * cs_dsp_halo_bus_error() - Handle a DSP bus error interrupt
3024 * @dsp: pointer to DSP structure
3026 * The firmware and DSP state will be logged for future analysis.
3028 void cs_dsp_halo_bus_error(struct cs_dsp *dsp)
3030 struct regmap *regmap = dsp->regmap;
3031 unsigned int fault[6];
3032 struct reg_sequence clear[] = {
3033 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 },
3034 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 },
3035 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 },
3039 mutex_lock(&dsp->pwr_lock);
3041 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1,
3044 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret);
3048 cs_dsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n",
3049 *fault & HALO_AHBM_FLAGS_ERR_MASK,
3050 (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >>
3051 HALO_AHBM_CORE_ERR_ADDR_SHIFT);
3053 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0,
3056 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret);
3060 cs_dsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault);
3062 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR,
3063 fault, ARRAY_SIZE(fault));
3065 cs_dsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret);
3069 cs_dsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]);
3070 cs_dsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]);
3071 cs_dsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]);
3073 ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear));
3075 cs_dsp_warn(dsp, "Failed to clear MPU status: %d\n", ret);
3078 mutex_unlock(&dsp->pwr_lock);
3080 EXPORT_SYMBOL_GPL(cs_dsp_halo_bus_error);
3083 * cs_dsp_halo_wdt_expire() - Handle DSP watchdog expiry
3084 * @dsp: pointer to DSP structure
3086 * This is logged for future analysis.
3088 void cs_dsp_halo_wdt_expire(struct cs_dsp *dsp)
3090 mutex_lock(&dsp->pwr_lock);
3092 cs_dsp_warn(dsp, "WDT Expiry Fault\n");
3094 dsp->ops->stop_watchdog(dsp);
3095 if (dsp->client_ops->watchdog_expired)
3096 dsp->client_ops->watchdog_expired(dsp);
3098 mutex_unlock(&dsp->pwr_lock);
3100 EXPORT_SYMBOL_GPL(cs_dsp_halo_wdt_expire);
3102 static const struct cs_dsp_ops cs_dsp_adsp1_ops = {
3103 .validate_version = cs_dsp_validate_version,
3104 .parse_sizes = cs_dsp_adsp1_parse_sizes,
3105 .region_to_reg = cs_dsp_region_to_reg,
3108 static const struct cs_dsp_ops cs_dsp_adsp2_ops[] = {
3110 .parse_sizes = cs_dsp_adsp2_parse_sizes,
3111 .validate_version = cs_dsp_validate_version,
3112 .setup_algs = cs_dsp_adsp2_setup_algs,
3113 .region_to_reg = cs_dsp_region_to_reg,
3115 .show_fw_status = cs_dsp_adsp2_show_fw_status,
3117 .enable_memory = cs_dsp_adsp2_enable_memory,
3118 .disable_memory = cs_dsp_adsp2_disable_memory,
3120 .enable_core = cs_dsp_adsp2_enable_core,
3121 .disable_core = cs_dsp_adsp2_disable_core,
3123 .start_core = cs_dsp_adsp2_start_core,
3124 .stop_core = cs_dsp_adsp2_stop_core,
3128 .parse_sizes = cs_dsp_adsp2_parse_sizes,
3129 .validate_version = cs_dsp_validate_version,
3130 .setup_algs = cs_dsp_adsp2_setup_algs,
3131 .region_to_reg = cs_dsp_region_to_reg,
3133 .show_fw_status = cs_dsp_adsp2v2_show_fw_status,
3135 .enable_memory = cs_dsp_adsp2_enable_memory,
3136 .disable_memory = cs_dsp_adsp2_disable_memory,
3137 .lock_memory = cs_dsp_adsp2_lock,
3139 .enable_core = cs_dsp_adsp2v2_enable_core,
3140 .disable_core = cs_dsp_adsp2v2_disable_core,
3142 .start_core = cs_dsp_adsp2_start_core,
3143 .stop_core = cs_dsp_adsp2_stop_core,
3146 .parse_sizes = cs_dsp_adsp2_parse_sizes,
3147 .validate_version = cs_dsp_validate_version,
3148 .setup_algs = cs_dsp_adsp2_setup_algs,
3149 .region_to_reg = cs_dsp_region_to_reg,
3151 .show_fw_status = cs_dsp_adsp2v2_show_fw_status,
3152 .stop_watchdog = cs_dsp_stop_watchdog,
3154 .enable_memory = cs_dsp_adsp2_enable_memory,
3155 .disable_memory = cs_dsp_adsp2_disable_memory,
3156 .lock_memory = cs_dsp_adsp2_lock,
3158 .enable_core = cs_dsp_adsp2v2_enable_core,
3159 .disable_core = cs_dsp_adsp2v2_disable_core,
3161 .start_core = cs_dsp_adsp2_start_core,
3162 .stop_core = cs_dsp_adsp2_stop_core,
3166 static const struct cs_dsp_ops cs_dsp_halo_ops = {
3167 .parse_sizes = cs_dsp_adsp2_parse_sizes,
3168 .validate_version = cs_dsp_halo_validate_version,
3169 .setup_algs = cs_dsp_halo_setup_algs,
3170 .region_to_reg = cs_dsp_halo_region_to_reg,
3172 .show_fw_status = cs_dsp_halo_show_fw_status,
3173 .stop_watchdog = cs_dsp_halo_stop_watchdog,
3175 .lock_memory = cs_dsp_halo_configure_mpu,
3177 .start_core = cs_dsp_halo_start_core,
3178 .stop_core = cs_dsp_halo_stop_core,
3181 MODULE_DESCRIPTION("Cirrus Logic DSP Support");
3182 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
3183 MODULE_LICENSE("GPL v2");