2 * Cavium ThunderX memory controller kernel module
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/edac.h>
15 #include <linux/interrupt.h>
16 #include <linux/string.h>
17 #include <linux/stop_machine.h>
18 #include <linux/delay.h>
19 #include <linux/sizes.h>
20 #include <linux/atomic.h>
21 #include <linux/bitfield.h>
22 #include <linux/circ_buf.h>
26 #include "edac_module.h"
28 #define phys_to_pfn(phys) (PFN_DOWN(phys))
30 #define THUNDERX_NODE GENMASK(45, 44)
38 #define MAX_SYNDROME_REGS 4
40 struct error_syndrome {
41 u64 reg[MAX_SYNDROME_REGS];
50 static void decode_register(char *str, size_t size,
51 const struct error_descr *descr,
56 while (descr->type && descr->mask && descr->descr) {
57 if (reg & descr->mask) {
58 ret = snprintf(str, size, "\n\t%s, %s",
59 descr->type == ERR_CORRECTED ?
60 "Corrected" : "Uncorrected",
69 static unsigned long get_bits(unsigned long data, int pos, int width)
71 return (data >> pos) & ((1 << width) - 1);
74 #define L2C_CTL 0x87E080800000
75 #define L2C_CTL_DISIDXALIAS BIT(0)
77 #define PCI_DEVICE_ID_THUNDER_LMC 0xa022
80 #define LMC_FADR_FDIMM(x) ((x >> 37) & 0x1)
81 #define LMC_FADR_FBUNK(x) ((x >> 36) & 0x1)
82 #define LMC_FADR_FBANK(x) ((x >> 32) & 0xf)
83 #define LMC_FADR_FROW(x) ((x >> 14) & 0xffff)
84 #define LMC_FADR_FCOL(x) ((x >> 0) & 0x1fff)
86 #define LMC_NXM_FADR 0x28
87 #define LMC_ECC_SYND 0x38
89 #define LMC_ECC_PARITY_TEST 0x108
91 #define LMC_INT_W1S 0x150
93 #define LMC_INT_ENA_W1C 0x158
94 #define LMC_INT_ENA_W1S 0x160
96 #define LMC_CONFIG 0x188
98 #define LMC_CONFIG_BG2 BIT(62)
99 #define LMC_CONFIG_RANK_ENA BIT(42)
100 #define LMC_CONFIG_PBANK_LSB(x) (((x) >> 5) & 0xF)
101 #define LMC_CONFIG_ROW_LSB(x) (((x) >> 2) & 0x7)
103 #define LMC_CONTROL 0x190
104 #define LMC_CONTROL_XOR_BANK BIT(16)
106 #define LMC_INT 0x1F0
108 #define LMC_INT_DDR_ERR BIT(11)
109 #define LMC_INT_DED_ERR (0xFUL << 5)
110 #define LMC_INT_SEC_ERR (0xFUL << 1)
111 #define LMC_INT_NXM_WR_MASK BIT(0)
113 #define LMC_DDR_PLL_CTL 0x258
114 #define LMC_DDR_PLL_CTL_DDR4 BIT(29)
116 #define LMC_FADR_SCRAMBLED 0x330
118 #define LMC_INT_UE (LMC_INT_DDR_ERR | LMC_INT_DED_ERR | \
121 #define LMC_INT_CE (LMC_INT_SEC_ERR)
123 static const struct error_descr lmc_errors[] = {
125 .type = ERR_CORRECTED,
126 .mask = LMC_INT_SEC_ERR,
127 .descr = "Single-bit ECC error",
130 .type = ERR_UNCORRECTED,
131 .mask = LMC_INT_DDR_ERR,
132 .descr = "DDR chip error",
135 .type = ERR_UNCORRECTED,
136 .mask = LMC_INT_DED_ERR,
137 .descr = "Double-bit ECC error",
140 .type = ERR_UNCORRECTED,
141 .mask = LMC_INT_NXM_WR_MASK,
142 .descr = "Non-existent memory write",
147 #define LMC_INT_EN_DDR_ERROR_ALERT_ENA BIT(5)
148 #define LMC_INT_EN_DLCRAM_DED_ERR BIT(4)
149 #define LMC_INT_EN_DLCRAM_SEC_ERR BIT(3)
150 #define LMC_INT_INTR_DED_ENA BIT(2)
151 #define LMC_INT_INTR_SEC_ENA BIT(1)
152 #define LMC_INT_INTR_NXM_WR_ENA BIT(0)
154 #define LMC_INT_ENA_ALL GENMASK(5, 0)
156 #define LMC_DDR_PLL_CTL 0x258
157 #define LMC_DDR_PLL_CTL_DDR4 BIT(29)
159 #define LMC_CONTROL 0x190
160 #define LMC_CONTROL_RDIMM BIT(0)
162 #define LMC_SCRAM_FADR 0x330
164 #define LMC_CHAR_MASK0 0x228
165 #define LMC_CHAR_MASK2 0x238
167 #define RING_ENTRIES 8
169 struct debugfs_entry {
172 const struct file_operations fops;
183 struct thunderx_lmc {
185 struct pci_dev *pdev;
186 struct msix_entry msix_ent;
209 struct lmc_err_ctx err_ctx[RING_ENTRIES];
210 unsigned long ring_head;
211 unsigned long ring_tail;
214 #define ring_pos(pos, size) ((pos) & (size - 1))
216 #define DEBUGFS_STRUCT(_name, _mode, _write, _read) \
217 static struct debugfs_entry debugfs_##_name = { \
218 .name = __stringify(_name), \
219 .mode = VERIFY_OCTAL_PERMISSIONS(_mode), \
221 .open = simple_open, \
224 .llseek = generic_file_llseek, \
228 #define DEBUGFS_FIELD_ATTR(_type, _field) \
229 static ssize_t thunderx_##_type##_##_field##_read(struct file *file, \
231 size_t count, loff_t *ppos) \
233 struct thunderx_##_type *pdata = file->private_data; \
236 snprintf(buf, count, "0x%016llx", pdata->_field); \
237 return simple_read_from_buffer(data, count, ppos, \
241 static ssize_t thunderx_##_type##_##_field##_write(struct file *file, \
242 const char __user *data, \
243 size_t count, loff_t *ppos) \
245 struct thunderx_##_type *pdata = file->private_data; \
248 res = kstrtoull_from_user(data, count, 0, &pdata->_field); \
250 return res ? res : count; \
253 DEBUGFS_STRUCT(_field, 0600, \
254 thunderx_##_type##_##_field##_write, \
255 thunderx_##_type##_##_field##_read) \
257 #define DEBUGFS_REG_ATTR(_type, _name, _reg) \
258 static ssize_t thunderx_##_type##_##_name##_read(struct file *file, \
260 size_t count, loff_t *ppos) \
262 struct thunderx_##_type *pdata = file->private_data; \
265 sprintf(buf, "0x%016llx", readq(pdata->regs + _reg)); \
266 return simple_read_from_buffer(data, count, ppos, \
270 static ssize_t thunderx_##_type##_##_name##_write(struct file *file, \
271 const char __user *data, \
272 size_t count, loff_t *ppos) \
274 struct thunderx_##_type *pdata = file->private_data; \
278 res = kstrtoull_from_user(data, count, 0, &val); \
281 writeq(val, pdata->regs + _reg); \
288 DEBUGFS_STRUCT(_name, 0600, \
289 thunderx_##_type##_##_name##_write, \
290 thunderx_##_type##_##_name##_read)
292 #define LMC_DEBUGFS_ENT(_field) DEBUGFS_FIELD_ATTR(lmc, _field)
295 * To get an ECC error injected, the following steps are needed:
296 * - Setup the ECC injection by writing the appropriate parameters:
297 * echo <bit mask value> > /sys/kernel/debug/<device number>/ecc_mask0
298 * echo <bit mask value> > /sys/kernel/debug/<device number>/ecc_mask2
299 * echo 0x802 > /sys/kernel/debug/<device number>/ecc_parity_test
300 * - Do the actual injection:
301 * echo 1 > /sys/kernel/debug/<device number>/inject_ecc
303 static ssize_t thunderx_lmc_inject_int_write(struct file *file,
304 const char __user *data,
305 size_t count, loff_t *ppos)
307 struct thunderx_lmc *lmc = file->private_data;
311 res = kstrtoull_from_user(data, count, 0, &val);
314 /* Trigger the interrupt */
315 writeq(val, lmc->regs + LMC_INT_W1S);
322 static ssize_t thunderx_lmc_int_read(struct file *file,
324 size_t count, loff_t *ppos)
326 struct thunderx_lmc *lmc = file->private_data;
328 u64 lmc_int = readq(lmc->regs + LMC_INT);
330 snprintf(buf, sizeof(buf), "0x%016llx", lmc_int);
331 return simple_read_from_buffer(data, count, ppos, buf, sizeof(buf));
334 #define TEST_PATTERN 0xa5
336 static int inject_ecc_fn(void *arg)
338 struct thunderx_lmc *lmc = arg;
339 uintptr_t addr, phys;
340 unsigned int cline_size = cache_line_size();
341 const unsigned int lines = PAGE_SIZE / cline_size;
342 unsigned int i, cl_idx;
344 addr = (uintptr_t)page_address(lmc->mem);
345 phys = (uintptr_t)page_to_phys(lmc->mem);
347 cl_idx = (phys & 0x7f) >> 4;
348 lmc->parity_test &= ~(7ULL << 8);
349 lmc->parity_test |= (cl_idx << 8);
351 writeq(lmc->mask0, lmc->regs + LMC_CHAR_MASK0);
352 writeq(lmc->mask2, lmc->regs + LMC_CHAR_MASK2);
353 writeq(lmc->parity_test, lmc->regs + LMC_ECC_PARITY_TEST);
355 readq(lmc->regs + LMC_CHAR_MASK0);
356 readq(lmc->regs + LMC_CHAR_MASK2);
357 readq(lmc->regs + LMC_ECC_PARITY_TEST);
359 for (i = 0; i < lines; i++) {
360 memset((void *)addr, TEST_PATTERN, cline_size);
364 * Flush L1 cachelines to the PoC (L2).
365 * This will cause cacheline eviction to the L2.
367 asm volatile("dc civac, %0\n"
369 : : "r"(addr + i * cline_size));
372 for (i = 0; i < lines; i++) {
374 * Flush L2 cachelines to the DRAM.
375 * This will cause cacheline eviction to the DRAM
376 * and ECC corruption according to the masks set.
378 __asm__ volatile("sys #0,c11,C1,#2, %0\n"
379 : : "r"(phys + i * cline_size));
382 for (i = 0; i < lines; i++) {
384 * Invalidate L2 cachelines.
385 * The subsequent load will cause cacheline fetch
386 * from the DRAM and an error interrupt
388 __asm__ volatile("sys #0,c11,C1,#1, %0"
389 : : "r"(phys + i * cline_size));
392 for (i = 0; i < lines; i++) {
394 * Invalidate L1 cachelines.
395 * The subsequent load will cause cacheline fetch
396 * from the L2 and/or DRAM
398 asm volatile("dc ivac, %0\n"
400 : : "r"(addr + i * cline_size));
406 static ssize_t thunderx_lmc_inject_ecc_write(struct file *file,
407 const char __user *data,
408 size_t count, loff_t *ppos)
410 struct thunderx_lmc *lmc = file->private_data;
412 unsigned int cline_size = cache_line_size();
416 unsigned int offs, timeout = 100000;
418 atomic_set(&lmc->ecc_int, 0);
420 lmc->mem = alloc_pages_node(lmc->node, GFP_KERNEL, 0);
425 addr = page_address(lmc->mem);
427 while (!atomic_read(&lmc->ecc_int) && timeout--) {
428 stop_machine(inject_ecc_fn, lmc, NULL);
430 for (offs = 0; offs < PAGE_SIZE; offs += sizeof(tmp)) {
432 * Do a load from the previously rigged location
433 * This should generate an error interrupt.
435 memcpy(tmp, addr + offs, cline_size);
436 asm volatile("dsb ld\n");
440 __free_pages(lmc->mem, 0);
445 LMC_DEBUGFS_ENT(mask0);
446 LMC_DEBUGFS_ENT(mask2);
447 LMC_DEBUGFS_ENT(parity_test);
449 DEBUGFS_STRUCT(inject_int, 0200, thunderx_lmc_inject_int_write, NULL);
450 DEBUGFS_STRUCT(inject_ecc, 0200, thunderx_lmc_inject_ecc_write, NULL);
451 DEBUGFS_STRUCT(int_w1c, 0400, NULL, thunderx_lmc_int_read);
453 struct debugfs_entry *lmc_dfs_ents[] = {
456 &debugfs_parity_test,
462 static int thunderx_create_debugfs_nodes(struct dentry *parent,
463 struct debugfs_entry *attrs[],
470 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
476 for (i = 0; i < num; i++) {
477 ent = edac_debugfs_create_file(attrs[i]->name, attrs[i]->mode,
478 parent, data, &attrs[i]->fops);
487 static phys_addr_t thunderx_faddr_to_phys(u64 faddr, struct thunderx_lmc *lmc)
489 phys_addr_t addr = 0;
492 addr |= lmc->node << 40;
493 addr |= LMC_FADR_FDIMM(faddr) << lmc->dimm_lsb;
494 addr |= LMC_FADR_FBUNK(faddr) << lmc->rank_lsb;
495 addr |= LMC_FADR_FROW(faddr) << lmc->row_lsb;
496 addr |= (LMC_FADR_FCOL(faddr) >> 4) << lmc->col_hi_lsb;
498 bank = LMC_FADR_FBANK(faddr) << lmc->bank_lsb;
501 bank ^= get_bits(addr, 12 + lmc->xbits, lmc->bank_width);
503 addr |= bank << lmc->bank_lsb;
505 xbits = PCI_FUNC(lmc->pdev->devfn);
508 xbits ^= get_bits(addr, 20, lmc->xbits) ^
509 get_bits(addr, 12, lmc->xbits);
516 static unsigned int thunderx_get_num_lmcs(unsigned int node)
518 unsigned int number = 0;
519 struct pci_dev *pdev = NULL;
522 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
523 PCI_DEVICE_ID_THUNDER_LMC,
527 if (pdev->dev.numa_node == node)
538 #define LMC_MESSAGE_SIZE 120
539 #define LMC_OTHER_SIZE (50 * ARRAY_SIZE(lmc_errors))
541 static irqreturn_t thunderx_lmc_err_isr(int irq, void *dev_id)
543 struct mem_ctl_info *mci = dev_id;
544 struct thunderx_lmc *lmc = mci->pvt_info;
546 unsigned long head = ring_pos(lmc->ring_head, ARRAY_SIZE(lmc->err_ctx));
547 struct lmc_err_ctx *ctx = &lmc->err_ctx[head];
549 writeq(0, lmc->regs + LMC_CHAR_MASK0);
550 writeq(0, lmc->regs + LMC_CHAR_MASK2);
551 writeq(0x2, lmc->regs + LMC_ECC_PARITY_TEST);
553 ctx->reg_int = readq(lmc->regs + LMC_INT);
554 ctx->reg_fadr = readq(lmc->regs + LMC_FADR);
555 ctx->reg_nxm_fadr = readq(lmc->regs + LMC_NXM_FADR);
556 ctx->reg_scram_fadr = readq(lmc->regs + LMC_SCRAM_FADR);
557 ctx->reg_ecc_synd = readq(lmc->regs + LMC_ECC_SYND);
561 atomic_set(&lmc->ecc_int, 1);
563 /* Clear the interrupt */
564 writeq(ctx->reg_int, lmc->regs + LMC_INT);
566 return IRQ_WAKE_THREAD;
569 static irqreturn_t thunderx_lmc_threaded_isr(int irq, void *dev_id)
571 struct mem_ctl_info *mci = dev_id;
572 struct thunderx_lmc *lmc = mci->pvt_info;
573 phys_addr_t phys_addr;
576 struct lmc_err_ctx *ctx;
578 irqreturn_t ret = IRQ_NONE;
583 msg = kmalloc(LMC_MESSAGE_SIZE, GFP_KERNEL);
584 other = kmalloc(LMC_OTHER_SIZE, GFP_KERNEL);
589 while (CIRC_CNT(lmc->ring_head, lmc->ring_tail,
590 ARRAY_SIZE(lmc->err_ctx))) {
591 tail = ring_pos(lmc->ring_tail, ARRAY_SIZE(lmc->err_ctx));
593 ctx = &lmc->err_ctx[tail];
595 dev_dbg(&lmc->pdev->dev, "LMC_INT: %016llx\n",
597 dev_dbg(&lmc->pdev->dev, "LMC_FADR: %016llx\n",
599 dev_dbg(&lmc->pdev->dev, "LMC_NXM_FADR: %016llx\n",
601 dev_dbg(&lmc->pdev->dev, "LMC_SCRAM_FADR: %016llx\n",
602 ctx->reg_scram_fadr);
603 dev_dbg(&lmc->pdev->dev, "LMC_ECC_SYND: %016llx\n",
606 snprintf(msg, LMC_MESSAGE_SIZE,
607 "DIMM %lld rank %lld bank %lld row %lld col %lld",
608 LMC_FADR_FDIMM(ctx->reg_scram_fadr),
609 LMC_FADR_FBUNK(ctx->reg_scram_fadr),
610 LMC_FADR_FBANK(ctx->reg_scram_fadr),
611 LMC_FADR_FROW(ctx->reg_scram_fadr),
612 LMC_FADR_FCOL(ctx->reg_scram_fadr));
614 decode_register(other, LMC_OTHER_SIZE, lmc_errors,
617 phys_addr = thunderx_faddr_to_phys(ctx->reg_fadr, lmc);
619 if (ctx->reg_int & LMC_INT_UE)
620 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
621 phys_to_pfn(phys_addr),
622 offset_in_page(phys_addr),
623 0, -1, -1, -1, msg, other);
624 else if (ctx->reg_int & LMC_INT_CE)
625 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
626 phys_to_pfn(phys_addr),
627 offset_in_page(phys_addr),
628 0, -1, -1, -1, msg, other);
643 static int thunderx_lmc_suspend(struct pci_dev *pdev, pm_message_t state)
645 pci_save_state(pdev);
646 pci_disable_device(pdev);
648 pci_set_power_state(pdev, pci_choose_state(pdev, state));
653 static int thunderx_lmc_resume(struct pci_dev *pdev)
655 pci_set_power_state(pdev, PCI_D0);
656 pci_enable_wake(pdev, PCI_D0, 0);
657 pci_restore_state(pdev);
663 static const struct pci_device_id thunderx_lmc_pci_tbl[] = {
664 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_LMC) },
668 static inline int pci_dev_to_mc_idx(struct pci_dev *pdev)
670 int node = dev_to_node(&pdev->dev);
671 int ret = PCI_FUNC(pdev->devfn);
673 ret += max(node, 0) << 3;
678 static int thunderx_lmc_probe(struct pci_dev *pdev,
679 const struct pci_device_id *id)
681 struct thunderx_lmc *lmc;
682 struct edac_mc_layer layer;
683 struct mem_ctl_info *mci;
684 u64 lmc_control, lmc_ddr_pll_ctl, lmc_config;
689 layer.type = EDAC_MC_LAYER_SLOT;
691 layer.is_virt_csrow = false;
693 ret = pcim_enable_device(pdev);
695 dev_err(&pdev->dev, "Cannot enable PCI device: %d\n", ret);
699 ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_lmc");
701 dev_err(&pdev->dev, "Cannot map PCI resources: %d\n", ret);
705 mci = edac_mc_alloc(pci_dev_to_mc_idx(pdev), 1, &layer,
706 sizeof(struct thunderx_lmc));
710 mci->pdev = &pdev->dev;
713 pci_set_drvdata(pdev, mci);
715 lmc->regs = pcim_iomap_table(pdev)[0];
717 lmc_control = readq(lmc->regs + LMC_CONTROL);
718 lmc_ddr_pll_ctl = readq(lmc->regs + LMC_DDR_PLL_CTL);
719 lmc_config = readq(lmc->regs + LMC_CONFIG);
721 if (lmc_control & LMC_CONTROL_RDIMM) {
722 mci->mtype_cap = FIELD_GET(LMC_DDR_PLL_CTL_DDR4,
724 MEM_RDDR4 : MEM_RDDR3;
726 mci->mtype_cap = FIELD_GET(LMC_DDR_PLL_CTL_DDR4,
731 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
732 mci->edac_cap = EDAC_FLAG_SECDED;
734 mci->mod_name = "thunderx-lmc";
735 mci->ctl_name = "thunderx-lmc";
736 mci->dev_name = dev_name(&pdev->dev);
737 mci->scrub_mode = SCRUB_NONE;
740 lmc->msix_ent.entry = 0;
745 ret = pci_enable_msix_exact(pdev, &lmc->msix_ent, 1);
747 dev_err(&pdev->dev, "Cannot enable interrupt: %d\n", ret);
751 ret = devm_request_threaded_irq(&pdev->dev, lmc->msix_ent.vector,
752 thunderx_lmc_err_isr,
753 thunderx_lmc_threaded_isr, 0,
754 "[EDAC] ThunderX LMC", mci);
756 dev_err(&pdev->dev, "Cannot set ISR: %d\n", ret);
760 lmc->node = FIELD_GET(THUNDERX_NODE, pci_resource_start(pdev, 0));
762 lmc->xbits = thunderx_get_num_lmcs(lmc->node) >> 1;
763 lmc->bank_width = (FIELD_GET(LMC_DDR_PLL_CTL_DDR4, lmc_ddr_pll_ctl) &&
764 FIELD_GET(LMC_CONFIG_BG2, lmc_config)) ? 4 : 3;
766 lmc->pbank_lsb = (lmc_config >> 5) & 0xf;
767 lmc->dimm_lsb = 28 + lmc->pbank_lsb + lmc->xbits;
768 lmc->rank_lsb = lmc->dimm_lsb;
769 lmc->rank_lsb -= FIELD_GET(LMC_CONFIG_RANK_ENA, lmc_config) ? 1 : 0;
770 lmc->bank_lsb = 7 + lmc->xbits;
771 lmc->row_lsb = 14 + LMC_CONFIG_ROW_LSB(lmc_config) + lmc->xbits;
773 lmc->col_hi_lsb = lmc->bank_lsb + lmc->bank_width;
775 lmc->xor_bank = lmc_control & LMC_CONTROL_XOR_BANK;
777 l2c_ioaddr = ioremap(L2C_CTL | FIELD_PREP(THUNDERX_NODE, lmc->node), PAGE_SIZE);
779 dev_err(&pdev->dev, "Cannot map L2C_CTL\n");
784 lmc->l2c_alias = !(readq(l2c_ioaddr) & L2C_CTL_DISIDXALIAS);
788 ret = edac_mc_add_mc(mci);
790 dev_err(&pdev->dev, "Cannot add the MC: %d\n", ret);
794 lmc_int = readq(lmc->regs + LMC_INT);
795 writeq(lmc_int, lmc->regs + LMC_INT);
797 writeq(LMC_INT_ENA_ALL, lmc->regs + LMC_INT_ENA_W1S);
799 if (IS_ENABLED(CONFIG_EDAC_DEBUG)) {
800 ret = thunderx_create_debugfs_nodes(mci->debugfs,
803 ARRAY_SIZE(lmc_dfs_ents));
805 if (ret != ARRAY_SIZE(lmc_dfs_ents)) {
806 dev_warn(&pdev->dev, "Error creating debugfs entries: %d%s\n",
807 ret, ret >= 0 ? " created" : "");
814 pci_set_drvdata(pdev, NULL);
820 static void thunderx_lmc_remove(struct pci_dev *pdev)
822 struct mem_ctl_info *mci = pci_get_drvdata(pdev);
823 struct thunderx_lmc *lmc = mci->pvt_info;
825 writeq(LMC_INT_ENA_ALL, lmc->regs + LMC_INT_ENA_W1C);
827 edac_mc_del_mc(&pdev->dev);
831 MODULE_DEVICE_TABLE(pci, thunderx_lmc_pci_tbl);
833 static struct pci_driver thunderx_lmc_driver = {
834 .name = "thunderx_lmc_edac",
835 .probe = thunderx_lmc_probe,
836 .remove = thunderx_lmc_remove,
838 .suspend = thunderx_lmc_suspend,
839 .resume = thunderx_lmc_resume,
841 .id_table = thunderx_lmc_pci_tbl,
844 /*---------------------- OCX driver ---------------------------------*/
846 #define PCI_DEVICE_ID_THUNDER_OCX 0xa013
848 #define OCX_LINK_INTS 3
849 #define OCX_INTS (OCX_LINK_INTS + 1)
850 #define OCX_RX_LANES 24
851 #define OCX_RX_LANE_STATS 15
853 #define OCX_COM_INT 0x100
854 #define OCX_COM_INT_W1S 0x108
855 #define OCX_COM_INT_ENA_W1S 0x110
856 #define OCX_COM_INT_ENA_W1C 0x118
858 #define OCX_COM_IO_BADID BIT(54)
859 #define OCX_COM_MEM_BADID BIT(53)
860 #define OCX_COM_COPR_BADID BIT(52)
861 #define OCX_COM_WIN_REQ_BADID BIT(51)
862 #define OCX_COM_WIN_REQ_TOUT BIT(50)
863 #define OCX_COM_RX_LANE GENMASK(23, 0)
865 #define OCX_COM_INT_CE (OCX_COM_IO_BADID | \
866 OCX_COM_MEM_BADID | \
867 OCX_COM_COPR_BADID | \
868 OCX_COM_WIN_REQ_BADID | \
869 OCX_COM_WIN_REQ_TOUT)
871 static const struct error_descr ocx_com_errors[] = {
873 .type = ERR_CORRECTED,
874 .mask = OCX_COM_IO_BADID,
875 .descr = "Invalid IO transaction node ID",
878 .type = ERR_CORRECTED,
879 .mask = OCX_COM_MEM_BADID,
880 .descr = "Invalid memory transaction node ID",
883 .type = ERR_CORRECTED,
884 .mask = OCX_COM_COPR_BADID,
885 .descr = "Invalid coprocessor transaction node ID",
888 .type = ERR_CORRECTED,
889 .mask = OCX_COM_WIN_REQ_BADID,
890 .descr = "Invalid SLI transaction node ID",
893 .type = ERR_CORRECTED,
894 .mask = OCX_COM_WIN_REQ_TOUT,
895 .descr = "Window/core request timeout",
900 #define OCX_COM_LINKX_INT(x) (0x120 + (x) * 8)
901 #define OCX_COM_LINKX_INT_W1S(x) (0x140 + (x) * 8)
902 #define OCX_COM_LINKX_INT_ENA_W1S(x) (0x160 + (x) * 8)
903 #define OCX_COM_LINKX_INT_ENA_W1C(x) (0x180 + (x) * 8)
905 #define OCX_COM_LINK_BAD_WORD BIT(13)
906 #define OCX_COM_LINK_ALIGN_FAIL BIT(12)
907 #define OCX_COM_LINK_ALIGN_DONE BIT(11)
908 #define OCX_COM_LINK_UP BIT(10)
909 #define OCX_COM_LINK_STOP BIT(9)
910 #define OCX_COM_LINK_BLK_ERR BIT(8)
911 #define OCX_COM_LINK_REINIT BIT(7)
912 #define OCX_COM_LINK_LNK_DATA BIT(6)
913 #define OCX_COM_LINK_RXFIFO_DBE BIT(5)
914 #define OCX_COM_LINK_RXFIFO_SBE BIT(4)
915 #define OCX_COM_LINK_TXFIFO_DBE BIT(3)
916 #define OCX_COM_LINK_TXFIFO_SBE BIT(2)
917 #define OCX_COM_LINK_REPLAY_DBE BIT(1)
918 #define OCX_COM_LINK_REPLAY_SBE BIT(0)
920 static const struct error_descr ocx_com_link_errors[] = {
922 .type = ERR_CORRECTED,
923 .mask = OCX_COM_LINK_REPLAY_SBE,
924 .descr = "Replay buffer single-bit error",
927 .type = ERR_CORRECTED,
928 .mask = OCX_COM_LINK_TXFIFO_SBE,
929 .descr = "TX FIFO single-bit error",
932 .type = ERR_CORRECTED,
933 .mask = OCX_COM_LINK_RXFIFO_SBE,
934 .descr = "RX FIFO single-bit error",
937 .type = ERR_CORRECTED,
938 .mask = OCX_COM_LINK_BLK_ERR,
939 .descr = "Block code error",
942 .type = ERR_CORRECTED,
943 .mask = OCX_COM_LINK_ALIGN_FAIL,
944 .descr = "Link alignment failure",
947 .type = ERR_CORRECTED,
948 .mask = OCX_COM_LINK_BAD_WORD,
949 .descr = "Bad code word",
952 .type = ERR_UNCORRECTED,
953 .mask = OCX_COM_LINK_REPLAY_DBE,
954 .descr = "Replay buffer double-bit error",
957 .type = ERR_UNCORRECTED,
958 .mask = OCX_COM_LINK_TXFIFO_DBE,
959 .descr = "TX FIFO double-bit error",
962 .type = ERR_UNCORRECTED,
963 .mask = OCX_COM_LINK_RXFIFO_DBE,
964 .descr = "RX FIFO double-bit error",
967 .type = ERR_UNCORRECTED,
968 .mask = OCX_COM_LINK_STOP,
969 .descr = "Link stopped",
974 #define OCX_COM_LINK_INT_UE (OCX_COM_LINK_REPLAY_DBE | \
975 OCX_COM_LINK_TXFIFO_DBE | \
976 OCX_COM_LINK_RXFIFO_DBE | \
979 #define OCX_COM_LINK_INT_CE (OCX_COM_LINK_REPLAY_SBE | \
980 OCX_COM_LINK_TXFIFO_SBE | \
981 OCX_COM_LINK_RXFIFO_SBE | \
982 OCX_COM_LINK_BLK_ERR | \
983 OCX_COM_LINK_ALIGN_FAIL | \
984 OCX_COM_LINK_BAD_WORD)
986 #define OCX_LNE_INT(x) (0x8018 + (x) * 0x100)
987 #define OCX_LNE_INT_EN(x) (0x8020 + (x) * 0x100)
988 #define OCX_LNE_BAD_CNT(x) (0x8028 + (x) * 0x100)
989 #define OCX_LNE_CFG(x) (0x8000 + (x) * 0x100)
990 #define OCX_LNE_STAT(x, y) (0x8040 + (x) * 0x100 + (y) * 8)
992 #define OCX_LNE_CFG_RX_BDRY_LOCK_DIS BIT(8)
993 #define OCX_LNE_CFG_RX_STAT_WRAP_DIS BIT(2)
994 #define OCX_LNE_CFG_RX_STAT_RDCLR BIT(1)
995 #define OCX_LNE_CFG_RX_STAT_ENA BIT(0)
998 #define OCX_LANE_BAD_64B67B BIT(8)
999 #define OCX_LANE_DSKEW_FIFO_OVFL BIT(5)
1000 #define OCX_LANE_SCRM_SYNC_LOSS BIT(4)
1001 #define OCX_LANE_UKWN_CNTL_WORD BIT(3)
1002 #define OCX_LANE_CRC32_ERR BIT(2)
1003 #define OCX_LANE_BDRY_SYNC_LOSS BIT(1)
1004 #define OCX_LANE_SERDES_LOCK_LOSS BIT(0)
1006 #define OCX_COM_LANE_INT_UE (0)
1007 #define OCX_COM_LANE_INT_CE (OCX_LANE_SERDES_LOCK_LOSS | \
1008 OCX_LANE_BDRY_SYNC_LOSS | \
1009 OCX_LANE_CRC32_ERR | \
1010 OCX_LANE_UKWN_CNTL_WORD | \
1011 OCX_LANE_SCRM_SYNC_LOSS | \
1012 OCX_LANE_DSKEW_FIFO_OVFL | \
1013 OCX_LANE_BAD_64B67B)
1015 static const struct error_descr ocx_lane_errors[] = {
1017 .type = ERR_CORRECTED,
1018 .mask = OCX_LANE_SERDES_LOCK_LOSS,
1019 .descr = "RX SerDes lock lost",
1022 .type = ERR_CORRECTED,
1023 .mask = OCX_LANE_BDRY_SYNC_LOSS,
1024 .descr = "RX word boundary lost",
1027 .type = ERR_CORRECTED,
1028 .mask = OCX_LANE_CRC32_ERR,
1029 .descr = "CRC32 error",
1032 .type = ERR_CORRECTED,
1033 .mask = OCX_LANE_UKWN_CNTL_WORD,
1034 .descr = "Unknown control word",
1037 .type = ERR_CORRECTED,
1038 .mask = OCX_LANE_SCRM_SYNC_LOSS,
1039 .descr = "Scrambler synchronization lost",
1042 .type = ERR_CORRECTED,
1043 .mask = OCX_LANE_DSKEW_FIFO_OVFL,
1044 .descr = "RX deskew FIFO overflow",
1047 .type = ERR_CORRECTED,
1048 .mask = OCX_LANE_BAD_64B67B,
1049 .descr = "Bad 64B/67B codeword",
1054 #define OCX_LNE_INT_ENA_ALL (GENMASK(9, 8) | GENMASK(6, 0))
1055 #define OCX_COM_INT_ENA_ALL (GENMASK(54, 50) | GENMASK(23, 0))
1056 #define OCX_COM_LINKX_INT_ENA_ALL (GENMASK(13, 12) | \
1057 GENMASK(9, 7) | GENMASK(5, 0))
1059 #define OCX_TLKX_ECC_CTL(x) (0x10018 + (x) * 0x2000)
1060 #define OCX_RLKX_ECC_CTL(x) (0x18018 + (x) * 0x2000)
1062 struct ocx_com_err_ctx {
1064 u64 reg_lane_int[OCX_RX_LANES];
1065 u64 reg_lane_stat11[OCX_RX_LANES];
1068 struct ocx_link_err_ctx {
1069 u64 reg_com_link_int;
1073 struct thunderx_ocx {
1076 struct pci_dev *pdev;
1077 struct edac_device_ctl_info *edac_dev;
1079 struct dentry *debugfs;
1080 struct msix_entry msix_ent[OCX_INTS];
1082 struct ocx_com_err_ctx com_err_ctx[RING_ENTRIES];
1083 struct ocx_link_err_ctx link_err_ctx[RING_ENTRIES];
1085 unsigned long com_ring_head;
1086 unsigned long com_ring_tail;
1088 unsigned long link_ring_head;
1089 unsigned long link_ring_tail;
1092 #define OCX_MESSAGE_SIZE SZ_1K
1093 #define OCX_OTHER_SIZE (50 * ARRAY_SIZE(ocx_com_link_errors))
1095 /* This handler is threaded */
1096 static irqreturn_t thunderx_ocx_com_isr(int irq, void *irq_id)
1098 struct msix_entry *msix = irq_id;
1099 struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,
1100 msix_ent[msix->entry]);
1103 unsigned long head = ring_pos(ocx->com_ring_head,
1104 ARRAY_SIZE(ocx->com_err_ctx));
1105 struct ocx_com_err_ctx *ctx = &ocx->com_err_ctx[head];
1107 ctx->reg_com_int = readq(ocx->regs + OCX_COM_INT);
1109 for (lane = 0; lane < OCX_RX_LANES; lane++) {
1110 ctx->reg_lane_int[lane] =
1111 readq(ocx->regs + OCX_LNE_INT(lane));
1112 ctx->reg_lane_stat11[lane] =
1113 readq(ocx->regs + OCX_LNE_STAT(lane, 11));
1115 writeq(ctx->reg_lane_int[lane], ocx->regs + OCX_LNE_INT(lane));
1118 writeq(ctx->reg_com_int, ocx->regs + OCX_COM_INT);
1120 ocx->com_ring_head++;
1122 return IRQ_WAKE_THREAD;
1125 static irqreturn_t thunderx_ocx_com_threaded_isr(int irq, void *irq_id)
1127 struct msix_entry *msix = irq_id;
1128 struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,
1129 msix_ent[msix->entry]);
1131 irqreturn_t ret = IRQ_NONE;
1134 struct ocx_com_err_ctx *ctx;
1139 msg = kmalloc(OCX_MESSAGE_SIZE, GFP_KERNEL);
1140 other = kmalloc(OCX_OTHER_SIZE, GFP_KERNEL);
1145 while (CIRC_CNT(ocx->com_ring_head, ocx->com_ring_tail,
1146 ARRAY_SIZE(ocx->com_err_ctx))) {
1147 tail = ring_pos(ocx->com_ring_tail,
1148 ARRAY_SIZE(ocx->com_err_ctx));
1149 ctx = &ocx->com_err_ctx[tail];
1151 snprintf(msg, OCX_MESSAGE_SIZE, "%s: OCX_COM_INT: %016llx",
1152 ocx->edac_dev->ctl_name, ctx->reg_com_int);
1154 decode_register(other, OCX_OTHER_SIZE,
1155 ocx_com_errors, ctx->reg_com_int);
1157 strncat(msg, other, OCX_MESSAGE_SIZE);
1159 for (lane = 0; lane < OCX_RX_LANES; lane++)
1160 if (ctx->reg_com_int & BIT(lane)) {
1161 snprintf(other, OCX_OTHER_SIZE,
1162 "\n\tOCX_LNE_INT[%02d]: %016llx OCX_LNE_STAT11[%02d]: %016llx",
1163 lane, ctx->reg_lane_int[lane],
1164 lane, ctx->reg_lane_stat11[lane]);
1166 strncat(msg, other, OCX_MESSAGE_SIZE);
1168 decode_register(other, OCX_OTHER_SIZE,
1170 ctx->reg_lane_int[lane]);
1171 strncat(msg, other, OCX_MESSAGE_SIZE);
1174 if (ctx->reg_com_int & OCX_COM_INT_CE)
1175 edac_device_handle_ce(ocx->edac_dev, 0, 0, msg);
1177 ocx->com_ring_tail++;
1189 static irqreturn_t thunderx_ocx_lnk_isr(int irq, void *irq_id)
1191 struct msix_entry *msix = irq_id;
1192 struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,
1193 msix_ent[msix->entry]);
1194 unsigned long head = ring_pos(ocx->link_ring_head,
1195 ARRAY_SIZE(ocx->link_err_ctx));
1196 struct ocx_link_err_ctx *ctx = &ocx->link_err_ctx[head];
1198 ctx->link = msix->entry;
1199 ctx->reg_com_link_int = readq(ocx->regs + OCX_COM_LINKX_INT(ctx->link));
1201 writeq(ctx->reg_com_link_int, ocx->regs + OCX_COM_LINKX_INT(ctx->link));
1203 ocx->link_ring_head++;
1205 return IRQ_WAKE_THREAD;
1208 static irqreturn_t thunderx_ocx_lnk_threaded_isr(int irq, void *irq_id)
1210 struct msix_entry *msix = irq_id;
1211 struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,
1212 msix_ent[msix->entry]);
1213 irqreturn_t ret = IRQ_NONE;
1215 struct ocx_link_err_ctx *ctx;
1220 msg = kmalloc(OCX_MESSAGE_SIZE, GFP_KERNEL);
1221 other = kmalloc(OCX_OTHER_SIZE, GFP_KERNEL);
1226 while (CIRC_CNT(ocx->link_ring_head, ocx->link_ring_tail,
1227 ARRAY_SIZE(ocx->link_err_ctx))) {
1228 tail = ring_pos(ocx->link_ring_head,
1229 ARRAY_SIZE(ocx->link_err_ctx));
1231 ctx = &ocx->link_err_ctx[tail];
1233 snprintf(msg, OCX_MESSAGE_SIZE,
1234 "%s: OCX_COM_LINK_INT[%d]: %016llx",
1235 ocx->edac_dev->ctl_name,
1236 ctx->link, ctx->reg_com_link_int);
1238 decode_register(other, OCX_OTHER_SIZE,
1239 ocx_com_link_errors, ctx->reg_com_link_int);
1241 strncat(msg, other, OCX_MESSAGE_SIZE);
1243 if (ctx->reg_com_link_int & OCX_COM_LINK_INT_UE)
1244 edac_device_handle_ue(ocx->edac_dev, 0, 0, msg);
1245 else if (ctx->reg_com_link_int & OCX_COM_LINK_INT_CE)
1246 edac_device_handle_ce(ocx->edac_dev, 0, 0, msg);
1248 ocx->link_ring_tail++;
1259 #define OCX_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(ocx, _name, _reg)
1261 OCX_DEBUGFS_ATTR(tlk0_ecc_ctl, OCX_TLKX_ECC_CTL(0));
1262 OCX_DEBUGFS_ATTR(tlk1_ecc_ctl, OCX_TLKX_ECC_CTL(1));
1263 OCX_DEBUGFS_ATTR(tlk2_ecc_ctl, OCX_TLKX_ECC_CTL(2));
1265 OCX_DEBUGFS_ATTR(rlk0_ecc_ctl, OCX_RLKX_ECC_CTL(0));
1266 OCX_DEBUGFS_ATTR(rlk1_ecc_ctl, OCX_RLKX_ECC_CTL(1));
1267 OCX_DEBUGFS_ATTR(rlk2_ecc_ctl, OCX_RLKX_ECC_CTL(2));
1269 OCX_DEBUGFS_ATTR(com_link0_int, OCX_COM_LINKX_INT_W1S(0));
1270 OCX_DEBUGFS_ATTR(com_link1_int, OCX_COM_LINKX_INT_W1S(1));
1271 OCX_DEBUGFS_ATTR(com_link2_int, OCX_COM_LINKX_INT_W1S(2));
1273 OCX_DEBUGFS_ATTR(lne00_badcnt, OCX_LNE_BAD_CNT(0));
1274 OCX_DEBUGFS_ATTR(lne01_badcnt, OCX_LNE_BAD_CNT(1));
1275 OCX_DEBUGFS_ATTR(lne02_badcnt, OCX_LNE_BAD_CNT(2));
1276 OCX_DEBUGFS_ATTR(lne03_badcnt, OCX_LNE_BAD_CNT(3));
1277 OCX_DEBUGFS_ATTR(lne04_badcnt, OCX_LNE_BAD_CNT(4));
1278 OCX_DEBUGFS_ATTR(lne05_badcnt, OCX_LNE_BAD_CNT(5));
1279 OCX_DEBUGFS_ATTR(lne06_badcnt, OCX_LNE_BAD_CNT(6));
1280 OCX_DEBUGFS_ATTR(lne07_badcnt, OCX_LNE_BAD_CNT(7));
1282 OCX_DEBUGFS_ATTR(lne08_badcnt, OCX_LNE_BAD_CNT(8));
1283 OCX_DEBUGFS_ATTR(lne09_badcnt, OCX_LNE_BAD_CNT(9));
1284 OCX_DEBUGFS_ATTR(lne10_badcnt, OCX_LNE_BAD_CNT(10));
1285 OCX_DEBUGFS_ATTR(lne11_badcnt, OCX_LNE_BAD_CNT(11));
1286 OCX_DEBUGFS_ATTR(lne12_badcnt, OCX_LNE_BAD_CNT(12));
1287 OCX_DEBUGFS_ATTR(lne13_badcnt, OCX_LNE_BAD_CNT(13));
1288 OCX_DEBUGFS_ATTR(lne14_badcnt, OCX_LNE_BAD_CNT(14));
1289 OCX_DEBUGFS_ATTR(lne15_badcnt, OCX_LNE_BAD_CNT(15));
1291 OCX_DEBUGFS_ATTR(lne16_badcnt, OCX_LNE_BAD_CNT(16));
1292 OCX_DEBUGFS_ATTR(lne17_badcnt, OCX_LNE_BAD_CNT(17));
1293 OCX_DEBUGFS_ATTR(lne18_badcnt, OCX_LNE_BAD_CNT(18));
1294 OCX_DEBUGFS_ATTR(lne19_badcnt, OCX_LNE_BAD_CNT(19));
1295 OCX_DEBUGFS_ATTR(lne20_badcnt, OCX_LNE_BAD_CNT(20));
1296 OCX_DEBUGFS_ATTR(lne21_badcnt, OCX_LNE_BAD_CNT(21));
1297 OCX_DEBUGFS_ATTR(lne22_badcnt, OCX_LNE_BAD_CNT(22));
1298 OCX_DEBUGFS_ATTR(lne23_badcnt, OCX_LNE_BAD_CNT(23));
1300 OCX_DEBUGFS_ATTR(com_int, OCX_COM_INT_W1S);
1302 struct debugfs_entry *ocx_dfs_ents[] = {
1303 &debugfs_tlk0_ecc_ctl,
1304 &debugfs_tlk1_ecc_ctl,
1305 &debugfs_tlk2_ecc_ctl,
1307 &debugfs_rlk0_ecc_ctl,
1308 &debugfs_rlk1_ecc_ctl,
1309 &debugfs_rlk2_ecc_ctl,
1311 &debugfs_com_link0_int,
1312 &debugfs_com_link1_int,
1313 &debugfs_com_link2_int,
1315 &debugfs_lne00_badcnt,
1316 &debugfs_lne01_badcnt,
1317 &debugfs_lne02_badcnt,
1318 &debugfs_lne03_badcnt,
1319 &debugfs_lne04_badcnt,
1320 &debugfs_lne05_badcnt,
1321 &debugfs_lne06_badcnt,
1322 &debugfs_lne07_badcnt,
1323 &debugfs_lne08_badcnt,
1324 &debugfs_lne09_badcnt,
1325 &debugfs_lne10_badcnt,
1326 &debugfs_lne11_badcnt,
1327 &debugfs_lne12_badcnt,
1328 &debugfs_lne13_badcnt,
1329 &debugfs_lne14_badcnt,
1330 &debugfs_lne15_badcnt,
1331 &debugfs_lne16_badcnt,
1332 &debugfs_lne17_badcnt,
1333 &debugfs_lne18_badcnt,
1334 &debugfs_lne19_badcnt,
1335 &debugfs_lne20_badcnt,
1336 &debugfs_lne21_badcnt,
1337 &debugfs_lne22_badcnt,
1338 &debugfs_lne23_badcnt,
1343 static const struct pci_device_id thunderx_ocx_pci_tbl[] = {
1344 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_OCX) },
1348 static void thunderx_ocx_clearstats(struct thunderx_ocx *ocx)
1350 int lane, stat, cfg;
1352 for (lane = 0; lane < OCX_RX_LANES; lane++) {
1353 cfg = readq(ocx->regs + OCX_LNE_CFG(lane));
1354 cfg |= OCX_LNE_CFG_RX_STAT_RDCLR;
1355 cfg &= ~OCX_LNE_CFG_RX_STAT_ENA;
1356 writeq(cfg, ocx->regs + OCX_LNE_CFG(lane));
1358 for (stat = 0; stat < OCX_RX_LANE_STATS; stat++)
1359 readq(ocx->regs + OCX_LNE_STAT(lane, stat));
1363 static int thunderx_ocx_probe(struct pci_dev *pdev,
1364 const struct pci_device_id *id)
1366 struct thunderx_ocx *ocx;
1367 struct edac_device_ctl_info *edac_dev;
1374 ret = pcim_enable_device(pdev);
1376 dev_err(&pdev->dev, "Cannot enable PCI device: %d\n", ret);
1380 ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_ocx");
1382 dev_err(&pdev->dev, "Cannot map PCI resources: %d\n", ret);
1386 idx = edac_device_alloc_index();
1387 snprintf(name, sizeof(name), "OCX%d", idx);
1388 edac_dev = edac_device_alloc_ctl_info(sizeof(struct thunderx_ocx),
1392 dev_err(&pdev->dev, "Cannot allocate EDAC device: %d\n", ret);
1395 ocx = edac_dev->pvt_info;
1396 ocx->edac_dev = edac_dev;
1397 ocx->com_ring_head = 0;
1398 ocx->com_ring_tail = 0;
1399 ocx->link_ring_head = 0;
1400 ocx->link_ring_tail = 0;
1402 ocx->regs = pcim_iomap_table(pdev)[0];
1404 dev_err(&pdev->dev, "Cannot map PCI resources: %d\n", ret);
1411 for (i = 0; i < OCX_INTS; i++) {
1412 ocx->msix_ent[i].entry = i;
1413 ocx->msix_ent[i].vector = 0;
1416 ret = pci_enable_msix_exact(pdev, ocx->msix_ent, OCX_INTS);
1418 dev_err(&pdev->dev, "Cannot enable interrupt: %d\n", ret);
1422 for (i = 0; i < OCX_INTS; i++) {
1423 ret = devm_request_threaded_irq(&pdev->dev,
1424 ocx->msix_ent[i].vector,
1426 thunderx_ocx_com_isr :
1427 thunderx_ocx_lnk_isr,
1429 thunderx_ocx_com_threaded_isr :
1430 thunderx_ocx_lnk_threaded_isr,
1431 0, "[EDAC] ThunderX OCX",
1437 edac_dev->dev = &pdev->dev;
1438 edac_dev->dev_name = dev_name(&pdev->dev);
1439 edac_dev->mod_name = "thunderx-ocx";
1440 edac_dev->ctl_name = "thunderx-ocx";
1442 ret = edac_device_add_device(edac_dev);
1444 dev_err(&pdev->dev, "Cannot add EDAC device: %d\n", ret);
1448 if (IS_ENABLED(CONFIG_EDAC_DEBUG)) {
1449 ocx->debugfs = edac_debugfs_create_dir(pdev->dev.kobj.name);
1451 ret = thunderx_create_debugfs_nodes(ocx->debugfs,
1454 ARRAY_SIZE(ocx_dfs_ents));
1455 if (ret != ARRAY_SIZE(ocx_dfs_ents)) {
1456 dev_warn(&pdev->dev, "Error creating debugfs entries: %d%s\n",
1457 ret, ret >= 0 ? " created" : "");
1461 pci_set_drvdata(pdev, edac_dev);
1463 thunderx_ocx_clearstats(ocx);
1465 for (i = 0; i < OCX_RX_LANES; i++) {
1466 writeq(OCX_LNE_INT_ENA_ALL,
1467 ocx->regs + OCX_LNE_INT_EN(i));
1469 reg = readq(ocx->regs + OCX_LNE_INT(i));
1470 writeq(reg, ocx->regs + OCX_LNE_INT(i));
1474 for (i = 0; i < OCX_LINK_INTS; i++) {
1475 reg = readq(ocx->regs + OCX_COM_LINKX_INT(i));
1476 writeq(reg, ocx->regs + OCX_COM_LINKX_INT(i));
1478 writeq(OCX_COM_LINKX_INT_ENA_ALL,
1479 ocx->regs + OCX_COM_LINKX_INT_ENA_W1S(i));
1482 reg = readq(ocx->regs + OCX_COM_INT);
1483 writeq(reg, ocx->regs + OCX_COM_INT);
1485 writeq(OCX_COM_INT_ENA_ALL, ocx->regs + OCX_COM_INT_ENA_W1S);
1489 edac_device_free_ctl_info(edac_dev);
1494 static void thunderx_ocx_remove(struct pci_dev *pdev)
1496 struct edac_device_ctl_info *edac_dev = pci_get_drvdata(pdev);
1497 struct thunderx_ocx *ocx = edac_dev->pvt_info;
1500 writeq(OCX_COM_INT_ENA_ALL, ocx->regs + OCX_COM_INT_ENA_W1C);
1502 for (i = 0; i < OCX_INTS; i++) {
1503 writeq(OCX_COM_LINKX_INT_ENA_ALL,
1504 ocx->regs + OCX_COM_LINKX_INT_ENA_W1C(i));
1507 edac_debugfs_remove_recursive(ocx->debugfs);
1509 edac_device_del_device(&pdev->dev);
1510 edac_device_free_ctl_info(edac_dev);
1513 MODULE_DEVICE_TABLE(pci, thunderx_ocx_pci_tbl);
1515 static struct pci_driver thunderx_ocx_driver = {
1516 .name = "thunderx_ocx_edac",
1517 .probe = thunderx_ocx_probe,
1518 .remove = thunderx_ocx_remove,
1519 .id_table = thunderx_ocx_pci_tbl,
1522 /*---------------------- L2C driver ---------------------------------*/
1524 #define PCI_DEVICE_ID_THUNDER_L2C_TAD 0xa02e
1525 #define PCI_DEVICE_ID_THUNDER_L2C_CBC 0xa02f
1526 #define PCI_DEVICE_ID_THUNDER_L2C_MCI 0xa030
1528 #define L2C_TAD_INT_W1C 0x40000
1529 #define L2C_TAD_INT_W1S 0x40008
1531 #define L2C_TAD_INT_ENA_W1C 0x40020
1532 #define L2C_TAD_INT_ENA_W1S 0x40028
1535 #define L2C_TAD_INT_L2DDBE BIT(1)
1536 #define L2C_TAD_INT_SBFSBE BIT(2)
1537 #define L2C_TAD_INT_SBFDBE BIT(3)
1538 #define L2C_TAD_INT_FBFSBE BIT(4)
1539 #define L2C_TAD_INT_FBFDBE BIT(5)
1540 #define L2C_TAD_INT_TAGDBE BIT(9)
1541 #define L2C_TAD_INT_RDDISLMC BIT(15)
1542 #define L2C_TAD_INT_WRDISLMC BIT(16)
1543 #define L2C_TAD_INT_LFBTO BIT(17)
1544 #define L2C_TAD_INT_GSYNCTO BIT(18)
1545 #define L2C_TAD_INT_RTGSBE BIT(32)
1546 #define L2C_TAD_INT_RTGDBE BIT(33)
1547 #define L2C_TAD_INT_RDDISOCI BIT(34)
1548 #define L2C_TAD_INT_WRDISOCI BIT(35)
1550 #define L2C_TAD_INT_ECC (L2C_TAD_INT_L2DDBE | \
1551 L2C_TAD_INT_SBFSBE | L2C_TAD_INT_SBFDBE | \
1552 L2C_TAD_INT_FBFSBE | L2C_TAD_INT_FBFDBE)
1554 #define L2C_TAD_INT_CE (L2C_TAD_INT_SBFSBE | \
1557 #define L2C_TAD_INT_UE (L2C_TAD_INT_L2DDBE | \
1558 L2C_TAD_INT_SBFDBE | \
1559 L2C_TAD_INT_FBFDBE | \
1560 L2C_TAD_INT_TAGDBE | \
1561 L2C_TAD_INT_RTGDBE | \
1562 L2C_TAD_INT_WRDISOCI | \
1563 L2C_TAD_INT_RDDISOCI | \
1564 L2C_TAD_INT_WRDISLMC | \
1565 L2C_TAD_INT_RDDISLMC | \
1566 L2C_TAD_INT_LFBTO | \
1567 L2C_TAD_INT_GSYNCTO)
1569 static const struct error_descr l2_tad_errors[] = {
1571 .type = ERR_CORRECTED,
1572 .mask = L2C_TAD_INT_SBFSBE,
1573 .descr = "SBF single-bit error",
1576 .type = ERR_CORRECTED,
1577 .mask = L2C_TAD_INT_FBFSBE,
1578 .descr = "FBF single-bit error",
1581 .type = ERR_UNCORRECTED,
1582 .mask = L2C_TAD_INT_L2DDBE,
1583 .descr = "L2D double-bit error",
1586 .type = ERR_UNCORRECTED,
1587 .mask = L2C_TAD_INT_SBFDBE,
1588 .descr = "SBF double-bit error",
1591 .type = ERR_UNCORRECTED,
1592 .mask = L2C_TAD_INT_FBFDBE,
1593 .descr = "FBF double-bit error",
1596 .type = ERR_UNCORRECTED,
1597 .mask = L2C_TAD_INT_TAGDBE,
1598 .descr = "TAG double-bit error",
1601 .type = ERR_UNCORRECTED,
1602 .mask = L2C_TAD_INT_RTGDBE,
1603 .descr = "RTG double-bit error",
1606 .type = ERR_UNCORRECTED,
1607 .mask = L2C_TAD_INT_WRDISOCI,
1608 .descr = "Write to a disabled CCPI",
1611 .type = ERR_UNCORRECTED,
1612 .mask = L2C_TAD_INT_RDDISOCI,
1613 .descr = "Read from a disabled CCPI",
1616 .type = ERR_UNCORRECTED,
1617 .mask = L2C_TAD_INT_WRDISLMC,
1618 .descr = "Write to a disabled LMC",
1621 .type = ERR_UNCORRECTED,
1622 .mask = L2C_TAD_INT_RDDISLMC,
1623 .descr = "Read from a disabled LMC",
1626 .type = ERR_UNCORRECTED,
1627 .mask = L2C_TAD_INT_LFBTO,
1628 .descr = "LFB entry timeout",
1631 .type = ERR_UNCORRECTED,
1632 .mask = L2C_TAD_INT_GSYNCTO,
1633 .descr = "Global sync CCPI timeout",
1638 #define L2C_TAD_INT_TAG (L2C_TAD_INT_TAGDBE)
1640 #define L2C_TAD_INT_RTG (L2C_TAD_INT_RTGDBE)
1642 #define L2C_TAD_INT_DISLMC (L2C_TAD_INT_WRDISLMC | L2C_TAD_INT_RDDISLMC)
1644 #define L2C_TAD_INT_DISOCI (L2C_TAD_INT_WRDISOCI | L2C_TAD_INT_RDDISOCI)
1646 #define L2C_TAD_INT_ENA_ALL (L2C_TAD_INT_ECC | L2C_TAD_INT_TAG | \
1648 L2C_TAD_INT_DISLMC | L2C_TAD_INT_DISOCI | \
1651 #define L2C_TAD_TIMETWO 0x50000
1652 #define L2C_TAD_TIMEOUT 0x50100
1653 #define L2C_TAD_ERR 0x60000
1654 #define L2C_TAD_TQD_ERR 0x60100
1655 #define L2C_TAD_TTG_ERR 0x60200
1658 #define L2C_CBC_INT_W1C 0x60000
1660 #define L2C_CBC_INT_RSDSBE BIT(0)
1661 #define L2C_CBC_INT_RSDDBE BIT(1)
1663 #define L2C_CBC_INT_RSD (L2C_CBC_INT_RSDSBE | L2C_CBC_INT_RSDDBE)
1665 #define L2C_CBC_INT_MIBSBE BIT(4)
1666 #define L2C_CBC_INT_MIBDBE BIT(5)
1668 #define L2C_CBC_INT_MIB (L2C_CBC_INT_MIBSBE | L2C_CBC_INT_MIBDBE)
1670 #define L2C_CBC_INT_IORDDISOCI BIT(6)
1671 #define L2C_CBC_INT_IOWRDISOCI BIT(7)
1673 #define L2C_CBC_INT_IODISOCI (L2C_CBC_INT_IORDDISOCI | \
1674 L2C_CBC_INT_IOWRDISOCI)
1676 #define L2C_CBC_INT_CE (L2C_CBC_INT_RSDSBE | L2C_CBC_INT_MIBSBE)
1677 #define L2C_CBC_INT_UE (L2C_CBC_INT_RSDDBE | L2C_CBC_INT_MIBDBE)
1680 static const struct error_descr l2_cbc_errors[] = {
1682 .type = ERR_CORRECTED,
1683 .mask = L2C_CBC_INT_RSDSBE,
1684 .descr = "RSD single-bit error",
1687 .type = ERR_CORRECTED,
1688 .mask = L2C_CBC_INT_MIBSBE,
1689 .descr = "MIB single-bit error",
1692 .type = ERR_UNCORRECTED,
1693 .mask = L2C_CBC_INT_RSDDBE,
1694 .descr = "RSD double-bit error",
1697 .type = ERR_UNCORRECTED,
1698 .mask = L2C_CBC_INT_MIBDBE,
1699 .descr = "MIB double-bit error",
1702 .type = ERR_UNCORRECTED,
1703 .mask = L2C_CBC_INT_IORDDISOCI,
1704 .descr = "Read from a disabled CCPI",
1707 .type = ERR_UNCORRECTED,
1708 .mask = L2C_CBC_INT_IOWRDISOCI,
1709 .descr = "Write to a disabled CCPI",
1714 #define L2C_CBC_INT_W1S 0x60008
1715 #define L2C_CBC_INT_ENA_W1C 0x60020
1717 #define L2C_CBC_INT_ENA_ALL (L2C_CBC_INT_RSD | L2C_CBC_INT_MIB | \
1718 L2C_CBC_INT_IODISOCI)
1720 #define L2C_CBC_INT_ENA_W1S 0x60028
1722 #define L2C_CBC_IODISOCIERR 0x80008
1723 #define L2C_CBC_IOCERR 0x80010
1724 #define L2C_CBC_RSDERR 0x80018
1725 #define L2C_CBC_MIBERR 0x80020
1728 #define L2C_MCI_INT_W1C 0x0
1730 #define L2C_MCI_INT_VBFSBE BIT(0)
1731 #define L2C_MCI_INT_VBFDBE BIT(1)
1733 static const struct error_descr l2_mci_errors[] = {
1735 .type = ERR_CORRECTED,
1736 .mask = L2C_MCI_INT_VBFSBE,
1737 .descr = "VBF single-bit error",
1740 .type = ERR_UNCORRECTED,
1741 .mask = L2C_MCI_INT_VBFDBE,
1742 .descr = "VBF double-bit error",
1747 #define L2C_MCI_INT_W1S 0x8
1748 #define L2C_MCI_INT_ENA_W1C 0x20
1750 #define L2C_MCI_INT_ENA_ALL (L2C_MCI_INT_VBFSBE | L2C_MCI_INT_VBFDBE)
1752 #define L2C_MCI_INT_ENA_W1S 0x28
1754 #define L2C_MCI_ERR 0x10000
1756 #define L2C_MESSAGE_SIZE SZ_1K
1757 #define L2C_OTHER_SIZE (50 * ARRAY_SIZE(l2_tad_errors))
1759 struct l2c_err_ctx {
1765 struct thunderx_l2c {
1767 struct pci_dev *pdev;
1768 struct edac_device_ctl_info *edac_dev;
1770 struct dentry *debugfs;
1774 struct msix_entry msix_ent;
1776 struct l2c_err_ctx err_ctx[RING_ENTRIES];
1777 unsigned long ring_head;
1778 unsigned long ring_tail;
1781 static irqreturn_t thunderx_l2c_tad_isr(int irq, void *irq_id)
1783 struct msix_entry *msix = irq_id;
1784 struct thunderx_l2c *tad = container_of(msix, struct thunderx_l2c,
1787 unsigned long head = ring_pos(tad->ring_head, ARRAY_SIZE(tad->err_ctx));
1788 struct l2c_err_ctx *ctx = &tad->err_ctx[head];
1790 ctx->reg_int = readq(tad->regs + L2C_TAD_INT_W1C);
1792 if (ctx->reg_int & L2C_TAD_INT_ECC) {
1793 ctx->reg_ext_name = "TQD_ERR";
1794 ctx->reg_ext = readq(tad->regs + L2C_TAD_TQD_ERR);
1795 } else if (ctx->reg_int & L2C_TAD_INT_TAG) {
1796 ctx->reg_ext_name = "TTG_ERR";
1797 ctx->reg_ext = readq(tad->regs + L2C_TAD_TTG_ERR);
1798 } else if (ctx->reg_int & L2C_TAD_INT_LFBTO) {
1799 ctx->reg_ext_name = "TIMEOUT";
1800 ctx->reg_ext = readq(tad->regs + L2C_TAD_TIMEOUT);
1801 } else if (ctx->reg_int & L2C_TAD_INT_DISOCI) {
1802 ctx->reg_ext_name = "ERR";
1803 ctx->reg_ext = readq(tad->regs + L2C_TAD_ERR);
1806 writeq(ctx->reg_int, tad->regs + L2C_TAD_INT_W1C);
1810 return IRQ_WAKE_THREAD;
1813 static irqreturn_t thunderx_l2c_cbc_isr(int irq, void *irq_id)
1815 struct msix_entry *msix = irq_id;
1816 struct thunderx_l2c *cbc = container_of(msix, struct thunderx_l2c,
1819 unsigned long head = ring_pos(cbc->ring_head, ARRAY_SIZE(cbc->err_ctx));
1820 struct l2c_err_ctx *ctx = &cbc->err_ctx[head];
1822 ctx->reg_int = readq(cbc->regs + L2C_CBC_INT_W1C);
1824 if (ctx->reg_int & L2C_CBC_INT_RSD) {
1825 ctx->reg_ext_name = "RSDERR";
1826 ctx->reg_ext = readq(cbc->regs + L2C_CBC_RSDERR);
1827 } else if (ctx->reg_int & L2C_CBC_INT_MIB) {
1828 ctx->reg_ext_name = "MIBERR";
1829 ctx->reg_ext = readq(cbc->regs + L2C_CBC_MIBERR);
1830 } else if (ctx->reg_int & L2C_CBC_INT_IODISOCI) {
1831 ctx->reg_ext_name = "IODISOCIERR";
1832 ctx->reg_ext = readq(cbc->regs + L2C_CBC_IODISOCIERR);
1835 writeq(ctx->reg_int, cbc->regs + L2C_CBC_INT_W1C);
1839 return IRQ_WAKE_THREAD;
1842 static irqreturn_t thunderx_l2c_mci_isr(int irq, void *irq_id)
1844 struct msix_entry *msix = irq_id;
1845 struct thunderx_l2c *mci = container_of(msix, struct thunderx_l2c,
1848 unsigned long head = ring_pos(mci->ring_head, ARRAY_SIZE(mci->err_ctx));
1849 struct l2c_err_ctx *ctx = &mci->err_ctx[head];
1851 ctx->reg_int = readq(mci->regs + L2C_MCI_INT_W1C);
1852 ctx->reg_ext = readq(mci->regs + L2C_MCI_ERR);
1854 writeq(ctx->reg_int, mci->regs + L2C_MCI_INT_W1C);
1856 ctx->reg_ext_name = "ERR";
1860 return IRQ_WAKE_THREAD;
1863 static irqreturn_t thunderx_l2c_threaded_isr(int irq, void *irq_id)
1865 struct msix_entry *msix = irq_id;
1866 struct thunderx_l2c *l2c = container_of(msix, struct thunderx_l2c,
1869 unsigned long tail = ring_pos(l2c->ring_tail, ARRAY_SIZE(l2c->err_ctx));
1870 struct l2c_err_ctx *ctx = &l2c->err_ctx[tail];
1871 irqreturn_t ret = IRQ_NONE;
1873 u64 mask_ue, mask_ce;
1874 const struct error_descr *l2_errors;
1880 msg = kmalloc(OCX_MESSAGE_SIZE, GFP_KERNEL);
1881 other = kmalloc(OCX_OTHER_SIZE, GFP_KERNEL);
1886 switch (l2c->pdev->device) {
1887 case PCI_DEVICE_ID_THUNDER_L2C_TAD:
1888 reg_int_name = "L2C_TAD_INT";
1889 mask_ue = L2C_TAD_INT_UE;
1890 mask_ce = L2C_TAD_INT_CE;
1891 l2_errors = l2_tad_errors;
1893 case PCI_DEVICE_ID_THUNDER_L2C_CBC:
1894 reg_int_name = "L2C_CBC_INT";
1895 mask_ue = L2C_CBC_INT_UE;
1896 mask_ce = L2C_CBC_INT_CE;
1897 l2_errors = l2_cbc_errors;
1899 case PCI_DEVICE_ID_THUNDER_L2C_MCI:
1900 reg_int_name = "L2C_MCI_INT";
1901 mask_ue = L2C_MCI_INT_VBFDBE;
1902 mask_ce = L2C_MCI_INT_VBFSBE;
1903 l2_errors = l2_mci_errors;
1906 dev_err(&l2c->pdev->dev, "Unsupported device: %04x\n",
1911 while (CIRC_CNT(l2c->ring_head, l2c->ring_tail,
1912 ARRAY_SIZE(l2c->err_ctx))) {
1913 snprintf(msg, L2C_MESSAGE_SIZE,
1914 "%s: %s: %016llx, %s: %016llx",
1915 l2c->edac_dev->ctl_name, reg_int_name, ctx->reg_int,
1916 ctx->reg_ext_name, ctx->reg_ext);
1918 decode_register(other, L2C_OTHER_SIZE, l2_errors, ctx->reg_int);
1920 strncat(msg, other, L2C_MESSAGE_SIZE);
1922 if (ctx->reg_int & mask_ue)
1923 edac_device_handle_ue(l2c->edac_dev, 0, 0, msg);
1924 else if (ctx->reg_int & mask_ce)
1925 edac_device_handle_ce(l2c->edac_dev, 0, 0, msg);
1939 #define L2C_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(l2c, _name, _reg)
1941 L2C_DEBUGFS_ATTR(tad_int, L2C_TAD_INT_W1S);
1943 struct debugfs_entry *l2c_tad_dfs_ents[] = {
1947 L2C_DEBUGFS_ATTR(cbc_int, L2C_CBC_INT_W1S);
1949 struct debugfs_entry *l2c_cbc_dfs_ents[] = {
1953 L2C_DEBUGFS_ATTR(mci_int, L2C_MCI_INT_W1S);
1955 struct debugfs_entry *l2c_mci_dfs_ents[] = {
1959 static const struct pci_device_id thunderx_l2c_pci_tbl[] = {
1960 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_L2C_TAD), },
1961 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_L2C_CBC), },
1962 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_L2C_MCI), },
1966 static int thunderx_l2c_probe(struct pci_dev *pdev,
1967 const struct pci_device_id *id)
1969 struct thunderx_l2c *l2c;
1970 struct edac_device_ctl_info *edac_dev;
1971 struct debugfs_entry **l2c_devattr;
1973 irqreturn_t (*thunderx_l2c_isr)(int, void *) = NULL;
1976 u64 reg_en_offs, reg_en_mask;
1980 ret = pcim_enable_device(pdev);
1982 dev_err(&pdev->dev, "Cannot enable PCI device: %d\n", ret);
1986 ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_l2c");
1988 dev_err(&pdev->dev, "Cannot map PCI resources: %d\n", ret);
1992 switch (pdev->device) {
1993 case PCI_DEVICE_ID_THUNDER_L2C_TAD:
1994 thunderx_l2c_isr = thunderx_l2c_tad_isr;
1995 l2c_devattr = l2c_tad_dfs_ents;
1996 dfs_entries = ARRAY_SIZE(l2c_tad_dfs_ents);
1998 reg_en_offs = L2C_TAD_INT_ENA_W1S;
1999 reg_en_mask = L2C_TAD_INT_ENA_ALL;
2001 case PCI_DEVICE_ID_THUNDER_L2C_CBC:
2002 thunderx_l2c_isr = thunderx_l2c_cbc_isr;
2003 l2c_devattr = l2c_cbc_dfs_ents;
2004 dfs_entries = ARRAY_SIZE(l2c_cbc_dfs_ents);
2006 reg_en_offs = L2C_CBC_INT_ENA_W1S;
2007 reg_en_mask = L2C_CBC_INT_ENA_ALL;
2009 case PCI_DEVICE_ID_THUNDER_L2C_MCI:
2010 thunderx_l2c_isr = thunderx_l2c_mci_isr;
2011 l2c_devattr = l2c_mci_dfs_ents;
2012 dfs_entries = ARRAY_SIZE(l2c_mci_dfs_ents);
2014 reg_en_offs = L2C_MCI_INT_ENA_W1S;
2015 reg_en_mask = L2C_MCI_INT_ENA_ALL;
2018 //Should never ever get here
2019 dev_err(&pdev->dev, "Unsupported PCI device: %04x\n",
2024 idx = edac_device_alloc_index();
2025 snprintf(name, sizeof(name), fmt, idx);
2027 edac_dev = edac_device_alloc_ctl_info(sizeof(struct thunderx_l2c),
2028 name, 1, "L2C", 1, 0,
2031 dev_err(&pdev->dev, "Cannot allocate EDAC device\n");
2035 l2c = edac_dev->pvt_info;
2036 l2c->edac_dev = edac_dev;
2038 l2c->regs = pcim_iomap_table(pdev)[0];
2040 dev_err(&pdev->dev, "Cannot map PCI resources\n");
2050 l2c->msix_ent.entry = 0;
2051 l2c->msix_ent.vector = 0;
2053 ret = pci_enable_msix_exact(pdev, &l2c->msix_ent, 1);
2055 dev_err(&pdev->dev, "Cannot enable interrupt: %d\n", ret);
2059 ret = devm_request_threaded_irq(&pdev->dev, l2c->msix_ent.vector,
2061 thunderx_l2c_threaded_isr,
2062 0, "[EDAC] ThunderX L2C",
2067 edac_dev->dev = &pdev->dev;
2068 edac_dev->dev_name = dev_name(&pdev->dev);
2069 edac_dev->mod_name = "thunderx-l2c";
2070 edac_dev->ctl_name = "thunderx-l2c";
2072 ret = edac_device_add_device(edac_dev);
2074 dev_err(&pdev->dev, "Cannot add EDAC device: %d\n", ret);
2078 if (IS_ENABLED(CONFIG_EDAC_DEBUG)) {
2079 l2c->debugfs = edac_debugfs_create_dir(pdev->dev.kobj.name);
2081 ret = thunderx_create_debugfs_nodes(l2c->debugfs, l2c_devattr,
2084 if (ret != dfs_entries) {
2085 dev_warn(&pdev->dev, "Error creating debugfs entries: %d%s\n",
2086 ret, ret >= 0 ? " created" : "");
2090 pci_set_drvdata(pdev, edac_dev);
2092 writeq(reg_en_mask, l2c->regs + reg_en_offs);
2097 edac_device_free_ctl_info(edac_dev);
2102 static void thunderx_l2c_remove(struct pci_dev *pdev)
2104 struct edac_device_ctl_info *edac_dev = pci_get_drvdata(pdev);
2105 struct thunderx_l2c *l2c = edac_dev->pvt_info;
2107 switch (pdev->device) {
2108 case PCI_DEVICE_ID_THUNDER_L2C_TAD:
2109 writeq(L2C_TAD_INT_ENA_ALL, l2c->regs + L2C_TAD_INT_ENA_W1C);
2111 case PCI_DEVICE_ID_THUNDER_L2C_CBC:
2112 writeq(L2C_CBC_INT_ENA_ALL, l2c->regs + L2C_CBC_INT_ENA_W1C);
2114 case PCI_DEVICE_ID_THUNDER_L2C_MCI:
2115 writeq(L2C_MCI_INT_ENA_ALL, l2c->regs + L2C_MCI_INT_ENA_W1C);
2119 edac_debugfs_remove_recursive(l2c->debugfs);
2121 edac_device_del_device(&pdev->dev);
2122 edac_device_free_ctl_info(edac_dev);
2125 MODULE_DEVICE_TABLE(pci, thunderx_l2c_pci_tbl);
2127 static struct pci_driver thunderx_l2c_driver = {
2128 .name = "thunderx_l2c_edac",
2129 .probe = thunderx_l2c_probe,
2130 .remove = thunderx_l2c_remove,
2131 .id_table = thunderx_l2c_pci_tbl,
2134 static int __init thunderx_edac_init(void)
2138 rc = pci_register_driver(&thunderx_lmc_driver);
2142 rc = pci_register_driver(&thunderx_ocx_driver);
2146 rc = pci_register_driver(&thunderx_l2c_driver);
2152 pci_unregister_driver(&thunderx_ocx_driver);
2154 pci_unregister_driver(&thunderx_lmc_driver);
2159 static void __exit thunderx_edac_exit(void)
2161 pci_unregister_driver(&thunderx_l2c_driver);
2162 pci_unregister_driver(&thunderx_ocx_driver);
2163 pci_unregister_driver(&thunderx_lmc_driver);
2167 module_init(thunderx_edac_init);
2168 module_exit(thunderx_edac_exit);
2170 MODULE_LICENSE("GPL v2");
2171 MODULE_AUTHOR("Cavium, Inc.");
2172 MODULE_DESCRIPTION("EDAC Driver for Cavium ThunderX");