2 * Synopsys DDR ECC Driver
3 * This driver is based on ppc4xx_edac.c drivers
5 * Copyright (C) 2012 - 2014 Xilinx, Inc.
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
22 #include <linux/edac.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
27 #include <linux/of_device.h>
29 #include "edac_module.h"
31 /* Number of cs_rows needed per memory controller */
32 #define SYNPS_EDAC_NR_CSROWS 1
34 /* Number of channels per memory controller */
35 #define SYNPS_EDAC_NR_CHANS 1
37 /* Granularity of reported error in bytes */
38 #define SYNPS_EDAC_ERR_GRAIN 1
40 #define SYNPS_EDAC_MSG_SIZE 256
42 #define SYNPS_EDAC_MOD_STRING "synps_edac"
43 #define SYNPS_EDAC_MOD_VER "1"
45 /* Synopsys DDR memory controller registers that are relevant to ECC */
47 #define T_ZQ_OFST 0xA4
49 /* ECC control register */
50 #define ECC_CTRL_OFST 0xC4
51 /* ECC log register */
52 #define CE_LOG_OFST 0xC8
53 /* ECC address register */
54 #define CE_ADDR_OFST 0xCC
55 /* ECC data[31:0] register */
56 #define CE_DATA_31_0_OFST 0xD0
58 /* Uncorrectable error info registers */
59 #define UE_LOG_OFST 0xDC
60 #define UE_ADDR_OFST 0xE0
61 #define UE_DATA_31_0_OFST 0xE4
63 #define STAT_OFST 0xF0
64 #define SCRUB_OFST 0xF4
66 /* Control register bit field definitions */
67 #define CTRL_BW_MASK 0xC
68 #define CTRL_BW_SHIFT 2
70 #define DDRCTL_WDTH_16 1
71 #define DDRCTL_WDTH_32 0
73 /* ZQ register bit field definitions */
74 #define T_ZQ_DDRMODE_MASK 0x2
76 /* ECC control register bit field definitions */
77 #define ECC_CTRL_CLR_CE_ERR 0x2
78 #define ECC_CTRL_CLR_UE_ERR 0x1
80 /* ECC correctable/uncorrectable error log register definitions */
82 #define CE_LOG_BITPOS_MASK 0xFE
83 #define CE_LOG_BITPOS_SHIFT 1
85 /* ECC correctable/uncorrectable error address register definitions */
86 #define ADDR_COL_MASK 0xFFF
87 #define ADDR_ROW_MASK 0xFFFF000
88 #define ADDR_ROW_SHIFT 12
89 #define ADDR_BANK_MASK 0x70000000
90 #define ADDR_BANK_SHIFT 28
92 /* ECC statistic register definitions */
93 #define STAT_UECNT_MASK 0xFF
94 #define STAT_CECNT_MASK 0xFF00
95 #define STAT_CECNT_SHIFT 8
97 /* ECC scrub register definitions */
98 #define SCRUB_MODE_MASK 0x7
99 #define SCRUB_MODE_SECDED 0x4
102 #define DDR_ECC_INTR_SUPPORT BIT(0)
103 #define DDR_ECC_DATA_POISON_SUPPORT BIT(1)
104 #define DDR_ECC_INTR_SELF_CLEAR BIT(2)
106 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
107 /* ECC Configuration Registers */
108 #define ECC_CFG0_OFST 0x70
109 #define ECC_CFG1_OFST 0x74
111 /* ECC Status Register */
112 #define ECC_STAT_OFST 0x78
114 /* ECC Clear Register */
115 #define ECC_CLR_OFST 0x7C
117 /* ECC Error count Register */
118 #define ECC_ERRCNT_OFST 0x80
120 /* ECC Corrected Error Address Register */
121 #define ECC_CEADDR0_OFST 0x84
122 #define ECC_CEADDR1_OFST 0x88
124 /* ECC Syndrome Registers */
125 #define ECC_CSYND0_OFST 0x8C
126 #define ECC_CSYND1_OFST 0x90
127 #define ECC_CSYND2_OFST 0x94
129 /* ECC Bit Mask0 Address Register */
130 #define ECC_BITMASK0_OFST 0x98
131 #define ECC_BITMASK1_OFST 0x9C
132 #define ECC_BITMASK2_OFST 0xA0
134 /* ECC UnCorrected Error Address Register */
135 #define ECC_UEADDR0_OFST 0xA4
136 #define ECC_UEADDR1_OFST 0xA8
138 /* ECC Syndrome Registers */
139 #define ECC_UESYND0_OFST 0xAC
140 #define ECC_UESYND1_OFST 0xB0
141 #define ECC_UESYND2_OFST 0xB4
143 /* ECC Poison Address Reg */
144 #define ECC_POISON0_OFST 0xB8
145 #define ECC_POISON1_OFST 0xBC
147 #define ECC_ADDRMAP0_OFFSET 0x200
149 /* Control register bitfield definitions */
150 #define ECC_CTRL_BUSWIDTH_MASK 0x3000
151 #define ECC_CTRL_BUSWIDTH_SHIFT 12
152 #define ECC_CTRL_CLR_CE_ERRCNT BIT(2)
153 #define ECC_CTRL_CLR_UE_ERRCNT BIT(3)
155 /* DDR Control Register width definitions */
156 #define DDRCTL_EWDTH_16 2
157 #define DDRCTL_EWDTH_32 1
158 #define DDRCTL_EWDTH_64 0
160 /* ECC status register definitions */
161 #define ECC_STAT_UECNT_MASK 0xF0000
162 #define ECC_STAT_UECNT_SHIFT 16
163 #define ECC_STAT_CECNT_MASK 0xF00
164 #define ECC_STAT_CECNT_SHIFT 8
165 #define ECC_STAT_BITNUM_MASK 0x7F
167 /* DDR QOS Interrupt register definitions */
168 #define DDR_QOS_IRQ_STAT_OFST 0x20200
169 #define DDR_QOSUE_MASK 0x4
170 #define DDR_QOSCE_MASK 0x2
171 #define ECC_CE_UE_INTR_MASK 0x6
172 #define DDR_QOS_IRQ_EN_OFST 0x20208
173 #define DDR_QOS_IRQ_DB_OFST 0x2020C
175 /* DDR QOS Interrupt register definitions */
176 #define DDR_UE_MASK BIT(9)
177 #define DDR_CE_MASK BIT(8)
179 /* ECC Corrected Error Register Mask and Shifts*/
180 #define ECC_CEADDR0_RW_MASK 0x3FFFF
181 #define ECC_CEADDR0_RNK_MASK BIT(24)
182 #define ECC_CEADDR1_BNKGRP_MASK 0x3000000
183 #define ECC_CEADDR1_BNKNR_MASK 0x70000
184 #define ECC_CEADDR1_BLKNR_MASK 0xFFF
185 #define ECC_CEADDR1_BNKGRP_SHIFT 24
186 #define ECC_CEADDR1_BNKNR_SHIFT 16
188 /* ECC Poison register shifts */
189 #define ECC_POISON0_RANK_SHIFT 24
190 #define ECC_POISON0_RANK_MASK BIT(24)
191 #define ECC_POISON0_COLUMN_SHIFT 0
192 #define ECC_POISON0_COLUMN_MASK 0xFFF
193 #define ECC_POISON1_BG_SHIFT 28
194 #define ECC_POISON1_BG_MASK 0x30000000
195 #define ECC_POISON1_BANKNR_SHIFT 24
196 #define ECC_POISON1_BANKNR_MASK 0x7000000
197 #define ECC_POISON1_ROW_SHIFT 0
198 #define ECC_POISON1_ROW_MASK 0x3FFFF
200 /* DDR Memory type defines */
201 #define MEM_TYPE_DDR3 0x1
202 #define MEM_TYPE_LPDDR3 0x8
203 #define MEM_TYPE_DDR2 0x4
204 #define MEM_TYPE_DDR4 0x10
205 #define MEM_TYPE_LPDDR4 0x20
207 /* DDRC Software control register */
208 #define DDRC_SWCTL 0x320
210 /* DDRC ECC CE & UE poison mask */
211 #define ECC_CEPOISON_MASK 0x3
212 #define ECC_UEPOISON_MASK 0x1
214 /* DDRC Device config masks */
215 #define DDRC_MSTR_CFG_MASK 0xC0000000
216 #define DDRC_MSTR_CFG_SHIFT 30
217 #define DDRC_MSTR_CFG_X4_MASK 0x0
218 #define DDRC_MSTR_CFG_X8_MASK 0x1
219 #define DDRC_MSTR_CFG_X16_MASK 0x2
220 #define DDRC_MSTR_CFG_X32_MASK 0x3
222 #define DDR_MAX_ROW_SHIFT 18
223 #define DDR_MAX_COL_SHIFT 14
224 #define DDR_MAX_BANK_SHIFT 3
225 #define DDR_MAX_BANKGRP_SHIFT 2
227 #define ROW_MAX_VAL_MASK 0xF
228 #define COL_MAX_VAL_MASK 0xF
229 #define BANK_MAX_VAL_MASK 0x1F
230 #define BANKGRP_MAX_VAL_MASK 0x1F
231 #define RANK_MAX_VAL_MASK 0x1F
233 #define ROW_B0_BASE 6
234 #define ROW_B1_BASE 7
235 #define ROW_B2_BASE 8
236 #define ROW_B3_BASE 9
237 #define ROW_B4_BASE 10
238 #define ROW_B5_BASE 11
239 #define ROW_B6_BASE 12
240 #define ROW_B7_BASE 13
241 #define ROW_B8_BASE 14
242 #define ROW_B9_BASE 15
243 #define ROW_B10_BASE 16
244 #define ROW_B11_BASE 17
245 #define ROW_B12_BASE 18
246 #define ROW_B13_BASE 19
247 #define ROW_B14_BASE 20
248 #define ROW_B15_BASE 21
249 #define ROW_B16_BASE 22
250 #define ROW_B17_BASE 23
252 #define COL_B2_BASE 2
253 #define COL_B3_BASE 3
254 #define COL_B4_BASE 4
255 #define COL_B5_BASE 5
256 #define COL_B6_BASE 6
257 #define COL_B7_BASE 7
258 #define COL_B8_BASE 8
259 #define COL_B9_BASE 9
260 #define COL_B10_BASE 10
261 #define COL_B11_BASE 11
262 #define COL_B12_BASE 12
263 #define COL_B13_BASE 13
265 #define BANK_B0_BASE 2
266 #define BANK_B1_BASE 3
267 #define BANK_B2_BASE 4
269 #define BANKGRP_B0_BASE 2
270 #define BANKGRP_B1_BASE 3
272 #define RANK_B0_BASE 6
275 * struct ecc_error_info - ECC error log information.
277 * @col: Column number.
278 * @bank: Bank number.
279 * @bitpos: Bit position.
280 * @data: Data causing the error.
281 * @bankgrpnr: Bank group number.
282 * @blknr: Block number.
284 struct ecc_error_info {
295 * struct synps_ecc_status - ECC status information to report.
296 * @ce_cnt: Correctable error count.
297 * @ue_cnt: Uncorrectable error count.
298 * @ceinfo: Correctable error log information.
299 * @ueinfo: Uncorrectable error log information.
301 struct synps_ecc_status {
304 struct ecc_error_info ceinfo;
305 struct ecc_error_info ueinfo;
309 * struct synps_edac_priv - DDR memory controller private instance data.
310 * @baseaddr: Base address of the DDR controller.
311 * @message: Buffer for framing the event specific info.
312 * @stat: ECC status information.
313 * @p_data: Platform data.
314 * @ce_cnt: Correctable Error count.
315 * @ue_cnt: Uncorrectable Error count.
316 * @poison_addr: Data poison address.
317 * @row_shift: Bit shifts for row bit.
318 * @col_shift: Bit shifts for column bit.
319 * @bank_shift: Bit shifts for bank bit.
320 * @bankgrp_shift: Bit shifts for bank group bit.
321 * @rank_shift: Bit shifts for rank bit.
323 struct synps_edac_priv {
324 void __iomem *baseaddr;
325 char message[SYNPS_EDAC_MSG_SIZE];
326 struct synps_ecc_status stat;
327 const struct synps_platform_data *p_data;
330 #ifdef CONFIG_EDAC_DEBUG
335 u32 bankgrp_shift[2];
341 * struct synps_platform_data - synps platform data structure.
342 * @get_error_info: Get EDAC error info.
343 * @get_mtype: Get mtype.
344 * @get_dtype: Get dtype.
345 * @get_ecc_state: Get ECC state.
346 * @quirks: To differentiate IPs.
348 struct synps_platform_data {
349 int (*get_error_info)(struct synps_edac_priv *priv);
350 enum mem_type (*get_mtype)(const void __iomem *base);
351 enum dev_type (*get_dtype)(const void __iomem *base);
352 bool (*get_ecc_state)(void __iomem *base);
357 * zynq_get_error_info - Get the current ECC error info.
358 * @priv: DDR memory controller private instance data.
360 * Return: one if there is no error, otherwise zero.
362 static int zynq_get_error_info(struct synps_edac_priv *priv)
364 struct synps_ecc_status *p;
365 u32 regval, clearval = 0;
368 base = priv->baseaddr;
371 regval = readl(base + STAT_OFST);
375 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT;
376 p->ue_cnt = regval & STAT_UECNT_MASK;
378 regval = readl(base + CE_LOG_OFST);
379 if (!(p->ce_cnt && (regval & LOG_VALID)))
382 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT;
383 regval = readl(base + CE_ADDR_OFST);
384 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
385 p->ceinfo.col = regval & ADDR_COL_MASK;
386 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
387 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST);
388 edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos,
390 clearval = ECC_CTRL_CLR_CE_ERR;
393 regval = readl(base + UE_LOG_OFST);
394 if (!(p->ue_cnt && (regval & LOG_VALID)))
397 regval = readl(base + UE_ADDR_OFST);
398 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
399 p->ueinfo.col = regval & ADDR_COL_MASK;
400 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
401 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST);
402 clearval |= ECC_CTRL_CLR_UE_ERR;
405 writel(clearval, base + ECC_CTRL_OFST);
406 writel(0x0, base + ECC_CTRL_OFST);
412 * zynqmp_get_error_info - Get the current ECC error info.
413 * @priv: DDR memory controller private instance data.
415 * Return: one if there is no error otherwise returns zero.
417 static int zynqmp_get_error_info(struct synps_edac_priv *priv)
419 struct synps_ecc_status *p;
420 u32 regval, clearval = 0;
423 base = priv->baseaddr;
426 regval = readl(base + ECC_STAT_OFST);
430 p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT;
431 p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT;
435 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
437 regval = readl(base + ECC_CEADDR0_OFST);
438 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK);
439 regval = readl(base + ECC_CEADDR1_OFST);
440 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
441 ECC_CEADDR1_BNKNR_SHIFT;
442 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
443 ECC_CEADDR1_BNKGRP_SHIFT;
444 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
445 p->ceinfo.data = readl(base + ECC_CSYND0_OFST);
446 edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n",
447 readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST),
448 readl(base + ECC_CSYND2_OFST));
453 regval = readl(base + ECC_UEADDR0_OFST);
454 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK);
455 regval = readl(base + ECC_UEADDR1_OFST);
456 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
457 ECC_CEADDR1_BNKGRP_SHIFT;
458 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
459 ECC_CEADDR1_BNKNR_SHIFT;
460 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
461 p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
463 clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT;
464 clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT;
465 writel(clearval, base + ECC_CLR_OFST);
466 writel(0x0, base + ECC_CLR_OFST);
472 * handle_error - Handle Correctable and Uncorrectable errors.
473 * @mci: EDAC memory controller instance.
474 * @p: Synopsys ECC status structure.
476 * Handles ECC correctable and uncorrectable errors.
478 static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
480 struct synps_edac_priv *priv = mci->pvt_info;
481 struct ecc_error_info *pinf;
485 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
486 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
487 "DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x",
488 "CE", pinf->row, pinf->bank,
489 pinf->bankgrpnr, pinf->blknr,
490 pinf->bitpos, pinf->data);
492 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
493 "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x",
494 "CE", pinf->row, pinf->bank, pinf->col,
495 pinf->bitpos, pinf->data);
498 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
499 p->ce_cnt, 0, 0, 0, 0, 0, -1,
505 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
506 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
507 "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d",
508 "UE", pinf->row, pinf->bank,
509 pinf->bankgrpnr, pinf->blknr);
511 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
512 "DDR ECC error type :%s Row %d Bank %d Col %d ",
513 "UE", pinf->row, pinf->bank, pinf->col);
516 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
517 p->ue_cnt, 0, 0, 0, 0, 0, -1,
521 memset(p, 0, sizeof(*p));
525 * intr_handler - Interrupt Handler for ECC interrupts.
527 * @dev_id: Device ID.
529 * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise.
531 static irqreturn_t intr_handler(int irq, void *dev_id)
533 const struct synps_platform_data *p_data;
534 struct mem_ctl_info *mci = dev_id;
535 struct synps_edac_priv *priv;
538 priv = mci->pvt_info;
539 p_data = priv->p_data;
542 * v3.0 of the controller has the ce/ue bits cleared automatically,
543 * so this condition does not apply.
545 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
546 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
547 regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK);
548 if (!(regval & ECC_CE_UE_INTR_MASK))
552 status = p_data->get_error_info(priv);
556 priv->ce_cnt += priv->stat.ce_cnt;
557 priv->ue_cnt += priv->stat.ue_cnt;
558 handle_error(mci, &priv->stat);
560 edac_dbg(3, "Total error count CE %d UE %d\n",
561 priv->ce_cnt, priv->ue_cnt);
562 /* v3.0 of the controller does not have this register */
563 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
564 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
569 * check_errors - Check controller for ECC errors.
570 * @mci: EDAC memory controller instance.
572 * Check and post ECC errors. Called by the polling thread.
574 static void check_errors(struct mem_ctl_info *mci)
576 const struct synps_platform_data *p_data;
577 struct synps_edac_priv *priv;
580 priv = mci->pvt_info;
581 p_data = priv->p_data;
583 status = p_data->get_error_info(priv);
587 priv->ce_cnt += priv->stat.ce_cnt;
588 priv->ue_cnt += priv->stat.ue_cnt;
589 handle_error(mci, &priv->stat);
591 edac_dbg(3, "Total error count CE %d UE %d\n",
592 priv->ce_cnt, priv->ue_cnt);
596 * zynq_get_dtype - Return the controller memory width.
597 * @base: DDR memory controller base address.
599 * Get the EDAC device type width appropriate for the current controller
602 * Return: a device type width enumeration.
604 static enum dev_type zynq_get_dtype(const void __iomem *base)
609 width = readl(base + CTRL_OFST);
610 width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT;
627 * zynqmp_get_dtype - Return the controller memory width.
628 * @base: DDR memory controller base address.
630 * Get the EDAC device type width appropriate for the current controller
633 * Return: a device type width enumeration.
635 static enum dev_type zynqmp_get_dtype(const void __iomem *base)
640 width = readl(base + CTRL_OFST);
641 width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
643 case DDRCTL_EWDTH_16:
646 case DDRCTL_EWDTH_32:
649 case DDRCTL_EWDTH_64:
660 * zynq_get_ecc_state - Return the controller ECC enable/disable status.
661 * @base: DDR memory controller base address.
663 * Get the ECC enable/disable status of the controller.
665 * Return: true if enabled, otherwise false.
667 static bool zynq_get_ecc_state(void __iomem *base)
672 dt = zynq_get_dtype(base);
673 if (dt == DEV_UNKNOWN)
676 ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK;
677 if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2))
684 * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
685 * @base: DDR memory controller base address.
687 * Get the ECC enable/disable status for the controller.
689 * Return: a ECC status boolean i.e true/false - enabled/disabled.
691 static bool zynqmp_get_ecc_state(void __iomem *base)
696 dt = zynqmp_get_dtype(base);
697 if (dt == DEV_UNKNOWN)
700 ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK;
701 if ((ecctype == SCRUB_MODE_SECDED) &&
702 ((dt == DEV_X2) || (dt == DEV_X4) || (dt == DEV_X8)))
709 * get_memsize - Read the size of the attached memory device.
711 * Return: the memory size in bytes.
713 static u32 get_memsize(void)
719 return inf.totalram * inf.mem_unit;
723 * zynq_get_mtype - Return the controller memory type.
724 * @base: Synopsys ECC status structure.
726 * Get the EDAC memory type appropriate for the current controller
729 * Return: a memory type enumeration.
731 static enum mem_type zynq_get_mtype(const void __iomem *base)
736 memtype = readl(base + T_ZQ_OFST);
738 if (memtype & T_ZQ_DDRMODE_MASK)
747 * zynqmp_get_mtype - Returns controller memory type.
748 * @base: Synopsys ECC status structure.
750 * Get the EDAC memory type appropriate for the current controller
753 * Return: a memory type enumeration.
755 static enum mem_type zynqmp_get_mtype(const void __iomem *base)
760 memtype = readl(base + CTRL_OFST);
762 if ((memtype & MEM_TYPE_DDR3) || (memtype & MEM_TYPE_LPDDR3))
764 else if (memtype & MEM_TYPE_DDR2)
766 else if ((memtype & MEM_TYPE_LPDDR4) || (memtype & MEM_TYPE_DDR4))
775 * init_csrows - Initialize the csrow data.
776 * @mci: EDAC memory controller instance.
778 * Initialize the chip select rows associated with the EDAC memory
779 * controller instance.
781 static void init_csrows(struct mem_ctl_info *mci)
783 struct synps_edac_priv *priv = mci->pvt_info;
784 const struct synps_platform_data *p_data;
785 struct csrow_info *csi;
786 struct dimm_info *dimm;
790 p_data = priv->p_data;
792 for (row = 0; row < mci->nr_csrows; row++) {
793 csi = mci->csrows[row];
794 size = get_memsize();
796 for (j = 0; j < csi->nr_channels; j++) {
797 dimm = csi->channels[j]->dimm;
798 dimm->edac_mode = EDAC_SECDED;
799 dimm->mtype = p_data->get_mtype(priv->baseaddr);
800 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
801 dimm->grain = SYNPS_EDAC_ERR_GRAIN;
802 dimm->dtype = p_data->get_dtype(priv->baseaddr);
808 * mc_init - Initialize one driver instance.
809 * @mci: EDAC memory controller instance.
810 * @pdev: platform device.
812 * Perform initialization of the EDAC memory controller instance and
813 * related driver-private data associated with the memory controller the
814 * instance is bound to.
816 static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
818 struct synps_edac_priv *priv;
820 mci->pdev = &pdev->dev;
821 priv = mci->pvt_info;
822 platform_set_drvdata(pdev, mci);
824 /* Initialize controller capabilities and configuration */
825 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2;
826 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
827 mci->scrub_cap = SCRUB_HW_SRC;
828 mci->scrub_mode = SCRUB_NONE;
830 mci->edac_cap = EDAC_FLAG_SECDED;
831 mci->ctl_name = "synps_ddr_controller";
832 mci->dev_name = SYNPS_EDAC_MOD_STRING;
833 mci->mod_name = SYNPS_EDAC_MOD_VER;
835 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
836 edac_op_state = EDAC_OPSTATE_INT;
838 edac_op_state = EDAC_OPSTATE_POLL;
839 mci->edac_check = check_errors;
842 mci->ctl_page_to_phys = NULL;
847 static void enable_intr(struct synps_edac_priv *priv)
849 /* Enable UE/CE Interrupts */
850 if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
851 writel(DDR_UE_MASK | DDR_CE_MASK,
852 priv->baseaddr + ECC_CLR_OFST);
854 writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
855 priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
859 static void disable_intr(struct synps_edac_priv *priv)
861 /* Disable UE/CE Interrupts */
862 writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
863 priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
866 static int setup_irq(struct mem_ctl_info *mci,
867 struct platform_device *pdev)
869 struct synps_edac_priv *priv = mci->pvt_info;
872 irq = platform_get_irq(pdev, 0);
874 edac_printk(KERN_ERR, EDAC_MC,
875 "No IRQ %d in DT\n", irq);
879 ret = devm_request_irq(&pdev->dev, irq, intr_handler,
880 0, dev_name(&pdev->dev), mci);
882 edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n");
891 static const struct synps_platform_data zynq_edac_def = {
892 .get_error_info = zynq_get_error_info,
893 .get_mtype = zynq_get_mtype,
894 .get_dtype = zynq_get_dtype,
895 .get_ecc_state = zynq_get_ecc_state,
899 static const struct synps_platform_data zynqmp_edac_def = {
900 .get_error_info = zynqmp_get_error_info,
901 .get_mtype = zynqmp_get_mtype,
902 .get_dtype = zynqmp_get_dtype,
903 .get_ecc_state = zynqmp_get_ecc_state,
904 .quirks = (DDR_ECC_INTR_SUPPORT
905 #ifdef CONFIG_EDAC_DEBUG
906 | DDR_ECC_DATA_POISON_SUPPORT
911 static const struct synps_platform_data synopsys_edac_def = {
912 .get_error_info = zynqmp_get_error_info,
913 .get_mtype = zynqmp_get_mtype,
914 .get_dtype = zynqmp_get_dtype,
915 .get_ecc_state = zynqmp_get_ecc_state,
916 .quirks = (DDR_ECC_INTR_SUPPORT | DDR_ECC_INTR_SELF_CLEAR
917 #ifdef CONFIG_EDAC_DEBUG
918 | DDR_ECC_DATA_POISON_SUPPORT
924 static const struct of_device_id synps_edac_match[] = {
926 .compatible = "xlnx,zynq-ddrc-a05",
927 .data = (void *)&zynq_edac_def
930 .compatible = "xlnx,zynqmp-ddrc-2.40a",
931 .data = (void *)&zynqmp_edac_def
934 .compatible = "snps,ddrc-3.80a",
935 .data = (void *)&synopsys_edac_def
942 MODULE_DEVICE_TABLE(of, synps_edac_match);
944 #ifdef CONFIG_EDAC_DEBUG
945 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
948 * ddr_poison_setup - Update poison registers.
949 * @priv: DDR memory controller private instance data.
951 * Update poison registers as per DDR mapping.
954 static void ddr_poison_setup(struct synps_edac_priv *priv)
956 int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval;
960 hif_addr = priv->poison_addr >> 3;
962 for (index = 0; index < DDR_MAX_ROW_SHIFT; index++) {
963 if (priv->row_shift[index])
964 row |= (((hif_addr >> priv->row_shift[index]) &
970 for (index = 0; index < DDR_MAX_COL_SHIFT; index++) {
971 if (priv->col_shift[index] || index < 3)
972 col |= (((hif_addr >> priv->col_shift[index]) &
978 for (index = 0; index < DDR_MAX_BANK_SHIFT; index++) {
979 if (priv->bank_shift[index])
980 bank |= (((hif_addr >> priv->bank_shift[index]) &
986 for (index = 0; index < DDR_MAX_BANKGRP_SHIFT; index++) {
987 if (priv->bankgrp_shift[index])
988 bankgrp |= (((hif_addr >> priv->bankgrp_shift[index])
994 if (priv->rank_shift[0])
995 rank = (hif_addr >> priv->rank_shift[0]) & BIT(0);
997 regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK;
998 regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK;
999 writel(regval, priv->baseaddr + ECC_POISON0_OFST);
1001 regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK;
1002 regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK;
1003 regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK;
1004 writel(regval, priv->baseaddr + ECC_POISON1_OFST);
1007 static ssize_t inject_data_error_show(struct device *dev,
1008 struct device_attribute *mattr,
1011 struct mem_ctl_info *mci = to_mci(dev);
1012 struct synps_edac_priv *priv = mci->pvt_info;
1014 return sprintf(data, "Poison0 Addr: 0x%08x\n\rPoison1 Addr: 0x%08x\n\r"
1015 "Error injection Address: 0x%lx\n\r",
1016 readl(priv->baseaddr + ECC_POISON0_OFST),
1017 readl(priv->baseaddr + ECC_POISON1_OFST),
1021 static ssize_t inject_data_error_store(struct device *dev,
1022 struct device_attribute *mattr,
1023 const char *data, size_t count)
1025 struct mem_ctl_info *mci = to_mci(dev);
1026 struct synps_edac_priv *priv = mci->pvt_info;
1028 if (kstrtoul(data, 0, &priv->poison_addr))
1031 ddr_poison_setup(priv);
1036 static ssize_t inject_data_poison_show(struct device *dev,
1037 struct device_attribute *mattr,
1040 struct mem_ctl_info *mci = to_mci(dev);
1041 struct synps_edac_priv *priv = mci->pvt_info;
1043 return sprintf(data, "Data Poisoning: %s\n\r",
1044 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3)
1045 ? ("Correctable Error") : ("UnCorrectable Error"));
1048 static ssize_t inject_data_poison_store(struct device *dev,
1049 struct device_attribute *mattr,
1050 const char *data, size_t count)
1052 struct mem_ctl_info *mci = to_mci(dev);
1053 struct synps_edac_priv *priv = mci->pvt_info;
1055 writel(0, priv->baseaddr + DDRC_SWCTL);
1056 if (strncmp(data, "CE", 2) == 0)
1057 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1059 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1060 writel(1, priv->baseaddr + DDRC_SWCTL);
1065 static DEVICE_ATTR_RW(inject_data_error);
1066 static DEVICE_ATTR_RW(inject_data_poison);
1068 static int edac_create_sysfs_attributes(struct mem_ctl_info *mci)
1072 rc = device_create_file(&mci->dev, &dev_attr_inject_data_error);
1075 rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison);
1081 static void edac_remove_sysfs_attributes(struct mem_ctl_info *mci)
1083 device_remove_file(&mci->dev, &dev_attr_inject_data_error);
1084 device_remove_file(&mci->dev, &dev_attr_inject_data_poison);
1087 static void setup_row_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1089 u32 addrmap_row_b2_10;
1092 priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE;
1093 priv->row_shift[1] = ((addrmap[5] >> 8) &
1094 ROW_MAX_VAL_MASK) + ROW_B1_BASE;
1096 addrmap_row_b2_10 = (addrmap[5] >> 16) & ROW_MAX_VAL_MASK;
1097 if (addrmap_row_b2_10 != ROW_MAX_VAL_MASK) {
1098 for (index = 2; index < 11; index++)
1099 priv->row_shift[index] = addrmap_row_b2_10 +
1100 index + ROW_B0_BASE;
1103 priv->row_shift[2] = (addrmap[9] &
1104 ROW_MAX_VAL_MASK) + ROW_B2_BASE;
1105 priv->row_shift[3] = ((addrmap[9] >> 8) &
1106 ROW_MAX_VAL_MASK) + ROW_B3_BASE;
1107 priv->row_shift[4] = ((addrmap[9] >> 16) &
1108 ROW_MAX_VAL_MASK) + ROW_B4_BASE;
1109 priv->row_shift[5] = ((addrmap[9] >> 24) &
1110 ROW_MAX_VAL_MASK) + ROW_B5_BASE;
1111 priv->row_shift[6] = (addrmap[10] &
1112 ROW_MAX_VAL_MASK) + ROW_B6_BASE;
1113 priv->row_shift[7] = ((addrmap[10] >> 8) &
1114 ROW_MAX_VAL_MASK) + ROW_B7_BASE;
1115 priv->row_shift[8] = ((addrmap[10] >> 16) &
1116 ROW_MAX_VAL_MASK) + ROW_B8_BASE;
1117 priv->row_shift[9] = ((addrmap[10] >> 24) &
1118 ROW_MAX_VAL_MASK) + ROW_B9_BASE;
1119 priv->row_shift[10] = (addrmap[11] &
1120 ROW_MAX_VAL_MASK) + ROW_B10_BASE;
1123 priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) ==
1124 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[5] >> 24) &
1125 ROW_MAX_VAL_MASK) + ROW_B11_BASE);
1126 priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) ==
1127 ROW_MAX_VAL_MASK) ? 0 : ((addrmap[6] &
1128 ROW_MAX_VAL_MASK) + ROW_B12_BASE);
1129 priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) ==
1130 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 8) &
1131 ROW_MAX_VAL_MASK) + ROW_B13_BASE);
1132 priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) ==
1133 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 16) &
1134 ROW_MAX_VAL_MASK) + ROW_B14_BASE);
1135 priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) ==
1136 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 24) &
1137 ROW_MAX_VAL_MASK) + ROW_B15_BASE);
1138 priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) ==
1139 ROW_MAX_VAL_MASK) ? 0 : ((addrmap[7] &
1140 ROW_MAX_VAL_MASK) + ROW_B16_BASE);
1141 priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) ==
1142 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[7] >> 8) &
1143 ROW_MAX_VAL_MASK) + ROW_B17_BASE);
1146 static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1151 memtype = readl(priv->baseaddr + CTRL_OFST);
1152 width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
1154 priv->col_shift[0] = 0;
1155 priv->col_shift[1] = 1;
1156 priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE;
1157 priv->col_shift[3] = ((addrmap[2] >> 8) &
1158 COL_MAX_VAL_MASK) + COL_B3_BASE;
1159 priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) ==
1160 COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 16) &
1161 COL_MAX_VAL_MASK) + COL_B4_BASE);
1162 priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) ==
1163 COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 24) &
1164 COL_MAX_VAL_MASK) + COL_B5_BASE);
1165 priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) ==
1166 COL_MAX_VAL_MASK) ? 0 : ((addrmap[3] &
1167 COL_MAX_VAL_MASK) + COL_B6_BASE);
1168 priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) ==
1169 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 8) &
1170 COL_MAX_VAL_MASK) + COL_B7_BASE);
1171 priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) ==
1172 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 16) &
1173 COL_MAX_VAL_MASK) + COL_B8_BASE);
1174 priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) ==
1175 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 24) &
1176 COL_MAX_VAL_MASK) + COL_B9_BASE);
1177 if (width == DDRCTL_EWDTH_64) {
1178 if (memtype & MEM_TYPE_LPDDR3) {
1179 priv->col_shift[10] = ((addrmap[4] &
1180 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1181 ((addrmap[4] & COL_MAX_VAL_MASK) +
1183 priv->col_shift[11] = (((addrmap[4] >> 8) &
1184 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1185 (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
1188 priv->col_shift[11] = ((addrmap[4] &
1189 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1190 ((addrmap[4] & COL_MAX_VAL_MASK) +
1192 priv->col_shift[13] = (((addrmap[4] >> 8) &
1193 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1194 (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
1197 } else if (width == DDRCTL_EWDTH_32) {
1198 if (memtype & MEM_TYPE_LPDDR3) {
1199 priv->col_shift[10] = (((addrmap[3] >> 24) &
1200 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1201 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1203 priv->col_shift[11] = ((addrmap[4] &
1204 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1205 ((addrmap[4] & COL_MAX_VAL_MASK) +
1208 priv->col_shift[11] = (((addrmap[3] >> 24) &
1209 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1210 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1212 priv->col_shift[13] = ((addrmap[4] &
1213 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1214 ((addrmap[4] & COL_MAX_VAL_MASK) +
1218 if (memtype & MEM_TYPE_LPDDR3) {
1219 priv->col_shift[10] = (((addrmap[3] >> 16) &
1220 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1221 (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
1223 priv->col_shift[11] = (((addrmap[3] >> 24) &
1224 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1225 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1227 priv->col_shift[13] = ((addrmap[4] &
1228 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1229 ((addrmap[4] & COL_MAX_VAL_MASK) +
1232 priv->col_shift[11] = (((addrmap[3] >> 16) &
1233 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1234 (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
1236 priv->col_shift[13] = (((addrmap[3] >> 24) &
1237 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1238 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1244 for (index = 9; index > width; index--) {
1245 priv->col_shift[index] = priv->col_shift[index - width];
1246 priv->col_shift[index - width] = 0;
1252 static void setup_bank_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1254 priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE;
1255 priv->bank_shift[1] = ((addrmap[1] >> 8) &
1256 BANK_MAX_VAL_MASK) + BANK_B1_BASE;
1257 priv->bank_shift[2] = (((addrmap[1] >> 16) &
1258 BANK_MAX_VAL_MASK) == BANK_MAX_VAL_MASK) ? 0 :
1259 (((addrmap[1] >> 16) & BANK_MAX_VAL_MASK) +
1264 static void setup_bg_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1266 priv->bankgrp_shift[0] = (addrmap[8] &
1267 BANKGRP_MAX_VAL_MASK) + BANKGRP_B0_BASE;
1268 priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) ==
1269 BANKGRP_MAX_VAL_MASK) ? 0 : (((addrmap[8] >> 8)
1270 & BANKGRP_MAX_VAL_MASK) + BANKGRP_B1_BASE);
1274 static void setup_rank_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1276 priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) ==
1277 RANK_MAX_VAL_MASK) ? 0 : ((addrmap[0] &
1278 RANK_MAX_VAL_MASK) + RANK_B0_BASE);
1282 * setup_address_map - Set Address Map by querying ADDRMAP registers.
1283 * @priv: DDR memory controller private instance data.
1285 * Set Address Map by querying ADDRMAP registers.
1289 static void setup_address_map(struct synps_edac_priv *priv)
1294 for (index = 0; index < 12; index++) {
1297 addrmap_offset = ECC_ADDRMAP0_OFFSET + (index * 4);
1298 addrmap[index] = readl(priv->baseaddr + addrmap_offset);
1301 setup_row_address_map(priv, addrmap);
1303 setup_column_address_map(priv, addrmap);
1305 setup_bank_address_map(priv, addrmap);
1307 setup_bg_address_map(priv, addrmap);
1309 setup_rank_address_map(priv, addrmap);
1311 #endif /* CONFIG_EDAC_DEBUG */
1314 * mc_probe - Check controller and bind driver.
1315 * @pdev: platform device.
1317 * Probe a specific controller instance for binding with the driver.
1319 * Return: 0 if the controller instance was successfully bound to the
1320 * driver; otherwise, < 0 on error.
1322 static int mc_probe(struct platform_device *pdev)
1324 const struct synps_platform_data *p_data;
1325 struct edac_mc_layer layers[2];
1326 struct synps_edac_priv *priv;
1327 struct mem_ctl_info *mci;
1328 void __iomem *baseaddr;
1329 struct resource *res;
1332 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1333 baseaddr = devm_ioremap_resource(&pdev->dev, res);
1334 if (IS_ERR(baseaddr))
1335 return PTR_ERR(baseaddr);
1337 p_data = of_device_get_match_data(&pdev->dev);
1341 if (!p_data->get_ecc_state(baseaddr)) {
1342 edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n");
1346 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1347 layers[0].size = SYNPS_EDAC_NR_CSROWS;
1348 layers[0].is_virt_csrow = true;
1349 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1350 layers[1].size = SYNPS_EDAC_NR_CHANS;
1351 layers[1].is_virt_csrow = false;
1353 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
1354 sizeof(struct synps_edac_priv));
1356 edac_printk(KERN_ERR, EDAC_MC,
1357 "Failed memory allocation for mc instance\n");
1361 priv = mci->pvt_info;
1362 priv->baseaddr = baseaddr;
1363 priv->p_data = p_data;
1367 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
1368 rc = setup_irq(mci, pdev);
1373 rc = edac_mc_add_mc(mci);
1375 edac_printk(KERN_ERR, EDAC_MC,
1376 "Failed to register with EDAC core\n");
1380 #ifdef CONFIG_EDAC_DEBUG
1381 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) {
1382 rc = edac_create_sysfs_attributes(mci);
1384 edac_printk(KERN_ERR, EDAC_MC,
1385 "Failed to create sysfs entries\n");
1390 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
1391 setup_address_map(priv);
1395 * Start capturing the correctable and uncorrectable errors. A write of
1396 * 0 starts the counters.
1398 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT))
1399 writel(0x0, baseaddr + ECC_CTRL_OFST);
1410 * mc_remove - Unbind driver from controller.
1411 * @pdev: Platform device.
1413 * Return: Unconditionally 0
1415 static int mc_remove(struct platform_device *pdev)
1417 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
1418 struct synps_edac_priv *priv = mci->pvt_info;
1420 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
1423 #ifdef CONFIG_EDAC_DEBUG
1424 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT)
1425 edac_remove_sysfs_attributes(mci);
1428 edac_mc_del_mc(&pdev->dev);
1434 static struct platform_driver synps_edac_mc_driver = {
1436 .name = "synopsys-edac",
1437 .of_match_table = synps_edac_match,
1440 .remove = mc_remove,
1443 module_platform_driver(synps_edac_mc_driver);
1445 MODULE_AUTHOR("Xilinx Inc");
1446 MODULE_DESCRIPTION("Synopsys DDR ECC driver");
1447 MODULE_LICENSE("GPL v2");