1 // SPDX-License-Identifier: GPL-2.0
4 * Shared code by both skx_edac and i10nm_edac. Originally split out
5 * from the skx_edac driver.
7 * This file is linked into both skx_edac and i10nm_edac drivers. In
8 * order to avoid link errors, this file must be like a pure library
9 * without including symbols and defines which would otherwise conflict,
10 * when linked once into a module and into a built-in object, at the
11 * same time. For example, __this_module symbol references when that
12 * file is being linked into a built-in object.
14 * Copyright (c) 2018, Intel Corporation.
17 #include <linux/acpi.h>
18 #include <linux/dmi.h>
19 #include <linux/adxl.h>
20 #include <acpi/nfit.h>
22 #include "edac_module.h"
23 #include "skx_common.h"
25 static const char * const component_names[] = {
26 [INDEX_SOCKET] = "ProcessorSocketId",
27 [INDEX_MEMCTRL] = "MemoryControllerId",
28 [INDEX_CHANNEL] = "ChannelId",
29 [INDEX_DIMM] = "DimmSlotId",
30 [INDEX_NM_MEMCTRL] = "NmMemoryControllerId",
31 [INDEX_NM_CHANNEL] = "NmChannelId",
32 [INDEX_NM_DIMM] = "NmDimmSlotId",
35 static int component_indices[ARRAY_SIZE(component_names)];
36 static int adxl_component_count;
37 static const char * const *adxl_component_names;
38 static u64 *adxl_values;
39 static char *adxl_msg;
40 static unsigned long adxl_nm_bitmap;
42 static char skx_msg[MSG_SIZE];
43 static skx_decode_f skx_decode;
44 static skx_show_retry_log_f skx_show_retry_rd_err_log;
45 static u64 skx_tolm, skx_tohm;
46 static LIST_HEAD(dev_edac_list);
47 static bool skx_mem_cfg_2lm;
49 int __init skx_adxl_get(void)
51 const char * const *names;
54 names = adxl_get_component_names();
56 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
60 for (i = 0; i < INDEX_MAX; i++) {
61 for (j = 0; names[j]; j++) {
62 if (!strcmp(component_names[i], names[j])) {
63 component_indices[i] = j;
65 if (i >= INDEX_NM_FIRST)
66 adxl_nm_bitmap |= 1 << i;
72 if (!names[j] && i < INDEX_NM_FIRST)
76 if (skx_mem_cfg_2lm) {
78 skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n");
80 edac_dbg(2, "adxl_nm_bitmap: 0x%lx\n", adxl_nm_bitmap);
83 adxl_component_names = names;
85 adxl_component_count++;
87 adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
90 adxl_component_count = 0;
94 adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
96 adxl_component_count = 0;
103 skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
105 for (j = 0; names[j]; j++)
106 skx_printk(KERN_CONT, "%s ", names[j]);
107 skx_printk(KERN_CONT, "\n");
112 void __exit skx_adxl_put(void)
118 static bool skx_adxl_decode(struct decoded_addr *res, bool error_in_1st_level_mem)
123 if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
124 res->addr < BIT_ULL(32))) {
125 edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
129 if (adxl_decode(res->addr, adxl_values)) {
130 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
134 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]];
135 if (error_in_1st_level_mem) {
136 res->imc = (adxl_nm_bitmap & BIT_NM_MEMCTRL) ?
137 (int)adxl_values[component_indices[INDEX_NM_MEMCTRL]] : -1;
138 res->channel = (adxl_nm_bitmap & BIT_NM_CHANNEL) ?
139 (int)adxl_values[component_indices[INDEX_NM_CHANNEL]] : -1;
140 res->dimm = (adxl_nm_bitmap & BIT_NM_DIMM) ?
141 (int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1;
143 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
144 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
145 res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]];
148 if (res->imc > NUM_IMC - 1 || res->imc < 0) {
149 skx_printk(KERN_ERR, "Bad imc %d\n", res->imc);
153 list_for_each_entry(d, &dev_edac_list, list) {
154 if (d->imc[0].src_id == res->socket) {
161 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
162 res->socket, res->imc);
166 for (i = 0; i < adxl_component_count; i++) {
167 if (adxl_values[i] == ~0x0ull)
170 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
171 adxl_component_names[i], adxl_values[i]);
172 if (MSG_SIZE - len <= 0)
179 void skx_set_mem_cfg(bool mem_cfg_2lm)
181 skx_mem_cfg_2lm = mem_cfg_2lm;
184 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
187 skx_show_retry_rd_err_log = show_retry_log;
190 int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
194 if (pci_read_config_dword(d->util_all, off, ®)) {
195 skx_printk(KERN_ERR, "Failed to read src id\n");
199 *id = GET_BITFIELD(reg, 12, 14);
203 int skx_get_node_id(struct skx_dev *d, u8 *id)
207 if (pci_read_config_dword(d->util_all, 0xf4, ®)) {
208 skx_printk(KERN_ERR, "Failed to read node id\n");
212 *id = GET_BITFIELD(reg, 0, 2);
216 static int get_width(u32 mtr)
218 switch (GET_BITFIELD(mtr, 8, 9)) {
230 * We use the per-socket device @cfg->did to count how many sockets are present,
231 * and to detemine which PCI buses are associated with each socket. Allocate
232 * and build the full list of all the skx_dev structures that we need here.
234 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list)
236 struct pci_dev *pdev, *prev;
243 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev);
247 d = kzalloc(sizeof(*d), GFP_KERNEL);
253 if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, ®)) {
256 skx_printk(KERN_ERR, "Failed to read bus idx\n");
260 d->bus[0] = GET_BITFIELD(reg, 0, 7);
261 d->bus[1] = GET_BITFIELD(reg, 8, 15);
262 if (cfg->type == SKX) {
263 d->seg = pci_domain_nr(pdev->bus);
264 d->bus[2] = GET_BITFIELD(reg, 16, 23);
265 d->bus[3] = GET_BITFIELD(reg, 24, 31);
267 d->seg = GET_BITFIELD(reg, 16, 23);
270 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
271 d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
272 list_add_tail(&d->list, &dev_edac_list);
277 *list = &dev_edac_list;
281 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
283 struct pci_dev *pdev;
286 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
288 edac_dbg(2, "Can't get tolm/tohm\n");
292 if (pci_read_config_dword(pdev, off[0], ®)) {
293 skx_printk(KERN_ERR, "Failed to read tolm\n");
298 if (pci_read_config_dword(pdev, off[1], ®)) {
299 skx_printk(KERN_ERR, "Failed to read lower tohm\n");
304 if (pci_read_config_dword(pdev, off[2], ®)) {
305 skx_printk(KERN_ERR, "Failed to read upper tohm\n");
308 skx_tohm |= (u64)reg << 32;
313 edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
320 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
321 int minval, int maxval, const char *name)
323 u32 val = GET_BITFIELD(reg, lobit, hibit);
325 if (val < minval || val > maxval) {
326 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
332 #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
333 #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
334 #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
336 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
337 struct skx_imc *imc, int chan, int dimmno,
338 struct res_config *cfg)
340 int banks, ranks, rows, cols, npages;
344 ranks = numrank(mtr);
346 cols = imc->hbm_mc ? 6 : numcol(mtr);
348 if (cfg->support_ddr5 && ((amap & 0x8) || imc->hbm_mc)) {
357 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
359 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
360 npages = MiB_TO_PAGES(size);
362 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
363 imc->mc, chan, dimmno, size, npages,
364 banks, 1 << ranks, rows, cols);
366 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0);
367 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9);
368 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
369 imc->chan[chan].dimms[dimmno].rowbits = rows;
370 imc->chan[chan].dimms[dimmno].colbits = cols;
372 dimm->nr_pages = npages;
374 dimm->dtype = get_width(mtr);
376 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
379 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u",
380 imc->src_id, imc->lmc, chan);
382 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
383 imc->src_id, imc->lmc, chan, dimmno);
388 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
389 int chan, int dimmno, const char *mod_str)
396 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
399 smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
400 if (smbios_handle == -EOPNOTSUPP) {
401 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
405 if (smbios_handle < 0) {
406 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
410 if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
411 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
415 size = dmi_memdev_size(smbios_handle);
417 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
418 dev_handle, smbios_handle);
421 dimm->nr_pages = size >> PAGE_SHIFT;
423 dimm->dtype = DEV_UNKNOWN;
424 dimm->mtype = MEM_NVDIMM;
425 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
427 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
428 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
430 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
431 imc->src_id, imc->lmc, chan, dimmno);
433 return (size == 0 || size == ~0ull) ? 0 : 1;
436 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
437 const char *ctl_name, const char *mod_str,
438 get_dimm_config_f get_dimm_config,
439 struct res_config *cfg)
441 struct mem_ctl_info *mci;
442 struct edac_mc_layer layers[2];
446 /* Allocate a new MC control structure */
447 layers[0].type = EDAC_MC_LAYER_CHANNEL;
448 layers[0].size = NUM_CHANNELS;
449 layers[0].is_virt_csrow = false;
450 layers[1].type = EDAC_MC_LAYER_SLOT;
451 layers[1].size = NUM_DIMMS;
452 layers[1].is_virt_csrow = true;
453 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
454 sizeof(struct skx_pvt));
459 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
461 /* Associate skx_dev and mci for future usage */
466 mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
467 imc->node_id, imc->lmc);
468 if (!mci->ctl_name) {
473 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
474 if (cfg->support_ddr5)
475 mci->mtype_cap |= MEM_FLAG_DDR5;
476 mci->edac_ctl_cap = EDAC_FLAG_NONE;
477 mci->edac_cap = EDAC_FLAG_NONE;
478 mci->mod_name = mod_str;
479 mci->dev_name = pci_name(pdev);
480 mci->ctl_page_to_phys = NULL;
482 rc = get_dimm_config(mci, cfg);
486 /* Record ptr to the generic device */
487 mci->pdev = &pdev->dev;
489 /* Add this new MC control structure to EDAC's list of MCs */
490 if (unlikely(edac_mc_add_mc(mci))) {
491 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
499 kfree(mci->ctl_name);
506 static void skx_unregister_mci(struct skx_imc *imc)
508 struct mem_ctl_info *mci = imc->mci;
513 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
515 /* Remove MC sysfs nodes */
516 edac_mc_del_mc(mci->pdev);
518 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
519 kfree(mci->ctl_name);
523 static void skx_mce_output_error(struct mem_ctl_info *mci,
525 struct decoded_addr *res)
527 enum hw_event_mc_err_type tp_event;
529 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
530 bool overflow = GET_BITFIELD(m->status, 62, 62);
531 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
534 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
535 u32 mscod = GET_BITFIELD(m->status, 16, 31);
536 u32 errcode = GET_BITFIELD(m->status, 0, 15);
537 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
539 recoverable = GET_BITFIELD(m->status, 56, 56);
541 if (uncorrected_error) {
544 tp_event = HW_EVENT_ERR_UNCORRECTED;
546 tp_event = HW_EVENT_ERR_FATAL;
549 tp_event = HW_EVENT_ERR_CORRECTED;
553 * According to Intel Architecture spec vol 3B,
554 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
555 * memory errors should fit one of these masks:
556 * 000f 0000 1mmm cccc (binary)
557 * 000f 0010 1mmm cccc (binary) [RAM used as cache]
559 * f = Correction Report Filtering Bit. If 1, subsequent errors
563 * If the mask doesn't match, report an error to the parsing logic
565 if (!((errcode & 0xef80) == 0x80 || (errcode & 0xef80) == 0x280)) {
566 optype = "Can't parse: it is not a mem";
570 optype = "generic undef request error";
573 optype = "memory read error";
576 optype = "memory write error";
579 optype = "addr/cmd error";
582 optype = "memory scrubbing error";
589 if (adxl_component_count) {
590 len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
591 overflow ? " OVERFLOW" : "",
592 (uncorrected_error && recoverable) ? " recoverable" : "",
593 mscod, errcode, adxl_msg);
595 len = snprintf(skx_msg, MSG_SIZE,
596 "%s%s err_code:0x%04x:0x%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:0x%x col:0x%x",
597 overflow ? " OVERFLOW" : "",
598 (uncorrected_error && recoverable) ? " recoverable" : "",
600 res->socket, res->imc, res->rank,
601 res->bank_group, res->bank_address, res->row, res->column);
604 if (skx_show_retry_rd_err_log)
605 skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len);
607 edac_dbg(0, "%s\n", skx_msg);
609 /* Call the helper to output message */
610 edac_mc_handle_error(tp_event, mci, core_err_cnt,
611 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
612 res->channel, res->dimm, -1,
616 static bool skx_error_in_1st_level_mem(const struct mce *m)
620 if (!skx_mem_cfg_2lm)
623 errcode = GET_BITFIELD(m->status, 0, 15);
625 if ((errcode & 0xef80) != 0x280)
631 int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
634 struct mce *mce = (struct mce *)data;
635 struct decoded_addr res;
636 struct mem_ctl_info *mci;
639 if (mce->kflags & MCE_HANDLED_CEC)
642 /* ignore unless this is memory related with an address */
643 if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV))
646 memset(&res, 0, sizeof(res));
647 res.addr = mce->addr;
649 if (adxl_component_count) {
650 if (!skx_adxl_decode(&res, skx_error_in_1st_level_mem(mce)))
652 } else if (!skx_decode || !skx_decode(&res)) {
656 mci = res.dev->imc[res.imc].mci;
661 if (mce->mcgstatus & MCG_STATUS_MCIP)
666 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
668 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
669 "Bank %d: 0x%llx\n", mce->extcpu, type,
670 mce->mcgstatus, mce->bank, mce->status);
671 skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
672 skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
673 skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
675 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
676 "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
677 mce->time, mce->socketid, mce->apicid);
679 skx_mce_output_error(mci, mce, &res);
681 mce->kflags |= MCE_HANDLED_EDAC;
685 void skx_remove(void)
688 struct skx_dev *d, *tmp;
692 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
694 for (i = 0; i < NUM_IMC; i++) {
696 skx_unregister_mci(&d->imc[i]);
699 pci_dev_put(d->imc[i].mdev);
702 iounmap(d->imc[i].mbase);
704 for (j = 0; j < NUM_CHANNELS; j++) {
705 if (d->imc[i].chan[j].cdev)
706 pci_dev_put(d->imc[i].chan[j].cdev);
710 pci_dev_put(d->util_all);
712 pci_dev_put(d->pcu_cr3);
714 pci_dev_put(d->sad_all);
716 pci_dev_put(d->uracu);