drivers/edac/sb_edac.c

   1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
   2  *
   3  * This driver supports the memory controllers found on the Intel
   4  * processor family Sandy Bridge.
   5  *
   6  * This file may be distributed under the terms of the
   7  * GNU General Public License version 2 only.
   8  *
   9  * Copyright (c) 2011 by:
  10  *       Mauro Carvalho Chehab
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci_ids.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/edac.h>
  20 #include <linux/mmzone.h>
  21 #include <linux/smp.h>
  22 #include <linux/bitmap.h>
  23 #include <linux/math64.h>
  24 #include <linux/mod_devicetable.h>
  25 #include <asm/cpu_device_id.h>
  26 #include <asm/intel-family.h>
  27 #include <asm/processor.h>
  28 #include <asm/mce.h>
  29
  30 #include "edac_module.h"
  31
  32 /* Static vars */
  33 static LIST_HEAD(sbridge_edac_list);
  34
  35 /*
  36  * Alter this version for the module when modifications are made
  37  */
  38 #define SBRIDGE_REVISION    " Ver: 1.1.2 "
  39 #define EDAC_MOD_STR        "sb_edac"
  40
  41 /*
  42  * Debug macros
  43  */
  44 #define sbridge_printk(level, fmt, arg...)                      \
  45         edac_printk(level, "sbridge", fmt, ##arg)
  46
  47 #define sbridge_mc_printk(mci, level, fmt, arg...)              \
  48         edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
  49
  50 /*
  51  * Get a bit field at register value <v>, from bit <lo> to bit <hi>
  52  */
  53 #define GET_BITFIELD(v, lo, hi) \
  54         (((v) & GENMASK_ULL(hi, lo)) >> (lo))
  55
  56 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
  57 static const u32 sbridge_dram_rule[] = {
  58         0x80, 0x88, 0x90, 0x98, 0xa0,
  59         0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
  60 };
  61
  62 static const u32 ibridge_dram_rule[] = {
  63         0x60, 0x68, 0x70, 0x78, 0x80,
  64         0x88, 0x90, 0x98, 0xa0, 0xa8,
  65         0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
  66         0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
  67 };
  68
  69 static const u32 knl_dram_rule[] = {
  70         0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
  71         0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
  72         0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
  73         0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
  74         0x100, 0x108, 0x110, 0x118,   /* 20-23 */
  75 };
  76
  77 #define DRAM_RULE_ENABLE(reg)   GET_BITFIELD(reg, 0,  0)
  78 #define A7MODE(reg)             GET_BITFIELD(reg, 26, 26)
  79
  80 static char *show_dram_attr(u32 attr)
  81 {
  82         switch (attr) {
  83                 case 0:
  84                         return "DRAM";
  85                 case 1:
  86                         return "MMCFG";
  87                 case 2:
  88                         return "NXM";
  89                 default:
  90                         return "unknown";
  91         }
  92 }
  93
  94 static const u32 sbridge_interleave_list[] = {
  95         0x84, 0x8c, 0x94, 0x9c, 0xa4,
  96         0xac, 0xb4, 0xbc, 0xc4, 0xcc,
  97 };
  98
  99 static const u32 ibridge_interleave_list[] = {
 100         0x64, 0x6c, 0x74, 0x7c, 0x84,
 101         0x8c, 0x94, 0x9c, 0xa4, 0xac,
 102         0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
 103         0xdc, 0xe4, 0xec, 0xf4, 0xfc,
 104 };
 105
 106 static const u32 knl_interleave_list[] = {
 107         0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
 108         0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
 109         0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
 110         0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
 111         0x104, 0x10c, 0x114, 0x11c,   /* 20-23 */
 112 };
 113 #define MAX_INTERLEAVE                                                  \
 114         (max_t(unsigned int, ARRAY_SIZE(sbridge_interleave_list),       \
 115                max_t(unsigned int, ARRAY_SIZE(ibridge_interleave_list), \
 116                      ARRAY_SIZE(knl_interleave_list))))
 117
 118 struct interleave_pkg {
 119         unsigned char start;
 120         unsigned char end;
 121 };
 122
 123 static const struct interleave_pkg sbridge_interleave_pkg[] = {
 124         { 0, 2 },
 125         { 3, 5 },
 126         { 8, 10 },
 127         { 11, 13 },
 128         { 16, 18 },
 129         { 19, 21 },
 130         { 24, 26 },
 131         { 27, 29 },
 132 };
 133
 134 static const struct interleave_pkg ibridge_interleave_pkg[] = {
 135         { 0, 3 },
 136         { 4, 7 },
 137         { 8, 11 },
 138         { 12, 15 },
 139         { 16, 19 },
 140         { 20, 23 },
 141         { 24, 27 },
 142         { 28, 31 },
 143 };
 144
 145 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
 146                           int interleave)
 147 {
 148         return GET_BITFIELD(reg, table[interleave].start,
 149                             table[interleave].end);
 150 }
 151
 152 /* Devices 12 Function 7 */
 153
 154 #define TOLM            0x80
 155 #define TOHM            0x84
 156 #define HASWELL_TOLM    0xd0
 157 #define HASWELL_TOHM_0  0xd4
 158 #define HASWELL_TOHM_1  0xd8
 159 #define KNL_TOLM        0xd0
 160 #define KNL_TOHM_0      0xd4
 161 #define KNL_TOHM_1      0xd8
 162
 163 #define GET_TOLM(reg)           ((GET_BITFIELD(reg, 0,  3) << 28) | 0x3ffffff)
 164 #define GET_TOHM(reg)           ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
 165
 166 /* Device 13 Function 6 */
 167
 168 #define SAD_TARGET      0xf0
 169
 170 #define SOURCE_ID(reg)          GET_BITFIELD(reg, 9, 11)
 171
 172 #define SOURCE_ID_KNL(reg)      GET_BITFIELD(reg, 12, 14)
 173
 174 #define SAD_CONTROL     0xf4
 175
 176 /* Device 14 function 0 */
 177
 178 static const u32 tad_dram_rule[] = {
 179         0x40, 0x44, 0x48, 0x4c,
 180         0x50, 0x54, 0x58, 0x5c,
 181         0x60, 0x64, 0x68, 0x6c,
 182 };
 183 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
 184
 185 #define TAD_LIMIT(reg)          ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
 186 #define TAD_SOCK(reg)           GET_BITFIELD(reg, 10, 11)
 187 #define TAD_CH(reg)             GET_BITFIELD(reg,  8,  9)
 188 #define TAD_TGT3(reg)           GET_BITFIELD(reg,  6,  7)
 189 #define TAD_TGT2(reg)           GET_BITFIELD(reg,  4,  5)
 190 #define TAD_TGT1(reg)           GET_BITFIELD(reg,  2,  3)
 191 #define TAD_TGT0(reg)           GET_BITFIELD(reg,  0,  1)
 192
 193 /* Device 15, function 0 */
 194
 195 #define MCMTR                   0x7c
 196 #define KNL_MCMTR               0x624
 197
 198 #define IS_ECC_ENABLED(mcmtr)           GET_BITFIELD(mcmtr, 2, 2)
 199 #define IS_LOCKSTEP_ENABLED(mcmtr)      GET_BITFIELD(mcmtr, 1, 1)
 200 #define IS_CLOSE_PG(mcmtr)              GET_BITFIELD(mcmtr, 0, 0)
 201
 202 /* Device 15, function 1 */
 203
 204 #define RASENABLES              0xac
 205 #define IS_MIRROR_ENABLED(reg)          GET_BITFIELD(reg, 0, 0)
 206
 207 /* Device 15, functions 2-5 */
 208
 209 static const int mtr_regs[] = {
 210         0x80, 0x84, 0x88,
 211 };
 212
 213 static const int knl_mtr_reg = 0xb60;
 214
 215 #define RANK_DISABLE(mtr)               GET_BITFIELD(mtr, 16, 19)
 216 #define IS_DIMM_PRESENT(mtr)            GET_BITFIELD(mtr, 14, 14)
 217 #define RANK_CNT_BITS(mtr)              GET_BITFIELD(mtr, 12, 13)
 218 #define RANK_WIDTH_BITS(mtr)            GET_BITFIELD(mtr, 2, 4)
 219 #define COL_WIDTH_BITS(mtr)             GET_BITFIELD(mtr, 0, 1)
 220
 221 static const u32 tad_ch_nilv_offset[] = {
 222         0x90, 0x94, 0x98, 0x9c,
 223         0xa0, 0xa4, 0xa8, 0xac,
 224         0xb0, 0xb4, 0xb8, 0xbc,
 225 };
 226 #define CHN_IDX_OFFSET(reg)             GET_BITFIELD(reg, 28, 29)
 227 #define TAD_OFFSET(reg)                 (GET_BITFIELD(reg,  6, 25) << 26)
 228
 229 static const u32 rir_way_limit[] = {
 230         0x108, 0x10c, 0x110, 0x114, 0x118,
 231 };
 232 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
 233
 234 #define IS_RIR_VALID(reg)       GET_BITFIELD(reg, 31, 31)
 235 #define RIR_WAY(reg)            GET_BITFIELD(reg, 28, 29)
 236
 237 #define MAX_RIR_WAY     8
 238
 239 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
 240         { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
 241         { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
 242         { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
 243         { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
 244         { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
 245 };
 246
 247 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
 248         GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
 249
 250 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
 251         GET_BITFIELD(reg,  2, 15) : GET_BITFIELD(reg,  2, 14))
 252
 253 /* Device 16, functions 2-7 */
 254
 255 /*
 256  * FIXME: Implement the error count reads directly
 257  */
 258
 259 static const u32 correrrcnt[] = {
 260         0x104, 0x108, 0x10c, 0x110,
 261 };
 262
 263 #define RANK_ODD_OV(reg)                GET_BITFIELD(reg, 31, 31)
 264 #define RANK_ODD_ERR_CNT(reg)           GET_BITFIELD(reg, 16, 30)
 265 #define RANK_EVEN_OV(reg)               GET_BITFIELD(reg, 15, 15)
 266 #define RANK_EVEN_ERR_CNT(reg)          GET_BITFIELD(reg,  0, 14)
 267
 268 static const u32 correrrthrsld[] = {
 269         0x11c, 0x120, 0x124, 0x128,
 270 };
 271
 272 #define RANK_ODD_ERR_THRSLD(reg)        GET_BITFIELD(reg, 16, 30)
 273 #define RANK_EVEN_ERR_THRSLD(reg)       GET_BITFIELD(reg,  0, 14)
 274
 275
 276 /* Device 17, function 0 */
 277
 278 #define SB_RANK_CFG_A           0x0328
 279
 280 #define IB_RANK_CFG_A           0x0320
 281
 282 /*
 283  * sbridge structs
 284  */
 285
 286 #define NUM_CHANNELS            6       /* Max channels per MC */
 287 #define MAX_DIMMS               3       /* Max DIMMS per channel */
 288 #define KNL_MAX_CHAS            38      /* KNL max num. of Cache Home Agents */
 289 #define KNL_MAX_CHANNELS        6       /* KNL max num. of PCI channels */
 290 #define KNL_MAX_EDCS            8       /* Embedded DRAM controllers */
 291 #define CHANNEL_UNSPECIFIED     0xf     /* Intel IA32 SDM 15-14 */
 292
 293 enum type {
 294         SANDY_BRIDGE,
 295         IVY_BRIDGE,
 296         HASWELL,
 297         BROADWELL,
 298         KNIGHTS_LANDING,
 299 };
 300
 301 enum domain {
 302         IMC0 = 0,
 303         IMC1,
 304         SOCK,
 305 };
 306
 307 enum mirroring_mode {
 308         NON_MIRRORING,
 309         ADDR_RANGE_MIRRORING,
 310         FULL_MIRRORING,
 311 };
 312
 313 struct sbridge_pvt;
 314 struct sbridge_info {
 315         enum type       type;
 316         u32             mcmtr;
 317         u32             rankcfgr;
 318         u64             (*get_tolm)(struct sbridge_pvt *pvt);
 319         u64             (*get_tohm)(struct sbridge_pvt *pvt);
 320         u64             (*rir_limit)(u32 reg);
 321         u64             (*sad_limit)(u32 reg);
 322         u32             (*interleave_mode)(u32 reg);
 323         u32             (*dram_attr)(u32 reg);
 324         const u32       *dram_rule;
 325         const u32       *interleave_list;
 326         const struct interleave_pkg *interleave_pkg;
 327         u8              max_sad;
 328         u8              (*get_node_id)(struct sbridge_pvt *pvt);
 329         u8              (*get_ha)(u8 bank);
 330         enum mem_type   (*get_memory_type)(struct sbridge_pvt *pvt);
 331         enum dev_type   (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
 332         struct pci_dev  *pci_vtd;
 333 };
 334
 335 struct sbridge_channel {
 336         u32             ranks;
 337         u32             dimms;
 338 };
 339
 340 struct pci_id_descr {
 341         int                     dev_id;
 342         int                     optional;
 343         enum domain             dom;
 344 };
 345
 346 struct pci_id_table {
 347         const struct pci_id_descr       *descr;
 348         int                             n_devs_per_imc;
 349         int                             n_devs_per_sock;
 350         int                             n_imcs_per_sock;
 351         enum type                       type;
 352 };
 353
 354 struct sbridge_dev {
 355         struct list_head        list;
 356         int                     seg;
 357         u8                      bus, mc;
 358         u8                      node_id, source_id;
 359         struct pci_dev          **pdev;
 360         enum domain             dom;
 361         int                     n_devs;
 362         int                     i_devs;
 363         struct mem_ctl_info     *mci;
 364 };
 365
 366 struct knl_pvt {
 367         struct pci_dev          *pci_cha[KNL_MAX_CHAS];
 368         struct pci_dev          *pci_channel[KNL_MAX_CHANNELS];
 369         struct pci_dev          *pci_mc0;
 370         struct pci_dev          *pci_mc1;
 371         struct pci_dev          *pci_mc0_misc;
 372         struct pci_dev          *pci_mc1_misc;
 373         struct pci_dev          *pci_mc_info; /* tolm, tohm */
 374 };
 375
 376 struct sbridge_pvt {
 377         /* Devices per socket */
 378         struct pci_dev          *pci_ddrio;
 379         struct pci_dev          *pci_sad0, *pci_sad1;
 380         struct pci_dev          *pci_br0, *pci_br1;
 381         /* Devices per memory controller */
 382         struct pci_dev          *pci_ha, *pci_ta, *pci_ras;
 383         struct pci_dev          *pci_tad[NUM_CHANNELS];
 384
 385         struct sbridge_dev      *sbridge_dev;
 386
 387         struct sbridge_info     info;
 388         struct sbridge_channel  channel[NUM_CHANNELS];
 389
 390         /* Memory type detection */
 391         bool                    is_cur_addr_mirrored, is_lockstep, is_close_pg;
 392         bool                    is_chan_hash;
 393         enum mirroring_mode     mirror_mode;
 394
 395         /* Memory description */
 396         u64                     tolm, tohm;
 397         struct knl_pvt knl;
 398 };
 399
 400 #define PCI_DESCR(device_id, opt, domain)       \
 401         .dev_id = (device_id),          \
 402         .optional = opt,        \
 403         .dom = domain
 404
 405 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
 406                 /* Processor Home Agent */
 407         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0,   0, IMC0) },
 408
 409                 /* Memory controller */
 410         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA,    0, IMC0) },
 411         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS,   0, IMC0) },
 412         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0,  0, IMC0) },
 413         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1,  0, IMC0) },
 414         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2,  0, IMC0) },
 415         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3,  0, IMC0) },
 416         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1, SOCK) },
 417
 418                 /* System Address Decoder */
 419         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0,      0, SOCK) },
 420         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1,      0, SOCK) },
 421
 422                 /* Broadcast Registers */
 423         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR,        0, SOCK) },
 424 };
 425
 426 #define PCI_ID_TABLE_ENTRY(A, N, M, T) {        \
 427         .descr = A,                     \
 428         .n_devs_per_imc = N,    \
 429         .n_devs_per_sock = ARRAY_SIZE(A),       \
 430         .n_imcs_per_sock = M,   \
 431         .type = T                       \
 432 }
 433
 434 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
 435         PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE),
 436         {0,}                    /* 0 terminated list. */
 437 };
 438
 439 /* This changes depending if 1HA or 2HA:
 440  * 1HA:
 441  *      0x0eb8 (17.0) is DDRIO0
 442  * 2HA:
 443  *      0x0ebc (17.4) is DDRIO0
 444  */
 445 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0      0x0eb8
 446 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0      0x0ebc
 447
 448 /* pci ids */
 449 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0             0x0ea0
 450 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA          0x0ea8
 451 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS         0x0e71
 452 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0        0x0eaa
 453 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1        0x0eab
 454 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2        0x0eac
 455 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3        0x0ead
 456 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD                 0x0ec8
 457 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0                 0x0ec9
 458 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1                 0x0eca
 459 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1             0x0e60
 460 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA          0x0e68
 461 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS         0x0e79
 462 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0        0x0e6a
 463 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1        0x0e6b
 464 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2        0x0e6c
 465 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3        0x0e6d
 466
 467 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
 468                 /* Processor Home Agent */
 469         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0,        0, IMC0) },
 470         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1,        1, IMC1) },
 471
 472                 /* Memory controller */
 473         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA,     0, IMC0) },
 474         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS,    0, IMC0) },
 475         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0,   0, IMC0) },
 476         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1,   0, IMC0) },
 477         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2,   0, IMC0) },
 478         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3,   0, IMC0) },
 479
 480                 /* Optional, mode 2HA */
 481         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA,     1, IMC1) },
 482         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS,    1, IMC1) },
 483         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0,   1, IMC1) },
 484         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1,   1, IMC1) },
 485         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2,   1, IMC1) },
 486         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3,   1, IMC1) },
 487
 488         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1, SOCK) },
 489         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1, SOCK) },
 490
 491                 /* System Address Decoder */
 492         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD,            0, SOCK) },
 493
 494                 /* Broadcast Registers */
 495         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0,            1, SOCK) },
 496         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1,            0, SOCK) },
 497
 498 };
 499
 500 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
 501         PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE),
 502         {0,}                    /* 0 terminated list. */
 503 };
 504
 505 /* Haswell support */
 506 /* EN processor:
 507  *      - 1 IMC
 508  *      - 3 DDR3 channels, 2 DPC per channel
 509  * EP processor:
 510  *      - 1 or 2 IMC
 511  *      - 4 DDR4 channels, 3 DPC per channel
 512  * EP 4S processor:
 513  *      - 2 IMC
 514  *      - 4 DDR4 channels, 3 DPC per channel
 515  * EX processor:
 516  *      - 2 IMC
 517  *      - each IMC interfaces with a SMI 2 channel
 518  *      - each SMI channel interfaces with a scalable memory buffer
 519  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 520  */
 521 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
 522 #define HASWELL_HASYSDEFEATURE2 0x84
 523 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
 524 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0     0x2fa0
 525 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1     0x2f60
 526 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA  0x2fa8
 527 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM  0x2f71
 528 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA  0x2f68
 529 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM  0x2f79
 530 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
 531 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
 532 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
 533 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
 534 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
 535 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
 536 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
 537 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
 538 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
 539 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
 540 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
 541 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
 542 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
 543 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
 544 static const struct pci_id_descr pci_dev_descr_haswell[] = {
 545         /* first item must be the HA */
 546         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0,      0, IMC0) },
 547         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1,      1, IMC1) },
 548
 549         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA,   0, IMC0) },
 550         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM,   0, IMC0) },
 551         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0, IMC0) },
 552         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0, IMC0) },
 553         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1, IMC0) },
 554         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1, IMC0) },
 555
 556         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA,   1, IMC1) },
 557         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM,   1, IMC1) },
 558         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1, IMC1) },
 559         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1, IMC1) },
 560         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1, IMC1) },
 561         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1, IMC1) },
 562
 563         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0, SOCK) },
 564         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0, SOCK) },
 565         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0,   1, SOCK) },
 566         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1,   1, SOCK) },
 567         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2,   1, SOCK) },
 568         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3,   1, SOCK) },
 569 };
 570
 571 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
 572         PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL),
 573         {0,}                    /* 0 terminated list. */
 574 };
 575
 576 /* Knight's Landing Support */
 577 /*
 578  * KNL's memory channels are swizzled between memory controllers.
 579  * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2
 580  */
 581 #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3)
 582
 583 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
 584 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC       0x7840
 585 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
 586 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN     0x7843
 587 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
 588 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA       0x7844
 589 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
 590 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0     0x782a
 591 /* SAD target - 1-29-1 (1 of these) */
 592 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1     0x782b
 593 /* Caching / Home Agent */
 594 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA      0x782c
 595 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
 596 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM    0x7810
 597
 598 /*
 599  * KNL differs from SB, IB, and Haswell in that it has multiple
 600  * instances of the same device with the same device ID, so we handle that
 601  * by creating as many copies in the table as we expect to find.
 602  * (Like device ID must be grouped together.)
 603  */
 604
 605 static const struct pci_id_descr pci_dev_descr_knl[] = {
 606         [0 ... 1]   = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC,    0, IMC0)},
 607         [2 ... 7]   = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN,  0, IMC0) },
 608         [8]         = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA,    0, IMC0) },
 609         [9]         = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0, IMC0) },
 610         [10]        = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0,  0, SOCK) },
 611         [11]        = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1,  0, SOCK) },
 612         [12 ... 49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA,   0, SOCK) },
 613 };
 614
 615 static const struct pci_id_table pci_dev_descr_knl_table[] = {
 616         PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING),
 617         {0,}
 618 };
 619
 620 /*
 621  * Broadwell support
 622  *
 623  * DE processor:
 624  *      - 1 IMC
 625  *      - 2 DDR3 channels, 2 DPC per channel
 626  * EP processor:
 627  *      - 1 or 2 IMC
 628  *      - 4 DDR4 channels, 3 DPC per channel
 629  * EP 4S processor:
 630  *      - 2 IMC
 631  *      - 4 DDR4 channels, 3 DPC per channel
 632  * EX processor:
 633  *      - 2 IMC
 634  *      - each IMC interfaces with a SMI 2 channel
 635  *      - each SMI channel interfaces with a scalable memory buffer
 636  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 637  */
 638 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
 639 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0   0x6fa0
 640 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1   0x6f60
 641 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA        0x6fa8
 642 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM        0x6f71
 643 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA        0x6f68
 644 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM        0x6f79
 645 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
 646 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
 647 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
 648 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
 649 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
 650 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
 651 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
 652 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
 653 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
 654 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
 655 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
 656
 657 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
 658         /* first item must be the HA */
 659         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0,      0, IMC0) },
 660         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1,      1, IMC1) },
 661
 662         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA,   0, IMC0) },
 663         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM,   0, IMC0) },
 664         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0, IMC0) },
 665         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0, IMC0) },
 666         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1, IMC0) },
 667         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1, IMC0) },
 668
 669         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA,   1, IMC1) },
 670         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM,   1, IMC1) },
 671         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1, IMC1) },
 672         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1, IMC1) },
 673         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1, IMC1) },
 674         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1, IMC1) },
 675
 676         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0, SOCK) },
 677         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0, SOCK) },
 678         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0,   1, SOCK) },
 679 };
 680
 681 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
 682         PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL),
 683         {0,}                    /* 0 terminated list. */
 684 };
 685
 686
 687 /****************************************************************************
 688                         Ancillary status routines
 689  ****************************************************************************/
 690
 691 static inline int numrank(enum type type, u32 mtr)
 692 {
 693         int ranks = (1 << RANK_CNT_BITS(mtr));
 694         int max = 4;
 695
 696         if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)
 697                 max = 8;
 698
 699         if (ranks > max) {
 700                 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
 701                          ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
 702                 return -EINVAL;
 703         }
 704
 705         return ranks;
 706 }
 707
 708 static inline int numrow(u32 mtr)
 709 {
 710         int rows = (RANK_WIDTH_BITS(mtr) + 12);
 711
 712         if (rows < 13 || rows > 18) {
 713                 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
 714                          rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
 715                 return -EINVAL;
 716         }
 717
 718         return 1 << rows;
 719 }
 720
 721 static inline int numcol(u32 mtr)
 722 {
 723         int cols = (COL_WIDTH_BITS(mtr) + 10);
 724
 725         if (cols > 12) {
 726                 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
 727                          cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
 728                 return -EINVAL;
 729         }
 730
 731         return 1 << cols;
 732 }
 733
 734 static struct sbridge_dev *get_sbridge_dev(int seg, u8 bus, enum domain dom,
 735                                            int multi_bus,
 736                                            struct sbridge_dev *prev)
 737 {
 738         struct sbridge_dev *sbridge_dev;
 739
 740         /*
 741          * If we have devices scattered across several busses that pertain
 742          * to the same memory controller, we'll lump them all together.
 743          */
 744         if (multi_bus) {
 745                 return list_first_entry_or_null(&sbridge_edac_list,
 746                                 struct sbridge_dev, list);
 747         }
 748
 749         sbridge_dev = list_entry(prev ? prev->list.next
 750                                       : sbridge_edac_list.next, struct sbridge_dev, list);
 751
 752         list_for_each_entry_from(sbridge_dev, &sbridge_edac_list, list) {
 753                 if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) &&
 754                                 (dom == SOCK || dom == sbridge_dev->dom))
 755                         return sbridge_dev;
 756         }
 757
 758         return NULL;
 759 }
 760
 761 static struct sbridge_dev *alloc_sbridge_dev(int seg, u8 bus, enum domain dom,
 762                                              const struct pci_id_table *table)
 763 {
 764         struct sbridge_dev *sbridge_dev;
 765
 766         sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
 767         if (!sbridge_dev)
 768                 return NULL;
 769
 770         sbridge_dev->pdev = kcalloc(table->n_devs_per_imc,
 771                                     sizeof(*sbridge_dev->pdev),
 772                                     GFP_KERNEL);
 773         if (!sbridge_dev->pdev) {
 774                 kfree(sbridge_dev);
 775                 return NULL;
 776         }
 777
 778         sbridge_dev->seg = seg;
 779         sbridge_dev->bus = bus;
 780         sbridge_dev->dom = dom;
 781         sbridge_dev->n_devs = table->n_devs_per_imc;
 782         list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
 783
 784         return sbridge_dev;
 785 }
 786
 787 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
 788 {
 789         list_del(&sbridge_dev->list);
 790         kfree(sbridge_dev->pdev);
 791         kfree(sbridge_dev);
 792 }
 793
 794 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
 795 {
 796         u32 reg;
 797
 798         /* Address range is 32:28 */
 799         pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
 800         return GET_TOLM(reg);
 801 }
 802
 803 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
 804 {
 805         u32 reg;
 806
 807         pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
 808         return GET_TOHM(reg);
 809 }
 810
 811 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
 812 {
 813         u32 reg;
 814
 815         pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
 816
 817         return GET_TOLM(reg);
 818 }
 819
 820 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
 821 {
 822         u32 reg;
 823
 824         pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
 825
 826         return GET_TOHM(reg);
 827 }
 828
 829 static u64 rir_limit(u32 reg)
 830 {
 831         return ((u64)GET_BITFIELD(reg,  1, 10) << 29) | 0x1fffffff;
 832 }
 833
 834 static u64 sad_limit(u32 reg)
 835 {
 836         return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
 837 }
 838
 839 static u32 interleave_mode(u32 reg)
 840 {
 841         return GET_BITFIELD(reg, 1, 1);
 842 }
 843
 844 static u32 dram_attr(u32 reg)
 845 {
 846         return GET_BITFIELD(reg, 2, 3);
 847 }
 848
 849 static u64 knl_sad_limit(u32 reg)
 850 {
 851         return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
 852 }
 853
 854 static u32 knl_interleave_mode(u32 reg)
 855 {
 856         return GET_BITFIELD(reg, 1, 2);
 857 }
 858
 859 static const char * const knl_intlv_mode[] = {
 860         "[8:6]", "[10:8]", "[14:12]", "[32:30]"
 861 };
 862
 863 static const char *get_intlv_mode_str(u32 reg, enum type t)
 864 {
 865         if (t == KNIGHTS_LANDING)
 866                 return knl_intlv_mode[knl_interleave_mode(reg)];
 867         else
 868                 return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]";
 869 }
 870
 871 static u32 dram_attr_knl(u32 reg)
 872 {
 873         return GET_BITFIELD(reg, 3, 4);
 874 }
 875
 876
 877 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
 878 {
 879         u32 reg;
 880         enum mem_type mtype;
 881
 882         if (pvt->pci_ddrio) {
 883                 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
 884                                       &reg);
 885                 if (GET_BITFIELD(reg, 11, 11))
 886                         /* FIXME: Can also be LRDIMM */
 887                         mtype = MEM_RDDR3;
 888                 else
 889                         mtype = MEM_DDR3;
 890         } else
 891                 mtype = MEM_UNKNOWN;
 892
 893         return mtype;
 894 }
 895
 896 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
 897 {
 898         u32 reg;
 899         bool registered = false;
 900         enum mem_type mtype = MEM_UNKNOWN;
 901
 902         if (!pvt->pci_ddrio)
 903                 goto out;
 904
 905         pci_read_config_dword(pvt->pci_ddrio,
 906                               HASWELL_DDRCRCLKCONTROLS, &reg);
 907         /* Is_Rdimm */
 908         if (GET_BITFIELD(reg, 16, 16))
 909                 registered = true;
 910
 911         pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
 912         if (GET_BITFIELD(reg, 14, 14)) {
 913                 if (registered)
 914                         mtype = MEM_RDDR4;
 915                 else
 916                         mtype = MEM_DDR4;
 917         } else {
 918                 if (registered)
 919                         mtype = MEM_RDDR3;
 920                 else
 921                         mtype = MEM_DDR3;
 922         }
 923
 924 out:
 925         return mtype;
 926 }
 927
 928 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
 929 {
 930         /* for KNL value is fixed */
 931         return DEV_X16;
 932 }
 933
 934 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 935 {
 936         /* there's no way to figure out */
 937         return DEV_UNKNOWN;
 938 }
 939
 940 static enum dev_type __ibridge_get_width(u32 mtr)
 941 {
 942         enum dev_type type;
 943
 944         switch (mtr) {
 945         case 3:
 946                 type = DEV_UNKNOWN;
 947                 break;
 948         case 2:
 949                 type = DEV_X16;
 950                 break;
 951         case 1:
 952                 type = DEV_X8;
 953                 break;
 954         case 0:
 955                 type = DEV_X4;
 956                 break;
 957         }
 958
 959         return type;
 960 }
 961
 962 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 963 {
 964         /*
 965          * ddr3_width on the documentation but also valid for DDR4 on
 966          * Haswell
 967          */
 968         return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
 969 }
 970
 971 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
 972 {
 973         /* ddr3_width on the documentation but also valid for DDR4 */
 974         return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
 975 }
 976
 977 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
 978 {
 979         /* DDR4 RDIMMS and LRDIMMS are supported */
 980         return MEM_RDDR4;
 981 }
 982
 983 static u8 get_node_id(struct sbridge_pvt *pvt)
 984 {
 985         u32 reg;
 986         pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
 987         return GET_BITFIELD(reg, 0, 2);
 988 }
 989
 990 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
 991 {
 992         u32 reg;
 993
 994         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
 995         return GET_BITFIELD(reg, 0, 3);
 996 }
 997
 998 static u8 knl_get_node_id(struct sbridge_pvt *pvt)
 999 {
1000         u32 reg;
1001
1002         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
1003         return GET_BITFIELD(reg, 0, 2);
1004 }
1005
1006 /*
1007  * Use the reporting bank number to determine which memory
1008  * controller (also known as "ha" for "home agent"). Sandy
1009  * Bridge only has one memory controller per socket, so the
1010  * answer is always zero.
1011  */
1012 static u8 sbridge_get_ha(u8 bank)
1013 {
1014         return 0;
1015 }
1016
1017 /*
1018  * On Ivy Bridge, Haswell and Broadwell the error may be in a
1019  * home agent bank (7, 8), or one of the per-channel memory
1020  * controller banks (9 .. 16).
1021  */
1022 static u8 ibridge_get_ha(u8 bank)
1023 {
1024         switch (bank) {
1025         case 7 ... 8:
1026                 return bank - 7;
1027         case 9 ... 16:
1028                 return (bank - 9) / 4;
1029         default:
1030                 return 0xff;
1031         }
1032 }
1033
1034 /* Not used, but included for safety/symmetry */
1035 static u8 knl_get_ha(u8 bank)
1036 {
1037         return 0xff;
1038 }
1039
1040 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
1041 {
1042         u32 reg;
1043
1044         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
1045         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1046 }
1047
1048 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
1049 {
1050         u64 rc;
1051         u32 reg;
1052
1053         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
1054         rc = GET_BITFIELD(reg, 26, 31);
1055         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
1056         rc = ((reg << 6) | rc) << 26;
1057
1058         return rc | 0x1ffffff;
1059 }
1060
1061 static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1062 {
1063         u32 reg;
1064
1065         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, &reg);
1066         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1067 }
1068
1069 static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1070 {
1071         u64 rc;
1072         u32 reg_lo, reg_hi;
1073
1074         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, &reg_lo);
1075         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, &reg_hi);
1076         rc = ((u64)reg_hi << 32) | reg_lo;
1077         return rc | 0x3ffffff;
1078 }
1079
1080
1081 static u64 haswell_rir_limit(u32 reg)
1082 {
1083         return (((u64)GET_BITFIELD(reg,  1, 11) + 1) << 29) - 1;
1084 }
1085
1086 static inline u8 sad_pkg_socket(u8 pkg)
1087 {
1088         /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
1089         return ((pkg >> 3) << 2) | (pkg & 0x3);
1090 }
1091
1092 static inline u8 sad_pkg_ha(u8 pkg)
1093 {
1094         return (pkg >> 2) & 0x1;
1095 }
1096
1097 static int haswell_chan_hash(int idx, u64 addr)
1098 {
1099         int i;
1100
1101         /*
1102          * XOR even bits from 12:26 to bit0 of idx,
1103          *     odd bits from 13:27 to bit1
1104          */
1105         for (i = 12; i < 28; i += 2)
1106                 idx ^= (addr >> i) & 3;
1107
1108         return idx;
1109 }
1110
1111 /* Low bits of TAD limit, and some metadata. */
1112 static const u32 knl_tad_dram_limit_lo[] = {
1113         0x400, 0x500, 0x600, 0x700,
1114         0x800, 0x900, 0xa00, 0xb00,
1115 };
1116
1117 /* Low bits of TAD offset. */
1118 static const u32 knl_tad_dram_offset_lo[] = {
1119         0x404, 0x504, 0x604, 0x704,
1120         0x804, 0x904, 0xa04, 0xb04,
1121 };
1122
1123 /* High 16 bits of TAD limit and offset. */
1124 static const u32 knl_tad_dram_hi[] = {
1125         0x408, 0x508, 0x608, 0x708,
1126         0x808, 0x908, 0xa08, 0xb08,
1127 };
1128
1129 /* Number of ways a tad entry is interleaved. */
1130 static const u32 knl_tad_ways[] = {
1131         8, 6, 4, 3, 2, 1,
1132 };
1133
1134 /*
1135  * Retrieve the n'th Target Address Decode table entry
1136  * from the memory controller's TAD table.
1137  *
1138  * @pvt:        driver private data
1139  * @entry:      which entry you want to retrieve
1140  * @mc:         which memory controller (0 or 1)
1141  * @offset:     output tad range offset
1142  * @limit:      output address of first byte above tad range
1143  * @ways:       output number of interleave ways
1144  *
1145  * The offset value has curious semantics.  It's a sort of running total
1146  * of the sizes of all the memory regions that aren't mapped in this
1147  * tad table.
1148  */
1149 static int knl_get_tad(const struct sbridge_pvt *pvt,
1150                 const int entry,
1151                 const int mc,
1152                 u64 *offset,
1153                 u64 *limit,
1154                 int *ways)
1155 {
1156         u32 reg_limit_lo, reg_offset_lo, reg_hi;
1157         struct pci_dev *pci_mc;
1158         int way_id;
1159
1160         switch (mc) {
1161         case 0:
1162                 pci_mc = pvt->knl.pci_mc0;
1163                 break;
1164         case 1:
1165                 pci_mc = pvt->knl.pci_mc1;
1166                 break;
1167         default:
1168                 WARN_ON(1);
1169                 return -EINVAL;
1170         }
1171
1172         pci_read_config_dword(pci_mc,
1173                         knl_tad_dram_limit_lo[entry], &reg_limit_lo);
1174         pci_read_config_dword(pci_mc,
1175                         knl_tad_dram_offset_lo[entry], &reg_offset_lo);
1176         pci_read_config_dword(pci_mc,
1177                         knl_tad_dram_hi[entry], &reg_hi);
1178
1179         /* Is this TAD entry enabled? */
1180         if (!GET_BITFIELD(reg_limit_lo, 0, 0))
1181                 return -ENODEV;
1182
1183         way_id = GET_BITFIELD(reg_limit_lo, 3, 5);
1184
1185         if (way_id < ARRAY_SIZE(knl_tad_ways)) {
1186                 *ways = knl_tad_ways[way_id];
1187         } else {
1188                 *ways = 0;
1189                 sbridge_printk(KERN_ERR,
1190                                 "Unexpected value %d in mc_tad_limit_lo wayness field\n",
1191                                 way_id);
1192                 return -ENODEV;
1193         }
1194
1195         /*
1196          * The least significant 6 bits of base and limit are truncated.
1197          * For limit, we fill the missing bits with 1s.
1198          */
1199         *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |
1200                                 ((u64) GET_BITFIELD(reg_hi, 0,  15) << 32);
1201         *limit = ((u64) GET_BITFIELD(reg_limit_lo,  6, 31) << 6) | 63 |
1202                                 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);
1203
1204         return 0;
1205 }
1206
1207 /* Determine which memory controller is responsible for a given channel. */
1208 static int knl_channel_mc(int channel)
1209 {
1210         WARN_ON(channel < 0 || channel >= 6);
1211
1212         return channel < 3 ? 1 : 0;
1213 }
1214
1215 /*
1216  * Get the Nth entry from EDC_ROUTE_TABLE register.
1217  * (This is the per-tile mapping of logical interleave targets to
1218  *  physical EDC modules.)
1219  *
1220  * entry 0: 0:2
1221  *       1: 3:5
1222  *       2: 6:8
1223  *       3: 9:11
1224  *       4: 12:14
1225  *       5: 15:17
1226  *       6: 18:20
1227  *       7: 21:23
1228  * reserved: 24:31
1229  */
1230 static u32 knl_get_edc_route(int entry, u32 reg)
1231 {
1232         WARN_ON(entry >= KNL_MAX_EDCS);
1233         return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1234 }
1235
1236 /*
1237  * Get the Nth entry from MC_ROUTE_TABLE register.
1238  * (This is the per-tile mapping of logical interleave targets to
1239  *  physical DRAM channels modules.)
1240  *
1241  * entry 0: mc 0:2   channel 18:19
1242  *       1: mc 3:5   channel 20:21
1243  *       2: mc 6:8   channel 22:23
1244  *       3: mc 9:11  channel 24:25
1245  *       4: mc 12:14 channel 26:27
1246  *       5: mc 15:17 channel 28:29
1247  * reserved: 30:31
1248  *
1249  * Though we have 3 bits to identify the MC, we should only see
1250  * the values 0 or 1.
1251  */
1252
1253 static u32 knl_get_mc_route(int entry, u32 reg)
1254 {
1255         int mc, chan;
1256
1257         WARN_ON(entry >= KNL_MAX_CHANNELS);
1258
1259         mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1260         chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1261
1262         return knl_channel_remap(mc, chan);
1263 }
1264
1265 /*
1266  * Render the EDC_ROUTE register in human-readable form.
1267  * Output string s should be at least KNL_MAX_EDCS*2 bytes.
1268  */
1269 static void knl_show_edc_route(u32 reg, char *s)
1270 {
1271         int i;
1272
1273         for (i = 0; i < KNL_MAX_EDCS; i++) {
1274                 s[i*2] = knl_get_edc_route(i, reg) + '0';
1275                 s[i*2+1] = '-';
1276         }
1277
1278         s[KNL_MAX_EDCS*2 - 1] = '\0';
1279 }
1280
1281 /*
1282  * Render the MC_ROUTE register in human-readable form.
1283  * Output string s should be at least KNL_MAX_CHANNELS*2 bytes.
1284  */
1285 static void knl_show_mc_route(u32 reg, char *s)
1286 {
1287         int i;
1288
1289         for (i = 0; i < KNL_MAX_CHANNELS; i++) {
1290                 s[i*2] = knl_get_mc_route(i, reg) + '0';
1291                 s[i*2+1] = '-';
1292         }
1293
1294         s[KNL_MAX_CHANNELS*2 - 1] = '\0';
1295 }
1296
1297 #define KNL_EDC_ROUTE 0xb8
1298 #define KNL_MC_ROUTE 0xb4
1299
1300 /* Is this dram rule backed by regular DRAM in flat mode? */
1301 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1302
1303 /* Is this dram rule cached? */
1304 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1305
1306 /* Is this rule backed by edc ? */
1307 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1308
1309 /* Is this rule backed by DRAM, cacheable in EDRAM? */
1310 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1311
1312 /* Is this rule mod3? */
1313 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1314
1315 /*
1316  * Figure out how big our RAM modules are.
1317  *
1318  * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
1319  * have to figure this out from the SAD rules, interleave lists, route tables,
1320  * and TAD rules.
1321  *
1322  * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1323  * inspect the TAD rules to figure out how large the SAD regions really are.
1324  *
1325  * When we know the real size of a SAD region and how many ways it's
1326  * interleaved, we know the individual contribution of each channel to
1327  * TAD is size/ways.
1328  *
1329  * Finally, we have to check whether each channel participates in each SAD
1330  * region.
1331  *
1332  * Fortunately, KNL only supports one DIMM per channel, so once we know how
1333  * much memory the channel uses, we know the DIMM is at least that large.
1334  * (The BIOS might possibly choose not to map all available memory, in which
1335  * case we will underreport the size of the DIMM.)
1336  *
1337  * In theory, we could try to determine the EDC sizes as well, but that would
1338  * only work in flat mode, not in cache mode.
1339  *
1340  * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS
1341  *            elements)
1342  */
1343 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1344 {
1345         u64 sad_base, sad_size, sad_limit = 0;
1346         u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace;
1347         int sad_rule = 0;
1348         int tad_rule = 0;
1349         int intrlv_ways, tad_ways;
1350         u32 first_pkg, pkg;
1351         int i;
1352         u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
1353         u32 dram_rule, interleave_reg;
1354         u32 mc_route_reg[KNL_MAX_CHAS];
1355         u32 edc_route_reg[KNL_MAX_CHAS];
1356         int edram_only;
1357         char edc_route_string[KNL_MAX_EDCS*2];
1358         char mc_route_string[KNL_MAX_CHANNELS*2];
1359         int cur_reg_start;
1360         int mc;
1361         int channel;
1362         int participants[KNL_MAX_CHANNELS];
1363
1364         for (i = 0; i < KNL_MAX_CHANNELS; i++)
1365                 mc_sizes[i] = 0;
1366
1367         /* Read the EDC route table in each CHA. */
1368         cur_reg_start = 0;
1369         for (i = 0; i < KNL_MAX_CHAS; i++) {
1370                 pci_read_config_dword(pvt->knl.pci_cha[i],
1371                                 KNL_EDC_ROUTE, &edc_route_reg[i]);
1372
1373                 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) {
1374                         knl_show_edc_route(edc_route_reg[i-1],
1375                                         edc_route_string);
1376                         if (cur_reg_start == i-1)
1377                                 edac_dbg(0, "edc route table for CHA %d: %s\n",
1378                                         cur_reg_start, edc_route_string);
1379                         else
1380                                 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1381                                         cur_reg_start, i-1, edc_route_string);
1382                         cur_reg_start = i;
1383                 }
1384         }
1385         knl_show_edc_route(edc_route_reg[i-1], edc_route_string);
1386         if (cur_reg_start == i-1)
1387                 edac_dbg(0, "edc route table for CHA %d: %s\n",
1388                         cur_reg_start, edc_route_string);
1389         else
1390                 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1391                         cur_reg_start, i-1, edc_route_string);
1392
1393         /* Read the MC route table in each CHA. */
1394         cur_reg_start = 0;
1395         for (i = 0; i < KNL_MAX_CHAS; i++) {
1396                 pci_read_config_dword(pvt->knl.pci_cha[i],
1397                         KNL_MC_ROUTE, &mc_route_reg[i]);
1398
1399                 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) {
1400                         knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1401                         if (cur_reg_start == i-1)
1402                                 edac_dbg(0, "mc route table for CHA %d: %s\n",
1403                                         cur_reg_start, mc_route_string);
1404                         else
1405                                 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1406                                         cur_reg_start, i-1, mc_route_string);
1407                         cur_reg_start = i;
1408                 }
1409         }
1410         knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1411         if (cur_reg_start == i-1)
1412                 edac_dbg(0, "mc route table for CHA %d: %s\n",
1413                         cur_reg_start, mc_route_string);
1414         else
1415                 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1416                         cur_reg_start, i-1, mc_route_string);
1417
1418         /* Process DRAM rules */
1419         for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1420                 /* previous limit becomes the new base */
1421                 sad_base = sad_limit;
1422
1423                 pci_read_config_dword(pvt->pci_sad0,
1424                         pvt->info.dram_rule[sad_rule], &dram_rule);
1425
1426                 if (!DRAM_RULE_ENABLE(dram_rule))
1427                         break;
1428
1429                 edram_only = KNL_EDRAM_ONLY(dram_rule);
1430
1431                 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1432                 sad_size = sad_limit - sad_base;
1433
1434                 pci_read_config_dword(pvt->pci_sad0,
1435                         pvt->info.interleave_list[sad_rule], &interleave_reg);
1436
1437                 /*
1438                  * Find out how many ways this dram rule is interleaved.
1439                  * We stop when we see the first channel again.
1440                  */
1441                 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1442                                                 interleave_reg, 0);
1443                 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) {
1444                         pkg = sad_pkg(pvt->info.interleave_pkg,
1445                                                 interleave_reg, intrlv_ways);
1446
1447                         if ((pkg & 0x8) == 0) {
1448                                 /*
1449                                  * 0 bit means memory is non-local,
1450                                  * which KNL doesn't support
1451                                  */
1452                                 edac_dbg(0, "Unexpected interleave target %d\n",
1453                                         pkg);
1454                                 return -1;
1455                         }
1456
1457                         if (pkg == first_pkg)
1458                                 break;
1459                 }
1460                 if (KNL_MOD3(dram_rule))
1461                         intrlv_ways *= 3;
1462
1463                 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
1464                         sad_rule,
1465                         sad_base,
1466                         sad_limit,
1467                         intrlv_ways,
1468                         edram_only ? ", EDRAM" : "");
1469
1470                 /*
1471                  * Find out how big the SAD region really is by iterating
1472                  * over TAD tables (SAD regions may contain holes).
1473                  * Each memory controller might have a different TAD table, so
1474                  * we have to look at both.
1475                  *
1476                  * Livespace is the memory that's mapped in this TAD table,
1477                  * deadspace is the holes (this could be the MMIO hole, or it
1478                  * could be memory that's mapped by the other TAD table but
1479                  * not this one).
1480                  */
1481                 for (mc = 0; mc < 2; mc++) {
1482                         sad_actual_size[mc] = 0;
1483                         tad_livespace = 0;
1484                         for (tad_rule = 0;
1485                                         tad_rule < ARRAY_SIZE(
1486                                                 knl_tad_dram_limit_lo);
1487                                         tad_rule++) {
1488                                 if (knl_get_tad(pvt,
1489                                                 tad_rule,
1490                                                 mc,
1491                                                 &tad_deadspace,
1492                                                 &tad_limit,
1493                                                 &tad_ways))
1494                                         break;
1495
1496                                 tad_size = (tad_limit+1) -
1497                                         (tad_livespace + tad_deadspace);
1498                                 tad_livespace += tad_size;
1499                                 tad_base = (tad_limit+1) - tad_size;
1500
1501                                 if (tad_base < sad_base) {
1502                                         if (tad_limit > sad_base)
1503                                                 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n");
1504                                 } else if (tad_base < sad_limit) {
1505                                         if (tad_limit+1 > sad_limit) {
1506                                                 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n");
1507                                         } else {
1508                                                 /* TAD region is completely inside SAD region */
1509                                                 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n",
1510                                                         tad_rule, tad_base,
1511                                                         tad_limit, tad_size,
1512                                                         mc);
1513                                                 sad_actual_size[mc] += tad_size;
1514                                         }
1515                                 }
1516                                 tad_base = tad_limit+1;
1517                         }
1518                 }
1519
1520                 for (mc = 0; mc < 2; mc++) {
1521                         edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n",
1522                                 mc, sad_actual_size[mc], sad_actual_size[mc]);
1523                 }
1524
1525                 /* Ignore EDRAM rule */
1526                 if (edram_only)
1527                         continue;
1528
1529                 /* Figure out which channels participate in interleave. */
1530                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1531                         participants[channel] = 0;
1532
1533                 /* For each channel, does at least one CHA have
1534                  * this channel mapped to the given target?
1535                  */
1536                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1537                         int target;
1538                         int cha;
1539
1540                         for (target = 0; target < KNL_MAX_CHANNELS; target++) {
1541                                 for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
1542                                         if (knl_get_mc_route(target,
1543                                                 mc_route_reg[cha]) == channel
1544                                                 && !participants[channel]) {
1545                                                 participants[channel] = 1;
1546                                                 break;
1547                                         }
1548                                 }
1549                         }
1550                 }
1551
1552                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1553                         mc = knl_channel_mc(channel);
1554                         if (participants[channel]) {
1555                                 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1556                                         channel,
1557                                         sad_actual_size[mc]/intrlv_ways,
1558                                         sad_rule);
1559                                 mc_sizes[channel] +=
1560                                         sad_actual_size[mc]/intrlv_ways;
1561                         }
1562                 }
1563         }
1564
1565         return 0;
1566 }
1567
1568 static void get_source_id(struct mem_ctl_info *mci)
1569 {
1570         struct sbridge_pvt *pvt = mci->pvt_info;
1571         u32 reg;
1572
1573         if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1574             pvt->info.type == KNIGHTS_LANDING)
1575                 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
1576         else
1577                 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
1578
1579         if (pvt->info.type == KNIGHTS_LANDING)
1580                 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1581         else
1582                 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1583 }
1584
1585 static int __populate_dimms(struct mem_ctl_info *mci,
1586                             u64 knl_mc_sizes[KNL_MAX_CHANNELS],
1587                             enum edac_type mode)
1588 {
1589         struct sbridge_pvt *pvt = mci->pvt_info;
1590         int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS
1591                                                          : NUM_CHANNELS;
1592         unsigned int i, j, banks, ranks, rows, cols, npages;
1593         struct dimm_info *dimm;
1594         enum mem_type mtype;
1595         u64 size;
1596
1597         mtype = pvt->info.get_memory_type(pvt);
1598         if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
1599                 edac_dbg(0, "Memory is registered\n");
1600         else if (mtype == MEM_UNKNOWN)
1601                 edac_dbg(0, "Cannot determine memory type\n");
1602         else
1603                 edac_dbg(0, "Memory is unregistered\n");
1604
1605         if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
1606                 banks = 16;
1607         else
1608                 banks = 8;
1609
1610         for (i = 0; i < channels; i++) {
1611                 u32 mtr;
1612
1613                 int max_dimms_per_channel;
1614
1615                 if (pvt->info.type == KNIGHTS_LANDING) {
1616                         max_dimms_per_channel = 1;
1617                         if (!pvt->knl.pci_channel[i])
1618                                 continue;
1619                 } else {
1620                         max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
1621                         if (!pvt->pci_tad[i])
1622                                 continue;
1623                 }
1624
1625                 for (j = 0; j < max_dimms_per_channel; j++) {
1626                         dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0);
1627                         if (pvt->info.type == KNIGHTS_LANDING) {
1628                                 pci_read_config_dword(pvt->knl.pci_channel[i],
1629                                         knl_mtr_reg, &mtr);
1630                         } else {
1631                                 pci_read_config_dword(pvt->pci_tad[i],
1632                                         mtr_regs[j], &mtr);
1633                         }
1634                         edac_dbg(4, "Channel #%d  MTR%d = %x\n", i, j, mtr);
1635                         if (IS_DIMM_PRESENT(mtr)) {
1636                                 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
1637                                         sbridge_printk(KERN_ERR, "CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n",
1638                                                        pvt->sbridge_dev->source_id,
1639                                                        pvt->sbridge_dev->dom, i);
1640                                         return -ENODEV;
1641                                 }
1642                                 pvt->channel[i].dimms++;
1643
1644                                 ranks = numrank(pvt->info.type, mtr);
1645
1646                                 if (pvt->info.type == KNIGHTS_LANDING) {
1647                                         /* For DDR4, this is fixed. */
1648                                         cols = 1 << 10;
1649                                         rows = knl_mc_sizes[i] /
1650                                                 ((u64) cols * ranks * banks * 8);
1651                                 } else {
1652                                         rows = numrow(mtr);
1653                                         cols = numcol(mtr);
1654                                 }
1655
1656                                 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
1657                                 npages = MiB_TO_PAGES(size);
1658
1659                                 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1660                                          pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j,
1661                                          size, npages,
1662                                          banks, ranks, rows, cols);
1663
1664                                 dimm->nr_pages = npages;
1665                                 dimm->grain = 32;
1666                                 dimm->dtype = pvt->info.get_width(pvt, mtr);
1667                                 dimm->mtype = mtype;
1668                                 dimm->edac_mode = mode;
1669                                 snprintf(dimm->label, sizeof(dimm->label),
1670                                                  "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1671                                                  pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j);
1672                         }
1673                 }
1674         }
1675
1676         return 0;
1677 }
1678
1679 static int get_dimm_config(struct mem_ctl_info *mci)
1680 {
1681         struct sbridge_pvt *pvt = mci->pvt_info;
1682         u64 knl_mc_sizes[KNL_MAX_CHANNELS];
1683         enum edac_type mode;
1684         u32 reg;
1685
1686         pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1687         edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
1688                  pvt->sbridge_dev->mc,
1689                  pvt->sbridge_dev->node_id,
1690                  pvt->sbridge_dev->source_id);
1691
1692         /* KNL doesn't support mirroring or lockstep,
1693          * and is always closed page
1694          */
1695         if (pvt->info.type == KNIGHTS_LANDING) {
1696                 mode = EDAC_S4ECD4ED;
1697                 pvt->mirror_mode = NON_MIRRORING;
1698                 pvt->is_cur_addr_mirrored = false;
1699
1700                 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1701                         return -1;
1702                 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) {
1703                         edac_dbg(0, "Failed to read KNL_MCMTR register\n");
1704                         return -ENODEV;
1705                 }
1706         } else {
1707                 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1708                         if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, &reg)) {
1709                                 edac_dbg(0, "Failed to read HASWELL_HASYSDEFEATURE2 register\n");
1710                                 return -ENODEV;
1711                         }
1712                         pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
1713                         if (GET_BITFIELD(reg, 28, 28)) {
1714                                 pvt->mirror_mode = ADDR_RANGE_MIRRORING;
1715                                 edac_dbg(0, "Address range partial memory mirroring is enabled\n");
1716                                 goto next;
1717                         }
1718                 }
1719                 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg)) {
1720                         edac_dbg(0, "Failed to read RASENABLES register\n");
1721                         return -ENODEV;
1722                 }
1723                 if (IS_MIRROR_ENABLED(reg)) {
1724                         pvt->mirror_mode = FULL_MIRRORING;
1725                         edac_dbg(0, "Full memory mirroring is enabled\n");
1726                 } else {
1727                         pvt->mirror_mode = NON_MIRRORING;
1728                         edac_dbg(0, "Memory mirroring is disabled\n");
1729                 }
1730
1731 next:
1732                 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) {
1733                         edac_dbg(0, "Failed to read MCMTR register\n");
1734                         return -ENODEV;
1735                 }
1736                 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1737                         edac_dbg(0, "Lockstep is enabled\n");
1738                         mode = EDAC_S8ECD8ED;
1739                         pvt->is_lockstep = true;
1740                 } else {
1741                         edac_dbg(0, "Lockstep is disabled\n");
1742                         mode = EDAC_S4ECD4ED;
1743                         pvt->is_lockstep = false;
1744                 }
1745                 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1746                         edac_dbg(0, "address map is on closed page mode\n");
1747                         pvt->is_close_pg = true;
1748                 } else {
1749                         edac_dbg(0, "address map is on open page mode\n");
1750                         pvt->is_close_pg = false;
1751                 }
1752         }
1753
1754         return __populate_dimms(mci, knl_mc_sizes, mode);
1755 }
1756
1757 static void get_memory_layout(const struct mem_ctl_info *mci)
1758 {
1759         struct sbridge_pvt *pvt = mci->pvt_info;
1760         int i, j, k, n_sads, n_tads, sad_interl;
1761         u32 reg;
1762         u64 limit, prv = 0;
1763         u64 tmp_mb;
1764         u32 gb, mb;
1765         u32 rir_way;
1766
1767         /*
1768          * Step 1) Get TOLM/TOHM ranges
1769          */
1770
1771         pvt->tolm = pvt->info.get_tolm(pvt);
1772         tmp_mb = (1 + pvt->tolm) >> 20;
1773
1774         gb = div_u64_rem(tmp_mb, 1024, &mb);
1775         edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1776                 gb, (mb*1000)/1024, (u64)pvt->tolm);
1777
1778         /* Address range is already 45:25 */
1779         pvt->tohm = pvt->info.get_tohm(pvt);
1780         tmp_mb = (1 + pvt->tohm) >> 20;
1781
1782         gb = div_u64_rem(tmp_mb, 1024, &mb);
1783         edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1784                 gb, (mb*1000)/1024, (u64)pvt->tohm);
1785
1786         /*
1787          * Step 2) Get SAD range and SAD Interleave list
1788          * TAD registers contain the interleave wayness. However, it
1789          * seems simpler to just discover it indirectly, with the
1790          * algorithm bellow.
1791          */
1792         prv = 0;
1793         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1794                 /* SAD_LIMIT Address range is 45:26 */
1795                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1796                                       &reg);
1797                 limit = pvt->info.sad_limit(reg);
1798
1799                 if (!DRAM_RULE_ENABLE(reg))
1800                         continue;
1801
1802                 if (limit <= prv)
1803                         break;
1804
1805                 tmp_mb = (limit + 1) >> 20;
1806                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1807                 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1808                          n_sads,
1809                          show_dram_attr(pvt->info.dram_attr(reg)),
1810                          gb, (mb*1000)/1024,
1811                          ((u64)tmp_mb) << 20L,
1812                          get_intlv_mode_str(reg, pvt->info.type),
1813                          reg);
1814                 prv = limit;
1815
1816                 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1817                                       &reg);
1818                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1819                 for (j = 0; j < 8; j++) {
1820                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1821                         if (j > 0 && sad_interl == pkg)
1822                                 break;
1823
1824                         edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1825                                  n_sads, j, pkg);
1826                 }
1827         }
1828
1829         if (pvt->info.type == KNIGHTS_LANDING)
1830                 return;
1831
1832         /*
1833          * Step 3) Get TAD range
1834          */
1835         prv = 0;
1836         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1837                 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], &reg);
1838                 limit = TAD_LIMIT(reg);
1839                 if (limit <= prv)
1840                         break;
1841                 tmp_mb = (limit + 1) >> 20;
1842
1843                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1844                 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1845                          n_tads, gb, (mb*1000)/1024,
1846                          ((u64)tmp_mb) << 20L,
1847                          (u32)(1 << TAD_SOCK(reg)),
1848                          (u32)TAD_CH(reg) + 1,
1849                          (u32)TAD_TGT0(reg),
1850                          (u32)TAD_TGT1(reg),
1851                          (u32)TAD_TGT2(reg),
1852                          (u32)TAD_TGT3(reg),
1853                          reg);
1854                 prv = limit;
1855         }
1856
1857         /*
1858          * Step 4) Get TAD offsets, per each channel
1859          */
1860         for (i = 0; i < NUM_CHANNELS; i++) {
1861                 if (!pvt->channel[i].dimms)
1862                         continue;
1863                 for (j = 0; j < n_tads; j++) {
1864                         pci_read_config_dword(pvt->pci_tad[i],
1865                                               tad_ch_nilv_offset[j],
1866                                               &reg);
1867                         tmp_mb = TAD_OFFSET(reg) >> 20;
1868                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1869                         edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1870                                  i, j,
1871                                  gb, (mb*1000)/1024,
1872                                  ((u64)tmp_mb) << 20L,
1873                                  reg);
1874                 }
1875         }
1876
1877         /*
1878          * Step 6) Get RIR Wayness/Limit, per each channel
1879          */
1880         for (i = 0; i < NUM_CHANNELS; i++) {
1881                 if (!pvt->channel[i].dimms)
1882                         continue;
1883                 for (j = 0; j < MAX_RIR_RANGES; j++) {
1884                         pci_read_config_dword(pvt->pci_tad[i],
1885                                               rir_way_limit[j],
1886                                               &reg);
1887
1888                         if (!IS_RIR_VALID(reg))
1889                                 continue;
1890
1891                         tmp_mb = pvt->info.rir_limit(reg) >> 20;
1892                         rir_way = 1 << RIR_WAY(reg);
1893                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1894                         edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1895                                  i, j,
1896                                  gb, (mb*1000)/1024,
1897                                  ((u64)tmp_mb) << 20L,
1898                                  rir_way,
1899                                  reg);
1900
1901                         for (k = 0; k < rir_way; k++) {
1902                                 pci_read_config_dword(pvt->pci_tad[i],
1903                                                       rir_offset[j][k],
1904                                                       &reg);
1905                                 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1906
1907                                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1908                                 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1909                                          i, j, k,
1910                                          gb, (mb*1000)/1024,
1911                                          ((u64)tmp_mb) << 20L,
1912                                          (u32)RIR_RNK_TGT(pvt->info.type, reg),
1913                                          reg);
1914                         }
1915                 }
1916         }
1917 }
1918
1919 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha)
1920 {
1921         struct sbridge_dev *sbridge_dev;
1922
1923         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1924                 if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha)
1925                         return sbridge_dev->mci;
1926         }
1927         return NULL;
1928 }
1929
1930 static int get_memory_error_data(struct mem_ctl_info *mci,
1931                                  u64 addr,
1932                                  u8 *socket, u8 *ha,
1933                                  long *channel_mask,
1934                                  u8 *rank,
1935                                  char **area_type, char *msg)
1936 {
1937         struct mem_ctl_info     *new_mci;
1938         struct sbridge_pvt *pvt = mci->pvt_info;
1939         struct pci_dev          *pci_ha;
1940         int                     n_rir, n_sads, n_tads, sad_way, sck_xch;
1941         int                     sad_interl, idx, base_ch;
1942         int                     interleave_mode, shiftup = 0;
1943         unsigned int            sad_interleave[MAX_INTERLEAVE];
1944         u32                     reg, dram_rule;
1945         u8                      ch_way, sck_way, pkg, sad_ha = 0;
1946         u32                     tad_offset;
1947         u32                     rir_way;
1948         u32                     mb, gb;
1949         u64                     ch_addr, offset, limit = 0, prv = 0;
1950
1951
1952         /*
1953          * Step 0) Check if the address is at special memory ranges
1954          * The check bellow is probably enough to fill all cases where
1955          * the error is not inside a memory, except for the legacy
1956          * range (e. g. VGA addresses). It is unlikely, however, that the
1957          * memory controller would generate an error on that range.
1958          */
1959         if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1960                 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1961                 return -EINVAL;
1962         }
1963         if (addr >= (u64)pvt->tohm) {
1964                 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1965                 return -EINVAL;
1966         }
1967
1968         /*
1969          * Step 1) Get socket
1970          */
1971         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1972                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1973                                       &reg);
1974
1975                 if (!DRAM_RULE_ENABLE(reg))
1976                         continue;
1977
1978                 limit = pvt->info.sad_limit(reg);
1979                 if (limit <= prv) {
1980                         sprintf(msg, "Can't discover the memory socket");
1981                         return -EINVAL;
1982                 }
1983                 if  (addr <= limit)
1984                         break;
1985                 prv = limit;
1986         }
1987         if (n_sads == pvt->info.max_sad) {
1988                 sprintf(msg, "Can't discover the memory socket");
1989                 return -EINVAL;
1990         }
1991         dram_rule = reg;
1992         *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1993         interleave_mode = pvt->info.interleave_mode(dram_rule);
1994
1995         pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1996                               &reg);
1997
1998         if (pvt->info.type == SANDY_BRIDGE) {
1999                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
2000                 for (sad_way = 0; sad_way < 8; sad_way++) {
2001                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
2002                         if (sad_way > 0 && sad_interl == pkg)
2003                                 break;
2004                         sad_interleave[sad_way] = pkg;
2005                         edac_dbg(0, "SAD interleave #%d: %d\n",
2006                                  sad_way, sad_interleave[sad_way]);
2007                 }
2008                 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
2009                          pvt->sbridge_dev->mc,
2010                          n_sads,
2011                          addr,
2012                          limit,
2013                          sad_way + 7,
2014                          !interleave_mode ? "" : "XOR[18:16]");
2015                 if (interleave_mode)
2016                         idx = ((addr >> 6) ^ (addr >> 16)) & 7;
2017                 else
2018                         idx = (addr >> 6) & 7;
2019                 switch (sad_way) {
2020                 case 1:
2021                         idx = 0;
2022                         break;
2023                 case 2:
2024                         idx = idx & 1;
2025                         break;
2026                 case 4:
2027                         idx = idx & 3;
2028                         break;
2029                 case 8:
2030                         break;
2031                 default:
2032                         sprintf(msg, "Can't discover socket interleave");
2033                         return -EINVAL;
2034                 }
2035                 *socket = sad_interleave[idx];
2036                 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
2037                          idx, sad_way, *socket);
2038         } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
2039                 int bits, a7mode = A7MODE(dram_rule);
2040
2041                 if (a7mode) {
2042                         /* A7 mode swaps P9 with P6 */
2043                         bits = GET_BITFIELD(addr, 7, 8) << 1;
2044                         bits |= GET_BITFIELD(addr, 9, 9);
2045                 } else
2046                         bits = GET_BITFIELD(addr, 6, 8);
2047
2048                 if (interleave_mode == 0) {
2049                         /* interleave mode will XOR {8,7,6} with {18,17,16} */
2050                         idx = GET_BITFIELD(addr, 16, 18);
2051                         idx ^= bits;
2052                 } else
2053                         idx = bits;
2054
2055                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2056                 *socket = sad_pkg_socket(pkg);
2057                 sad_ha = sad_pkg_ha(pkg);
2058
2059                 if (a7mode) {
2060                         /* MCChanShiftUpEnable */
2061                         pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, &reg);
2062                         shiftup = GET_BITFIELD(reg, 22, 22);
2063                 }
2064
2065                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
2066                          idx, *socket, sad_ha, shiftup);
2067         } else {
2068                 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
2069                 idx = (addr >> 6) & 7;
2070                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2071                 *socket = sad_pkg_socket(pkg);
2072                 sad_ha = sad_pkg_ha(pkg);
2073                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
2074                          idx, *socket, sad_ha);
2075         }
2076
2077         *ha = sad_ha;
2078
2079         /*
2080          * Move to the proper node structure, in order to access the
2081          * right PCI registers
2082          */
2083         new_mci = get_mci_for_node_id(*socket, sad_ha);
2084         if (!new_mci) {
2085                 sprintf(msg, "Struct for socket #%u wasn't initialized",
2086                         *socket);
2087                 return -EINVAL;
2088         }
2089         mci = new_mci;
2090         pvt = mci->pvt_info;
2091
2092         /*
2093          * Step 2) Get memory channel
2094          */
2095         prv = 0;
2096         pci_ha = pvt->pci_ha;
2097         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
2098                 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
2099                 limit = TAD_LIMIT(reg);
2100                 if (limit <= prv) {
2101                         sprintf(msg, "Can't discover the memory channel");
2102                         return -EINVAL;
2103                 }
2104                 if  (addr <= limit)
2105                         break;
2106                 prv = limit;
2107         }
2108         if (n_tads == MAX_TAD) {
2109                 sprintf(msg, "Can't discover the memory channel");
2110                 return -EINVAL;
2111         }
2112
2113         ch_way = TAD_CH(reg) + 1;
2114         sck_way = TAD_SOCK(reg);
2115
2116         if (ch_way == 3)
2117                 idx = addr >> 6;
2118         else {
2119                 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
2120                 if (pvt->is_chan_hash)
2121                         idx = haswell_chan_hash(idx, addr);
2122         }
2123         idx = idx % ch_way;
2124
2125         /*
2126          * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
2127          */
2128         switch (idx) {
2129         case 0:
2130                 base_ch = TAD_TGT0(reg);
2131                 break;
2132         case 1:
2133                 base_ch = TAD_TGT1(reg);
2134                 break;
2135         case 2:
2136                 base_ch = TAD_TGT2(reg);
2137                 break;
2138         case 3:
2139                 base_ch = TAD_TGT3(reg);
2140                 break;
2141         default:
2142                 sprintf(msg, "Can't discover the TAD target");
2143                 return -EINVAL;
2144         }
2145         *channel_mask = 1 << base_ch;
2146
2147         pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset);
2148
2149         if (pvt->mirror_mode == FULL_MIRRORING ||
2150             (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) {
2151                 *channel_mask |= 1 << ((base_ch + 2) % 4);
2152                 switch(ch_way) {
2153                 case 2:
2154                 case 4:
2155                         sck_xch = (1 << sck_way) * (ch_way >> 1);
2156                         break;
2157                 default:
2158                         sprintf(msg, "Invalid mirror set. Can't decode addr");
2159                         return -EINVAL;
2160                 }
2161
2162                 pvt->is_cur_addr_mirrored = true;
2163         } else {
2164                 sck_xch = (1 << sck_way) * ch_way;
2165                 pvt->is_cur_addr_mirrored = false;
2166         }
2167
2168         if (pvt->is_lockstep)
2169                 *channel_mask |= 1 << ((base_ch + 1) % 4);
2170
2171         offset = TAD_OFFSET(tad_offset);
2172
2173         edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2174                  n_tads,
2175                  addr,
2176                  limit,
2177                  sck_way,
2178                  ch_way,
2179                  offset,
2180                  idx,
2181                  base_ch,
2182                  *channel_mask);
2183
2184         /* Calculate channel address */
2185         /* Remove the TAD offset */
2186
2187         if (offset > addr) {
2188                 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
2189                         offset, addr);
2190                 return -EINVAL;
2191         }
2192
2193         ch_addr = addr - offset;
2194         ch_addr >>= (6 + shiftup);
2195         ch_addr /= sck_xch;
2196         ch_addr <<= (6 + shiftup);
2197         ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
2198
2199         /*
2200          * Step 3) Decode rank
2201          */
2202         for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
2203                 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], &reg);
2204
2205                 if (!IS_RIR_VALID(reg))
2206                         continue;
2207
2208                 limit = pvt->info.rir_limit(reg);
2209                 gb = div_u64_rem(limit >> 20, 1024, &mb);
2210                 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
2211                          n_rir,
2212                          gb, (mb*1000)/1024,
2213                          limit,
2214                          1 << RIR_WAY(reg));
2215                 if  (ch_addr <= limit)
2216                         break;
2217         }
2218         if (n_rir == MAX_RIR_RANGES) {
2219                 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
2220                         ch_addr);
2221                 return -EINVAL;
2222         }
2223         rir_way = RIR_WAY(reg);
2224
2225         if (pvt->is_close_pg)
2226                 idx = (ch_addr >> 6);
2227         else
2228                 idx = (ch_addr >> 13);  /* FIXME: Datasheet says to shift by 15 */
2229         idx %= 1 << rir_way;
2230
2231         pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], &reg);
2232         *rank = RIR_RNK_TGT(pvt->info.type, reg);
2233
2234         edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2235                  n_rir,
2236                  ch_addr,
2237                  limit,
2238                  rir_way,
2239                  idx);
2240
2241         return 0;
2242 }
2243
2244 static int get_memory_error_data_from_mce(struct mem_ctl_info *mci,
2245                                           const struct mce *m, u8 *socket,
2246                                           u8 *ha, long *channel_mask,
2247                                           char *msg)
2248 {
2249         u32 reg, channel = GET_BITFIELD(m->status, 0, 3);
2250         struct mem_ctl_info *new_mci;
2251         struct sbridge_pvt *pvt;
2252         struct pci_dev *pci_ha;
2253         bool tad0;
2254
2255         if (channel >= NUM_CHANNELS) {
2256                 sprintf(msg, "Invalid channel 0x%x", channel);
2257                 return -EINVAL;
2258         }
2259
2260         pvt = mci->pvt_info;
2261         if (!pvt->info.get_ha) {
2262                 sprintf(msg, "No get_ha()");
2263                 return -EINVAL;
2264         }
2265         *ha = pvt->info.get_ha(m->bank);
2266         if (*ha != 0 && *ha != 1) {
2267                 sprintf(msg, "Impossible bank %d", m->bank);
2268                 return -EINVAL;
2269         }
2270
2271         *socket = m->socketid;
2272         new_mci = get_mci_for_node_id(*socket, *ha);
2273         if (!new_mci) {
2274                 strcpy(msg, "mci socket got corrupted!");
2275                 return -EINVAL;
2276         }
2277
2278         pvt = new_mci->pvt_info;
2279         pci_ha = pvt->pci_ha;
2280         pci_read_config_dword(pci_ha, tad_dram_rule[0], &reg);
2281         tad0 = m->addr <= TAD_LIMIT(reg);
2282
2283         *channel_mask = 1 << channel;
2284         if (pvt->mirror_mode == FULL_MIRRORING ||
2285             (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) {
2286                 *channel_mask |= 1 << ((channel + 2) % 4);
2287                 pvt->is_cur_addr_mirrored = true;
2288         } else {
2289                 pvt->is_cur_addr_mirrored = false;
2290         }
2291
2292         if (pvt->is_lockstep)
2293                 *channel_mask |= 1 << ((channel + 1) % 4);
2294
2295         return 0;
2296 }
2297
2298 /****************************************************************************
2299         Device initialization routines: put/get, init/exit
2300  ****************************************************************************/
2301
2302 /*
2303  *      sbridge_put_all_devices 'put' all the devices that we have
2304  *                              reserved via 'get'
2305  */
2306 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
2307 {
2308         int i;
2309
2310         edac_dbg(0, "\n");
2311         for (i = 0; i < sbridge_dev->n_devs; i++) {
2312                 struct pci_dev *pdev = sbridge_dev->pdev[i];
2313                 if (!pdev)
2314                         continue;
2315                 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
2316                          pdev->bus->number,
2317                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
2318                 pci_dev_put(pdev);
2319         }
2320 }
2321
2322 static void sbridge_put_all_devices(void)
2323 {
2324         struct sbridge_dev *sbridge_dev, *tmp;
2325
2326         list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
2327                 sbridge_put_devices(sbridge_dev);
2328                 free_sbridge_dev(sbridge_dev);
2329         }
2330 }
2331
2332 static int sbridge_get_onedevice(struct pci_dev **prev,
2333                                  u8 *num_mc,
2334                                  const struct pci_id_table *table,
2335                                  const unsigned devno,
2336                                  const int multi_bus)
2337 {
2338         struct sbridge_dev *sbridge_dev = NULL;
2339         const struct pci_id_descr *dev_descr = &table->descr[devno];
2340         struct pci_dev *pdev = NULL;
2341         int seg = 0;
2342         u8 bus = 0;
2343         int i = 0;
2344
2345         sbridge_printk(KERN_DEBUG,
2346                 "Seeking for: PCI ID %04x:%04x\n",
2347                 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2348
2349         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
2350                               dev_descr->dev_id, *prev);
2351
2352         if (!pdev) {
2353                 if (*prev) {
2354                         *prev = pdev;
2355                         return 0;
2356                 }
2357
2358                 if (dev_descr->optional)
2359                         return 0;
2360
2361                 /* if the HA wasn't found */
2362                 if (devno == 0)
2363                         return -ENODEV;
2364
2365                 sbridge_printk(KERN_INFO,
2366                         "Device not found: %04x:%04x\n",
2367                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2368
2369                 /* End of list, leave */
2370                 return -ENODEV;
2371         }
2372         seg = pci_domain_nr(pdev->bus);
2373         bus = pdev->bus->number;
2374
2375 next_imc:
2376         sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom,
2377                                       multi_bus, sbridge_dev);
2378         if (!sbridge_dev) {
2379                 /* If the HA1 wasn't found, don't create EDAC second memory controller */
2380                 if (dev_descr->dom == IMC1 && devno != 1) {
2381                         edac_dbg(0, "Skip IMC1: %04x:%04x (since HA1 was absent)\n",
2382                                  PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2383                         pci_dev_put(pdev);
2384                         return 0;
2385                 }
2386
2387                 if (dev_descr->dom == SOCK)
2388                         goto out_imc;
2389
2390                 sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table);
2391                 if (!sbridge_dev) {
2392                         pci_dev_put(pdev);
2393                         return -ENOMEM;
2394                 }
2395                 (*num_mc)++;
2396         }
2397
2398         if (sbridge_dev->pdev[sbridge_dev->i_devs]) {
2399                 sbridge_printk(KERN_ERR,
2400                         "Duplicated device for %04x:%04x\n",
2401                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2402                 pci_dev_put(pdev);
2403                 return -ENODEV;
2404         }
2405
2406         sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev;
2407
2408         /* pdev belongs to more than one IMC, do extra gets */
2409         if (++i > 1)
2410                 pci_dev_get(pdev);
2411
2412         if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock)
2413                 goto next_imc;
2414
2415 out_imc:
2416         /* Be sure that the device is enabled */
2417         if (unlikely(pci_enable_device(pdev) < 0)) {
2418                 sbridge_printk(KERN_ERR,
2419                         "Couldn't enable %04x:%04x\n",
2420                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2421                 return -ENODEV;
2422         }
2423
2424         edac_dbg(0, "Detected %04x:%04x\n",
2425                  PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2426
2427         /*
2428          * As stated on drivers/pci/search.c, the reference count for
2429          * @from is always decremented if it is not %NULL. So, as we need
2430          * to get all devices up to null, we need to do a get for the device
2431          */
2432         pci_dev_get(pdev);
2433
2434         *prev = pdev;
2435
2436         return 0;
2437 }
2438
2439 /*
2440  * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2441  *                           devices we want to reference for this driver.
2442  * @num_mc: pointer to the memory controllers count, to be incremented in case
2443  *          of success.
2444  * @table: model specific table
2445  *
2446  * returns 0 in case of success or error code
2447  */
2448 static int sbridge_get_all_devices(u8 *num_mc,
2449                                         const struct pci_id_table *table)
2450 {
2451         int i, rc;
2452         struct pci_dev *pdev = NULL;
2453         int allow_dups = 0;
2454         int multi_bus = 0;
2455
2456         if (table->type == KNIGHTS_LANDING)
2457                 allow_dups = multi_bus = 1;
2458         while (table && table->descr) {
2459                 for (i = 0; i < table->n_devs_per_sock; i++) {
2460                         if (!allow_dups || i == 0 ||
2461                                         table->descr[i].dev_id !=
2462                                                 table->descr[i-1].dev_id) {
2463                                 pdev = NULL;
2464                         }
2465                         do {
2466                                 rc = sbridge_get_onedevice(&pdev, num_mc,
2467                                                            table, i, multi_bus);
2468                                 if (rc < 0) {
2469                                         if (i == 0) {
2470                                                 i = table->n_devs_per_sock;
2471                                                 break;
2472                                         }
2473                                         sbridge_put_all_devices();
2474                                         return -ENODEV;
2475                                 }
2476                         } while (pdev && !allow_dups);
2477                 }
2478                 table++;
2479         }
2480
2481         return 0;
2482 }
2483
2484 /*
2485  * Device IDs for {SBRIDGE,IBRIDGE,HASWELL,BROADWELL}_IMC_HA0_TAD0 are in
2486  * the format: XXXa. So we can convert from a device to the corresponding
2487  * channel like this
2488  */
2489 #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa)
2490
2491 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
2492                                  struct sbridge_dev *sbridge_dev)
2493 {
2494         struct sbridge_pvt *pvt = mci->pvt_info;
2495         struct pci_dev *pdev;
2496         u8 saw_chan_mask = 0;
2497         int i;
2498
2499         for (i = 0; i < sbridge_dev->n_devs; i++) {
2500                 pdev = sbridge_dev->pdev[i];
2501                 if (!pdev)
2502                         continue;
2503
2504                 switch (pdev->device) {
2505                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
2506                         pvt->pci_sad0 = pdev;
2507                         break;
2508                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
2509                         pvt->pci_sad1 = pdev;
2510                         break;
2511                 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
2512                         pvt->pci_br0 = pdev;
2513                         break;
2514                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2515                         pvt->pci_ha = pdev;
2516                         break;
2517                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
2518                         pvt->pci_ta = pdev;
2519                         break;
2520                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
2521                         pvt->pci_ras = pdev;
2522                         break;
2523                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
2524                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
2525                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
2526                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
2527                 {
2528                         int id = TAD_DEV_TO_CHAN(pdev->device);
2529                         pvt->pci_tad[id] = pdev;
2530                         saw_chan_mask |= 1 << id;
2531                 }
2532                         break;
2533                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
2534                         pvt->pci_ddrio = pdev;
2535                         break;
2536                 default:
2537                         goto error;
2538                 }
2539
2540                 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
2541                          pdev->vendor, pdev->device,
2542                          sbridge_dev->bus,
2543                          pdev);
2544         }
2545
2546         /* Check if everything were registered */
2547         if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha ||
2548             !pvt->pci_ras || !pvt->pci_ta)
2549                 goto enodev;
2550
2551         if (saw_chan_mask != 0x0f)
2552                 goto enodev;
2553         return 0;
2554
2555 enodev:
2556         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2557         return -ENODEV;
2558
2559 error:
2560         sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
2561                        PCI_VENDOR_ID_INTEL, pdev->device);
2562         return -EINVAL;
2563 }
2564
2565 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
2566                                  struct sbridge_dev *sbridge_dev)
2567 {
2568         struct sbridge_pvt *pvt = mci->pvt_info;
2569         struct pci_dev *pdev;
2570         u8 saw_chan_mask = 0;
2571         int i;
2572
2573         for (i = 0; i < sbridge_dev->n_devs; i++) {
2574                 pdev = sbridge_dev->pdev[i];
2575                 if (!pdev)
2576                         continue;
2577
2578                 switch (pdev->device) {
2579                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
2580                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
2581                         pvt->pci_ha = pdev;
2582                         break;
2583                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2584                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA:
2585                         pvt->pci_ta = pdev;
2586                         break;
2587                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
2588                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS:
2589                         pvt->pci_ras = pdev;
2590                         break;
2591                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
2592                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
2593                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
2594                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
2595                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
2596                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
2597                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
2598                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
2599                 {
2600                         int id = TAD_DEV_TO_CHAN(pdev->device);
2601                         pvt->pci_tad[id] = pdev;
2602                         saw_chan_mask |= 1 << id;
2603                 }
2604                         break;
2605                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
2606                         pvt->pci_ddrio = pdev;
2607                         break;
2608                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
2609                         pvt->pci_ddrio = pdev;
2610                         break;
2611                 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
2612                         pvt->pci_sad0 = pdev;
2613                         break;
2614                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
2615                         pvt->pci_br0 = pdev;
2616                         break;
2617                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
2618                         pvt->pci_br1 = pdev;
2619                         break;
2620                 default:
2621                         goto error;
2622                 }
2623
2624                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2625                          sbridge_dev->bus,
2626                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2627                          pdev);
2628         }
2629
2630         /* Check if everything were registered */
2631         if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 ||
2632             !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta)
2633                 goto enodev;
2634
2635         if (saw_chan_mask != 0x0f && /* -EN/-EX */
2636             saw_chan_mask != 0x03)   /* -EP */
2637                 goto enodev;
2638         return 0;
2639
2640 enodev:
2641         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2642         return -ENODEV;
2643
2644 error:
2645         sbridge_printk(KERN_ERR,
2646                        "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
2647                         pdev->device);
2648         return -EINVAL;
2649 }
2650
2651 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
2652                                  struct sbridge_dev *sbridge_dev)
2653 {
2654         struct sbridge_pvt *pvt = mci->pvt_info;
2655         struct pci_dev *pdev;
2656         u8 saw_chan_mask = 0;
2657         int i;
2658
2659         /* there's only one device per system; not tied to any bus */
2660         if (pvt->info.pci_vtd == NULL)
2661                 /* result will be checked later */
2662                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2663                                                    PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
2664                                                    NULL);
2665
2666         for (i = 0; i < sbridge_dev->n_devs; i++) {
2667                 pdev = sbridge_dev->pdev[i];
2668                 if (!pdev)
2669                         continue;
2670
2671                 switch (pdev->device) {
2672                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
2673                         pvt->pci_sad0 = pdev;
2674                         break;
2675                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
2676                         pvt->pci_sad1 = pdev;
2677                         break;
2678                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2679                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
2680                         pvt->pci_ha = pdev;
2681                         break;
2682                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
2683                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
2684                         pvt->pci_ta = pdev;
2685                         break;
2686                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM:
2687                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM:
2688                         pvt->pci_ras = pdev;
2689                         break;
2690                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
2691                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
2692                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
2693                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
2694                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
2695                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
2696                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
2697                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
2698                 {
2699                         int id = TAD_DEV_TO_CHAN(pdev->device);
2700                         pvt->pci_tad[id] = pdev;
2701                         saw_chan_mask |= 1 << id;
2702                 }
2703                         break;
2704                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
2705                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
2706                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
2707                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
2708                         if (!pvt->pci_ddrio)
2709                                 pvt->pci_ddrio = pdev;
2710                         break;
2711                 default:
2712                         break;
2713                 }
2714
2715                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2716                          sbridge_dev->bus,
2717                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2718                          pdev);
2719         }
2720
2721         /* Check if everything were registered */
2722         if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2723             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2724                 goto enodev;
2725
2726         if (saw_chan_mask != 0x0f && /* -EN/-EX */
2727             saw_chan_mask != 0x03)   /* -EP */
2728                 goto enodev;
2729         return 0;
2730
2731 enodev:
2732         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2733         return -ENODEV;
2734 }
2735
2736 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
2737                                  struct sbridge_dev *sbridge_dev)
2738 {
2739         struct sbridge_pvt *pvt = mci->pvt_info;
2740         struct pci_dev *pdev;
2741         u8 saw_chan_mask = 0;
2742         int i;
2743
2744         /* there's only one device per system; not tied to any bus */
2745         if (pvt->info.pci_vtd == NULL)
2746                 /* result will be checked later */
2747                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2748                                                    PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
2749                                                    NULL);
2750
2751         for (i = 0; i < sbridge_dev->n_devs; i++) {
2752                 pdev = sbridge_dev->pdev[i];
2753                 if (!pdev)
2754                         continue;
2755
2756                 switch (pdev->device) {
2757                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
2758                         pvt->pci_sad0 = pdev;
2759                         break;
2760                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
2761                         pvt->pci_sad1 = pdev;
2762                         break;
2763                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2764                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2765                         pvt->pci_ha = pdev;
2766                         break;
2767                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2768                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2769                         pvt->pci_ta = pdev;
2770                         break;
2771                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM:
2772                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM:
2773                         pvt->pci_ras = pdev;
2774                         break;
2775                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
2776                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
2777                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
2778                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
2779                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
2780                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
2781                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
2782                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
2783                 {
2784                         int id = TAD_DEV_TO_CHAN(pdev->device);
2785                         pvt->pci_tad[id] = pdev;
2786                         saw_chan_mask |= 1 << id;
2787                 }
2788                         break;
2789                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2790                         pvt->pci_ddrio = pdev;
2791                         break;
2792                 default:
2793                         break;
2794                 }
2795
2796                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2797                          sbridge_dev->bus,
2798                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2799                          pdev);
2800         }
2801
2802         /* Check if everything were registered */
2803         if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2804             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2805                 goto enodev;
2806
2807         if (saw_chan_mask != 0x0f && /* -EN/-EX */
2808             saw_chan_mask != 0x03)   /* -EP */
2809                 goto enodev;
2810         return 0;
2811
2812 enodev:
2813         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2814         return -ENODEV;
2815 }
2816
2817 static int knl_mci_bind_devs(struct mem_ctl_info *mci,
2818                         struct sbridge_dev *sbridge_dev)
2819 {
2820         struct sbridge_pvt *pvt = mci->pvt_info;
2821         struct pci_dev *pdev;
2822         int dev, func;
2823
2824         int i;
2825         int devidx;
2826
2827         for (i = 0; i < sbridge_dev->n_devs; i++) {
2828                 pdev = sbridge_dev->pdev[i];
2829                 if (!pdev)
2830                         continue;
2831
2832                 /* Extract PCI device and function. */
2833                 dev = (pdev->devfn >> 3) & 0x1f;
2834                 func = pdev->devfn & 0x7;
2835
2836                 switch (pdev->device) {
2837                 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:
2838                         if (dev == 8)
2839                                 pvt->knl.pci_mc0 = pdev;
2840                         else if (dev == 9)
2841                                 pvt->knl.pci_mc1 = pdev;
2842                         else {
2843                                 sbridge_printk(KERN_ERR,
2844                                         "Memory controller in unexpected place! (dev %d, fn %d)\n",
2845                                         dev, func);
2846                                 continue;
2847                         }
2848                         break;
2849
2850                 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
2851                         pvt->pci_sad0 = pdev;
2852                         break;
2853
2854                 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:
2855                         pvt->pci_sad1 = pdev;
2856                         break;
2857
2858                 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:
2859                         /* There are one of these per tile, and range from
2860                          * 1.14.0 to 1.18.5.
2861                          */
2862                         devidx = ((dev-14)*8)+func;
2863
2864                         if (devidx < 0 || devidx >= KNL_MAX_CHAS) {
2865                                 sbridge_printk(KERN_ERR,
2866                                         "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n",
2867                                         dev, func);
2868                                 continue;
2869                         }
2870
2871                         WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2872
2873                         pvt->knl.pci_cha[devidx] = pdev;
2874                         break;
2875
2876                 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN:
2877                         devidx = -1;
2878
2879                         /*
2880                          *  MC0 channels 0-2 are device 9 function 2-4,
2881                          *  MC1 channels 3-5 are device 8 function 2-4.
2882                          */
2883
2884                         if (dev == 9)
2885                                 devidx = func-2;
2886                         else if (dev == 8)
2887                                 devidx = 3 + (func-2);
2888
2889                         if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {
2890                                 sbridge_printk(KERN_ERR,
2891                                         "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n",
2892                                         dev, func);
2893                                 continue;
2894                         }
2895
2896                         WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
2897                         pvt->knl.pci_channel[devidx] = pdev;
2898                         break;
2899
2900                 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:
2901                         pvt->knl.pci_mc_info = pdev;
2902                         break;
2903
2904                 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:
2905                         pvt->pci_ta = pdev;
2906                         break;
2907
2908                 default:
2909                         sbridge_printk(KERN_ERR, "Unexpected device %d\n",
2910                                 pdev->device);
2911                         break;
2912                 }
2913         }
2914
2915         if (!pvt->knl.pci_mc0  || !pvt->knl.pci_mc1 ||
2916             !pvt->pci_sad0     || !pvt->pci_sad1    ||
2917             !pvt->pci_ta) {
2918                 goto enodev;
2919         }
2920
2921         for (i = 0; i < KNL_MAX_CHANNELS; i++) {
2922                 if (!pvt->knl.pci_channel[i]) {
2923                         sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
2924                         goto enodev;
2925                 }
2926         }
2927
2928         for (i = 0; i < KNL_MAX_CHAS; i++) {
2929                 if (!pvt->knl.pci_cha[i]) {
2930                         sbridge_printk(KERN_ERR, "Missing CHA %d\n", i);
2931                         goto enodev;
2932                 }
2933         }
2934
2935         return 0;
2936
2937 enodev:
2938         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2939         return -ENODEV;
2940 }
2941
2942 /****************************************************************************
2943                         Error check routines
2944  ****************************************************************************/
2945
2946 /*
2947  * While Sandy Bridge has error count registers, SMI BIOS read values from
2948  * and resets the counters. So, they are not reliable for the OS to read
2949  * from them. So, we have no option but to just trust on whatever MCE is
2950  * telling us about the errors.
2951  */
2952 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2953                                     const struct mce *m)
2954 {
2955         struct mem_ctl_info *new_mci;
2956         struct sbridge_pvt *pvt = mci->pvt_info;
2957         enum hw_event_mc_err_type tp_event;
2958         char *type, *optype, msg[256];
2959         bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2960         bool overflow = GET_BITFIELD(m->status, 62, 62);
2961         bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2962         bool recoverable;
2963         u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2964         u32 mscod = GET_BITFIELD(m->status, 16, 31);
2965         u32 errcode = GET_BITFIELD(m->status, 0, 15);
2966         u32 channel = GET_BITFIELD(m->status, 0, 3);
2967         u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2968         /*
2969          * Bits 5-0 of MCi_MISC give the least significant bit that is valid.
2970          * A value 6 is for cache line aligned address, a value 12 is for page
2971          * aligned address reported by patrol scrubber.
2972          */
2973         u32 lsb = GET_BITFIELD(m->misc, 0, 5);
2974         long channel_mask, first_channel;
2975         u8  rank = 0xff, socket, ha;
2976         int rc, dimm;
2977         char *area_type = "DRAM";
2978
2979         if (pvt->info.type != SANDY_BRIDGE)
2980                 recoverable = true;
2981         else
2982                 recoverable = GET_BITFIELD(m->status, 56, 56);
2983
2984         if (uncorrected_error) {
2985                 core_err_cnt = 1;
2986                 if (ripv) {
2987                         type = "FATAL";
2988                         tp_event = HW_EVENT_ERR_FATAL;
2989                 } else {
2990                         type = "NON_FATAL";
2991                         tp_event = HW_EVENT_ERR_UNCORRECTED;
2992                 }
2993         } else {
2994                 type = "CORRECTED";
2995                 tp_event = HW_EVENT_ERR_CORRECTED;
2996         }
2997
2998         /*
2999          * According with Table 15-9 of the Intel Architecture spec vol 3A,
3000          * memory errors should fit in this mask:
3001          *      000f 0000 1mmm cccc (binary)
3002          * where:
3003          *      f = Correction Report Filtering Bit. If 1, subsequent errors
3004          *          won't be shown
3005          *      mmm = error type
3006          *      cccc = channel
3007          * If the mask doesn't match, report an error to the parsing logic
3008          */
3009         switch (optypenum) {
3010         case 0:
3011                 optype = "generic undef request error";
3012                 break;
3013         case 1:
3014                 optype = "memory read error";
3015                 break;
3016         case 2:
3017                 optype = "memory write error";
3018                 break;
3019         case 3:
3020                 optype = "addr/cmd error";
3021                 break;
3022         case 4:
3023                 optype = "memory scrubbing error";
3024                 break;
3025         default:
3026                 optype = "reserved";
3027                 break;
3028         }
3029
3030         if (pvt->info.type == KNIGHTS_LANDING) {
3031                 if (channel == 14) {
3032                         edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
3033                                 overflow ? " OVERFLOW" : "",
3034                                 (uncorrected_error && recoverable)
3035                                 ? " recoverable" : "",
3036                                 mscod, errcode,
3037                                 m->bank);
3038                 } else {
3039                         char A = *("A");
3040
3041                         /*
3042                          * Reported channel is in range 0-2, so we can't map it
3043                          * back to mc. To figure out mc we check machine check
3044                          * bank register that reported this error.
3045                          * bank15 means mc0 and bank16 means mc1.
3046                          */
3047                         channel = knl_channel_remap(m->bank == 16, channel);
3048                         channel_mask = 1 << channel;
3049
3050                         snprintf(msg, sizeof(msg),
3051                                 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
3052                                 overflow ? " OVERFLOW" : "",
3053                                 (uncorrected_error && recoverable)
3054                                 ? " recoverable" : " ",
3055                                 mscod, errcode, channel, A + channel);
3056                         edac_mc_handle_error(tp_event, mci, core_err_cnt,
3057                                 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3058                                 channel, 0, -1,
3059                                 optype, msg);
3060                 }
3061                 return;
3062         } else if (lsb < 12) {
3063                 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
3064                                            &channel_mask, &rank,
3065                                            &area_type, msg);
3066         } else {
3067                 rc = get_memory_error_data_from_mce(mci, m, &socket, &ha,
3068                                                     &channel_mask, msg);
3069         }
3070
3071         if (rc < 0)
3072                 goto err_parsing;
3073         new_mci = get_mci_for_node_id(socket, ha);
3074         if (!new_mci) {
3075                 strcpy(msg, "Error: socket got corrupted!");
3076                 goto err_parsing;
3077         }
3078         mci = new_mci;
3079         pvt = mci->pvt_info;
3080
3081         first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
3082
3083         if (rank == 0xff)
3084                 dimm = -1;
3085         else if (rank < 4)
3086                 dimm = 0;
3087         else if (rank < 8)
3088                 dimm = 1;
3089         else
3090                 dimm = 2;
3091
3092         /*
3093          * FIXME: On some memory configurations (mirror, lockstep), the
3094          * Memory Controller can't point the error to a single DIMM. The
3095          * EDAC core should be handling the channel mask, in order to point
3096          * to the group of dimm's where the error may be happening.
3097          */
3098         if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg)
3099                 channel = first_channel;
3100
3101         snprintf(msg, sizeof(msg),
3102                  "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
3103                  overflow ? " OVERFLOW" : "",
3104                  (uncorrected_error && recoverable) ? " recoverable" : "",
3105                  area_type,
3106                  mscod, errcode,
3107                  socket, ha,
3108                  channel_mask,
3109                  rank);
3110
3111         edac_dbg(0, "%s\n", msg);
3112
3113         /* FIXME: need support for channel mask */
3114
3115         if (channel == CHANNEL_UNSPECIFIED)
3116                 channel = -1;
3117
3118         /* Call the helper to output message */
3119         edac_mc_handle_error(tp_event, mci, core_err_cnt,
3120                              m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3121                              channel, dimm, -1,
3122                              optype, msg);
3123         return;
3124 err_parsing:
3125         edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
3126                              -1, -1, -1,
3127                              msg, "");
3128
3129 }
3130
3131 /*
3132  * Check that logging is enabled and that this is the right type
3133  * of error for us to handle.
3134  */
3135 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
3136                                    void *data)
3137 {
3138         struct mce *mce = (struct mce *)data;
3139         struct mem_ctl_info *mci;
3140         char *type;
3141
3142         if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
3143                 return NOTIFY_DONE;
3144
3145         /*
3146          * Just let mcelog handle it if the error is
3147          * outside the memory controller. A memory error
3148          * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
3149          * bit 12 has an special meaning.
3150          */
3151         if ((mce->status & 0xefff) >> 7 != 1)
3152                 return NOTIFY_DONE;
3153
3154         /* Check ADDRV bit in STATUS */
3155         if (!GET_BITFIELD(mce->status, 58, 58))
3156                 return NOTIFY_DONE;
3157
3158         /* Check MISCV bit in STATUS */
3159         if (!GET_BITFIELD(mce->status, 59, 59))
3160                 return NOTIFY_DONE;
3161
3162         /* Check address type in MISC (physical address only) */
3163         if (GET_BITFIELD(mce->misc, 6, 8) != 2)
3164                 return NOTIFY_DONE;
3165
3166         mci = get_mci_for_node_id(mce->socketid, IMC0);
3167         if (!mci)
3168                 return NOTIFY_DONE;
3169
3170         if (mce->mcgstatus & MCG_STATUS_MCIP)
3171                 type = "Exception";
3172         else
3173                 type = "Event";
3174
3175         sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
3176
3177         sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
3178                           "Bank %d: %016Lx\n", mce->extcpu, type,
3179                           mce->mcgstatus, mce->bank, mce->status);
3180         sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
3181         sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
3182         sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
3183
3184         sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
3185                           "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
3186                           mce->time, mce->socketid, mce->apicid);
3187
3188         sbridge_mce_output_error(mci, mce);
3189
3190         /* Advice mcelog that the error were handled */
3191         return NOTIFY_STOP;
3192 }
3193
3194 static struct notifier_block sbridge_mce_dec = {
3195         .notifier_call  = sbridge_mce_check_error,
3196         .priority       = MCE_PRIO_EDAC,
3197 };
3198
3199 /****************************************************************************
3200                         EDAC register/unregister logic
3201  ****************************************************************************/
3202
3203 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
3204 {
3205         struct mem_ctl_info *mci = sbridge_dev->mci;
3206         struct sbridge_pvt *pvt;
3207
3208         if (unlikely(!mci || !mci->pvt_info)) {
3209                 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
3210
3211                 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
3212                 return;
3213         }
3214
3215         pvt = mci->pvt_info;
3216
3217         edac_dbg(0, "MC: mci = %p, dev = %p\n",
3218                  mci, &sbridge_dev->pdev[0]->dev);
3219
3220         /* Remove MC sysfs nodes */
3221         edac_mc_del_mc(mci->pdev);
3222
3223         edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
3224         kfree(mci->ctl_name);
3225         edac_mc_free(mci);
3226         sbridge_dev->mci = NULL;
3227 }
3228
3229 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
3230 {
3231         struct mem_ctl_info *mci;
3232         struct edac_mc_layer layers[2];
3233         struct sbridge_pvt *pvt;
3234         struct pci_dev *pdev = sbridge_dev->pdev[0];
3235         int rc;
3236
3237         /* allocate a new MC control structure */
3238         layers[0].type = EDAC_MC_LAYER_CHANNEL;
3239         layers[0].size = type == KNIGHTS_LANDING ?
3240                 KNL_MAX_CHANNELS : NUM_CHANNELS;
3241         layers[0].is_virt_csrow = false;
3242         layers[1].type = EDAC_MC_LAYER_SLOT;
3243         layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
3244         layers[1].is_virt_csrow = true;
3245         mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
3246                             sizeof(*pvt));
3247
3248         if (unlikely(!mci))
3249                 return -ENOMEM;
3250
3251         edac_dbg(0, "MC: mci = %p, dev = %p\n",
3252                  mci, &pdev->dev);
3253
3254         pvt = mci->pvt_info;
3255         memset(pvt, 0, sizeof(*pvt));
3256
3257         /* Associate sbridge_dev and mci for future usage */
3258         pvt->sbridge_dev = sbridge_dev;
3259         sbridge_dev->mci = mci;
3260
3261         mci->mtype_cap = type == KNIGHTS_LANDING ?
3262                 MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
3263         mci->edac_ctl_cap = EDAC_FLAG_NONE;
3264         mci->edac_cap = EDAC_FLAG_NONE;
3265         mci->mod_name = EDAC_MOD_STR;
3266         mci->dev_name = pci_name(pdev);
3267         mci->ctl_page_to_phys = NULL;
3268
3269         pvt->info.type = type;
3270         switch (type) {
3271         case IVY_BRIDGE:
3272                 pvt->info.rankcfgr = IB_RANK_CFG_A;
3273                 pvt->info.get_tolm = ibridge_get_tolm;
3274                 pvt->info.get_tohm = ibridge_get_tohm;
3275                 pvt->info.dram_rule = ibridge_dram_rule;
3276                 pvt->info.get_memory_type = get_memory_type;
3277                 pvt->info.get_node_id = get_node_id;
3278                 pvt->info.get_ha = ibridge_get_ha;
3279                 pvt->info.rir_limit = rir_limit;
3280                 pvt->info.sad_limit = sad_limit;
3281                 pvt->info.interleave_mode = interleave_mode;
3282                 pvt->info.dram_attr = dram_attr;
3283                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3284                 pvt->info.interleave_list = ibridge_interleave_list;
3285                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3286                 pvt->info.get_width = ibridge_get_width;
3287
3288                 /* Store pci devices at mci for faster access */
3289                 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
3290                 if (unlikely(rc < 0))
3291                         goto fail0;
3292                 get_source_id(mci);
3293                 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d",
3294                         pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3295                 break;
3296         case SANDY_BRIDGE:
3297                 pvt->info.rankcfgr = SB_RANK_CFG_A;
3298                 pvt->info.get_tolm = sbridge_get_tolm;
3299                 pvt->info.get_tohm = sbridge_get_tohm;
3300                 pvt->info.dram_rule = sbridge_dram_rule;
3301                 pvt->info.get_memory_type = get_memory_type;
3302                 pvt->info.get_node_id = get_node_id;
3303                 pvt->info.get_ha = sbridge_get_ha;
3304                 pvt->info.rir_limit = rir_limit;
3305                 pvt->info.sad_limit = sad_limit;
3306                 pvt->info.interleave_mode = interleave_mode;
3307                 pvt->info.dram_attr = dram_attr;
3308                 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3309                 pvt->info.interleave_list = sbridge_interleave_list;
3310                 pvt->info.interleave_pkg = sbridge_interleave_pkg;
3311                 pvt->info.get_width = sbridge_get_width;
3312
3313                 /* Store pci devices at mci for faster access */
3314                 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
3315                 if (unlikely(rc < 0))
3316                         goto fail0;
3317                 get_source_id(mci);
3318                 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d",
3319                         pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3320                 break;
3321         case HASWELL:
3322                 /* rankcfgr isn't used */
3323                 pvt->info.get_tolm = haswell_get_tolm;
3324                 pvt->info.get_tohm = haswell_get_tohm;
3325                 pvt->info.dram_rule = ibridge_dram_rule;
3326                 pvt->info.get_memory_type = haswell_get_memory_type;
3327                 pvt->info.get_node_id = haswell_get_node_id;
3328                 pvt->info.get_ha = ibridge_get_ha;
3329                 pvt->info.rir_limit = haswell_rir_limit;
3330                 pvt->info.sad_limit = sad_limit;
3331                 pvt->info.interleave_mode = interleave_mode;
3332                 pvt->info.dram_attr = dram_attr;
3333                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3334                 pvt->info.interleave_list = ibridge_interleave_list;
3335                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3336                 pvt->info.get_width = ibridge_get_width;
3337
3338                 /* Store pci devices at mci for faster access */
3339                 rc = haswell_mci_bind_devs(mci, sbridge_dev);
3340                 if (unlikely(rc < 0))
3341                         goto fail0;
3342                 get_source_id(mci);
3343                 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d",
3344                         pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3345                 break;
3346         case BROADWELL:
3347                 /* rankcfgr isn't used */
3348                 pvt->info.get_tolm = haswell_get_tolm;
3349                 pvt->info.get_tohm = haswell_get_tohm;
3350                 pvt->info.dram_rule = ibridge_dram_rule;
3351                 pvt->info.get_memory_type = haswell_get_memory_type;
3352                 pvt->info.get_node_id = haswell_get_node_id;
3353                 pvt->info.get_ha = ibridge_get_ha;
3354                 pvt->info.rir_limit = haswell_rir_limit;
3355                 pvt->info.sad_limit = sad_limit;
3356                 pvt->info.interleave_mode = interleave_mode;
3357                 pvt->info.dram_attr = dram_attr;
3358                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3359                 pvt->info.interleave_list = ibridge_interleave_list;
3360                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3361                 pvt->info.get_width = broadwell_get_width;
3362
3363                 /* Store pci devices at mci for faster access */
3364                 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
3365                 if (unlikely(rc < 0))
3366                         goto fail0;
3367                 get_source_id(mci);
3368                 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d",
3369                         pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3370                 break;
3371         case KNIGHTS_LANDING:
3372                 /* pvt->info.rankcfgr == ??? */
3373                 pvt->info.get_tolm = knl_get_tolm;
3374                 pvt->info.get_tohm = knl_get_tohm;
3375                 pvt->info.dram_rule = knl_dram_rule;
3376                 pvt->info.get_memory_type = knl_get_memory_type;
3377                 pvt->info.get_node_id = knl_get_node_id;
3378                 pvt->info.get_ha = knl_get_ha;
3379                 pvt->info.rir_limit = NULL;
3380                 pvt->info.sad_limit = knl_sad_limit;
3381                 pvt->info.interleave_mode = knl_interleave_mode;
3382                 pvt->info.dram_attr = dram_attr_knl;
3383                 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3384                 pvt->info.interleave_list = knl_interleave_list;
3385                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3386                 pvt->info.get_width = knl_get_width;
3387
3388                 rc = knl_mci_bind_devs(mci, sbridge_dev);
3389                 if (unlikely(rc < 0))
3390                         goto fail0;
3391                 get_source_id(mci);
3392                 mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d",
3393                         pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3394                 break;
3395         }
3396
3397         if (!mci->ctl_name) {
3398                 rc = -ENOMEM;
3399                 goto fail0;
3400         }
3401
3402         /* Get dimm basic config and the memory layout */
3403         rc = get_dimm_config(mci);
3404         if (rc < 0) {
3405                 edac_dbg(0, "MC: failed to get_dimm_config()\n");
3406                 goto fail;
3407         }
3408         get_memory_layout(mci);
3409
3410         /* record ptr to the generic device */
3411         mci->pdev = &pdev->dev;
3412
3413         /* add this new MC control structure to EDAC's list of MCs */
3414         if (unlikely(edac_mc_add_mc(mci))) {
3415                 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
3416                 rc = -EINVAL;
3417                 goto fail;
3418         }
3419
3420         return 0;
3421
3422 fail:
3423         kfree(mci->ctl_name);
3424 fail0:
3425         edac_mc_free(mci);
3426         sbridge_dev->mci = NULL;
3427         return rc;
3428 }
3429
3430 static const struct x86_cpu_id sbridge_cpuids[] = {
3431         INTEL_CPU_FAM6(SANDYBRIDGE_X,     pci_dev_descr_sbridge_table),
3432         INTEL_CPU_FAM6(IVYBRIDGE_X,       pci_dev_descr_ibridge_table),
3433         INTEL_CPU_FAM6(HASWELL_X,         pci_dev_descr_haswell_table),
3434         INTEL_CPU_FAM6(BROADWELL_X,       pci_dev_descr_broadwell_table),
3435         INTEL_CPU_FAM6(BROADWELL_XEON_D,  pci_dev_descr_broadwell_table),
3436         INTEL_CPU_FAM6(XEON_PHI_KNL,      pci_dev_descr_knl_table),
3437         INTEL_CPU_FAM6(XEON_PHI_KNM,      pci_dev_descr_knl_table),
3438         { }
3439 };
3440 MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids);
3441
3442 /*
3443  *      sbridge_probe   Get all devices and register memory controllers
3444  *                      present.
3445  *      return:
3446  *              0 for FOUND a device
3447  *              < 0 for error code
3448  */
3449
3450 static int sbridge_probe(const struct x86_cpu_id *id)
3451 {
3452         int rc = -ENODEV;
3453         u8 mc, num_mc = 0;
3454         struct sbridge_dev *sbridge_dev;
3455         struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data;
3456
3457         /* get the pci devices we want to reserve for our use */
3458         rc = sbridge_get_all_devices(&num_mc, ptable);
3459
3460         if (unlikely(rc < 0)) {
3461                 edac_dbg(0, "couldn't get all devices\n");
3462                 goto fail0;
3463         }
3464
3465         mc = 0;
3466
3467         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
3468                 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
3469                          mc, mc + 1, num_mc);
3470
3471                 sbridge_dev->mc = mc++;
3472                 rc = sbridge_register_mci(sbridge_dev, ptable->type);
3473                 if (unlikely(rc < 0))
3474                         goto fail1;
3475         }
3476
3477         sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
3478
3479         return 0;
3480
3481 fail1:
3482         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3483                 sbridge_unregister_mci(sbridge_dev);
3484
3485         sbridge_put_all_devices();
3486 fail0:
3487         return rc;
3488 }
3489
3490 /*
3491  *      sbridge_remove  cleanup
3492  *
3493  */
3494 static void sbridge_remove(void)
3495 {
3496         struct sbridge_dev *sbridge_dev;
3497
3498         edac_dbg(0, "\n");
3499
3500         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3501                 sbridge_unregister_mci(sbridge_dev);
3502
3503         /* Release PCI resources */
3504         sbridge_put_all_devices();
3505 }
3506
3507 /*
3508  *      sbridge_init            Module entry function
3509  *                      Try to initialize this module for its devices
3510  */
3511 static int __init sbridge_init(void)
3512 {
3513         const struct x86_cpu_id *id;
3514         const char *owner;
3515         int rc;
3516
3517         edac_dbg(2, "\n");
3518
3519         owner = edac_get_owner();
3520         if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
3521                 return -EBUSY;
3522
3523         id = x86_match_cpu(sbridge_cpuids);
3524         if (!id)
3525                 return -ENODEV;
3526
3527         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
3528         opstate_init();
3529
3530         rc = sbridge_probe(id);
3531
3532         if (rc >= 0) {
3533                 mce_register_decode_chain(&sbridge_mce_dec);
3534                 if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
3535                         sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
3536                 return 0;
3537         }
3538
3539         sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
3540                       rc);
3541
3542         return rc;
3543 }
3544
3545 /*
3546  *      sbridge_exit()  Module exit function
3547  *                      Unregister the driver
3548  */
3549 static void __exit sbridge_exit(void)
3550 {
3551         edac_dbg(2, "\n");
3552         sbridge_remove();
3553         mce_unregister_decode_chain(&sbridge_mce_dec);
3554 }
3555
3556 module_init(sbridge_init);
3557 module_exit(sbridge_exit);
3558
3559 module_param(edac_op_state, int, 0444);
3560 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
3561
3562 MODULE_LICENSE("GPL");
3563 MODULE_AUTHOR("Mauro Carvalho Chehab");
3564 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
3565 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
3566                    SBRIDGE_REVISION);