1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Intel client SoC with integrated memory controller using IBECC
5 * Copyright (C) 2020 Intel Corporation
7 * The In-Band ECC (IBECC) IP provides ECC protection to all or specific
8 * regions of the physical memory space. It's used for memory controllers
9 * that don't support the out-of-band ECC which often needs an additional
10 * storage device to each channel for storing ECC data.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/slab.h>
17 #include <linux/irq_work.h>
18 #include <linux/llist.h>
19 #include <linux/genalloc.h>
20 #include <linux/edac.h>
21 #include <linux/bits.h>
23 #include <asm/mach_traps.h>
28 #include "edac_module.h"
30 #define IGEN6_REVISION "v2.5.1"
32 #define EDAC_MOD_STR "igen6_edac"
33 #define IGEN6_NMI_NAME "igen6_ibecc"
36 #define igen6_printk(level, fmt, arg...) \
37 edac_printk(level, "igen6", fmt, ##arg)
39 #define igen6_mc_printk(mci, level, fmt, arg...) \
40 edac_mc_chipset_printk(mci, level, "igen6", fmt, ##arg)
42 #define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo))
44 #define NUM_IMC 2 /* Max memory controllers */
45 #define NUM_CHANNELS 2 /* Max channels */
46 #define NUM_DIMMS 2 /* Max DIMMs per channel */
48 #define _4GB BIT_ULL(32)
50 /* Size of physical memory */
51 #define TOM_OFFSET 0xa0
52 /* Top of low usable DRAM */
53 #define TOLUD_OFFSET 0xbc
54 /* Capability register C */
55 #define CAPID_C_OFFSET 0xec
56 #define CAPID_C_IBECC BIT(15)
58 /* Capability register E */
59 #define CAPID_E_OFFSET 0xf0
60 #define CAPID_E_IBECC BIT(12)
61 #define CAPID_E_IBECC_BIT18 BIT(18)
64 #define ERRSTS_OFFSET 0xc8
65 #define ERRSTS_CE BIT_ULL(6)
66 #define ERRSTS_UE BIT_ULL(7)
69 #define ERRCMD_OFFSET 0xca
70 #define ERRCMD_CE BIT_ULL(6)
71 #define ERRCMD_UE BIT_ULL(7)
73 /* IBECC MMIO base address */
74 #define IBECC_BASE (res_cfg->ibecc_base)
75 #define IBECC_ACTIVATE_OFFSET IBECC_BASE
76 #define IBECC_ACTIVATE_EN BIT(0)
79 #define ECC_ERROR_LOG_OFFSET (IBECC_BASE + res_cfg->ibecc_error_log_offset)
80 #define ECC_ERROR_LOG_CE BIT_ULL(62)
81 #define ECC_ERROR_LOG_UE BIT_ULL(63)
82 #define ECC_ERROR_LOG_ADDR_SHIFT 5
83 #define ECC_ERROR_LOG_ADDR(v) GET_BITFIELD(v, 5, 38)
84 #define ECC_ERROR_LOG_ADDR45(v) GET_BITFIELD(v, 5, 45)
85 #define ECC_ERROR_LOG_SYND(v) GET_BITFIELD(v, 46, 61)
87 /* Host MMIO base address */
88 #define MCHBAR_OFFSET 0x48
89 #define MCHBAR_EN BIT_ULL(0)
90 #define MCHBAR_BASE(v) (GET_BITFIELD(v, 16, 38) << 16)
91 #define MCHBAR_SIZE 0x10000
93 /* Parameters for the channel decode stage */
94 #define IMC_BASE (res_cfg->imc_base)
95 #define MAD_INTER_CHANNEL_OFFSET IMC_BASE
96 #define MAD_INTER_CHANNEL_DDR_TYPE(v) GET_BITFIELD(v, 0, 2)
97 #define MAD_INTER_CHANNEL_ECHM(v) GET_BITFIELD(v, 3, 3)
98 #define MAD_INTER_CHANNEL_CH_L_MAP(v) GET_BITFIELD(v, 4, 4)
99 #define MAD_INTER_CHANNEL_CH_S_SIZE(v) ((u64)GET_BITFIELD(v, 12, 19) << 29)
101 /* Parameters for DRAM decode stage */
102 #define MAD_INTRA_CH0_OFFSET (IMC_BASE + 4)
103 #define MAD_INTRA_CH_DIMM_L_MAP(v) GET_BITFIELD(v, 0, 0)
105 /* DIMM characteristics */
106 #define MAD_DIMM_CH0_OFFSET (IMC_BASE + 0xc)
107 #define MAD_DIMM_CH_DIMM_L_SIZE(v) ((u64)GET_BITFIELD(v, 0, 6) << 29)
108 #define MAD_DIMM_CH_DLW(v) GET_BITFIELD(v, 7, 8)
109 #define MAD_DIMM_CH_DIMM_S_SIZE(v) ((u64)GET_BITFIELD(v, 16, 22) << 29)
110 #define MAD_DIMM_CH_DSW(v) GET_BITFIELD(v, 24, 25)
112 /* Hash for memory controller selection */
113 #define MAD_MC_HASH_OFFSET (IMC_BASE + 0x1b8)
114 #define MAC_MC_HASH_LSB(v) GET_BITFIELD(v, 1, 3)
116 /* Hash for channel selection */
117 #define CHANNEL_HASH_OFFSET (IMC_BASE + 0x24)
118 /* Hash for enhanced channel selection */
119 #define CHANNEL_EHASH_OFFSET (IMC_BASE + 0x28)
120 #define CHANNEL_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6)
121 #define CHANNEL_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26)
122 #define CHANNEL_HASH_MODE(v) GET_BITFIELD(v, 28, 28)
124 /* Parameters for memory slice decode stage */
125 #define MEM_SLICE_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6)
126 #define MEM_SLICE_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26)
128 static struct res_config {
136 u32 ibecc_error_log_offset;
137 bool (*ibecc_available)(struct pci_dev *pdev);
138 /* Extract error address logged in IBECC */
139 u64 (*err_addr)(u64 ecclog);
140 /* Convert error address logged in IBECC to system physical address */
141 u64 (*err_addr_to_sys_addr)(u64 eaddr, int mc);
142 /* Convert error address logged in IBECC to integrated memory controller address */
143 u64 (*err_addr_to_imc_addr)(u64 eaddr, int mc);
148 struct mem_ctl_info *mci;
149 struct pci_dev *pdev;
151 void __iomem *window;
155 u64 dimm_s_size[NUM_CHANNELS];
156 u64 dimm_l_size[NUM_CHANNELS];
157 int dimm_l_map[NUM_CHANNELS];
160 static struct igen6_pvt {
161 struct igen6_imc imc[NUM_IMC];
167 /* The top of low usable DRAM */
168 static u32 igen6_tolud;
169 /* The size of physical memory */
170 static u64 igen6_tom;
172 struct decoded_addr {
179 u64 sub_channel_addr;
183 struct llist_node llnode;
189 * In the NMI handler, the driver uses the lock-less memory allocator
190 * to allocate memory to store the IBECC error logs and links the logs
191 * to the lock-less list. Delay printk() and the work of error reporting
192 * to EDAC core in a worker.
194 #define ECCLOG_POOL_SIZE PAGE_SIZE
195 static LLIST_HEAD(ecclog_llist);
196 static struct gen_pool *ecclog_pool;
197 static char ecclog_buf[ECCLOG_POOL_SIZE];
198 static struct irq_work ecclog_irq_work;
199 static struct work_struct ecclog_work;
201 /* Compute die IDs for Elkhart Lake with IBECC */
202 #define DID_EHL_SKU5 0x4514
203 #define DID_EHL_SKU6 0x4528
204 #define DID_EHL_SKU7 0x452a
205 #define DID_EHL_SKU8 0x4516
206 #define DID_EHL_SKU9 0x452c
207 #define DID_EHL_SKU10 0x452e
208 #define DID_EHL_SKU11 0x4532
209 #define DID_EHL_SKU12 0x4518
210 #define DID_EHL_SKU13 0x451a
211 #define DID_EHL_SKU14 0x4534
212 #define DID_EHL_SKU15 0x4536
214 /* Compute die IDs for ICL-NNPI with IBECC */
215 #define DID_ICL_SKU8 0x4581
216 #define DID_ICL_SKU10 0x4585
217 #define DID_ICL_SKU11 0x4589
218 #define DID_ICL_SKU12 0x458d
220 /* Compute die IDs for Tiger Lake with IBECC */
221 #define DID_TGL_SKU 0x9a14
223 /* Compute die IDs for Alder Lake with IBECC */
224 #define DID_ADL_SKU1 0x4601
225 #define DID_ADL_SKU2 0x4602
226 #define DID_ADL_SKU3 0x4621
227 #define DID_ADL_SKU4 0x4641
229 /* Compute die IDs for Alder Lake-N with IBECC */
230 #define DID_ADL_N_SKU1 0x4614
231 #define DID_ADL_N_SKU2 0x4617
232 #define DID_ADL_N_SKU3 0x461b
233 #define DID_ADL_N_SKU4 0x461c
234 #define DID_ADL_N_SKU5 0x4673
235 #define DID_ADL_N_SKU6 0x4674
236 #define DID_ADL_N_SKU7 0x4675
237 #define DID_ADL_N_SKU8 0x4677
238 #define DID_ADL_N_SKU9 0x4678
239 #define DID_ADL_N_SKU10 0x4679
240 #define DID_ADL_N_SKU11 0x467c
242 /* Compute die IDs for Raptor Lake-P with IBECC */
243 #define DID_RPL_P_SKU1 0xa706
244 #define DID_RPL_P_SKU2 0xa707
245 #define DID_RPL_P_SKU3 0xa708
246 #define DID_RPL_P_SKU4 0xa716
247 #define DID_RPL_P_SKU5 0xa718
249 /* Compute die IDs for Meteor Lake-PS with IBECC */
250 #define DID_MTL_PS_SKU1 0x7d21
251 #define DID_MTL_PS_SKU2 0x7d22
252 #define DID_MTL_PS_SKU3 0x7d23
253 #define DID_MTL_PS_SKU4 0x7d24
255 /* Compute die IDs for Meteor Lake-P with IBECC */
256 #define DID_MTL_P_SKU1 0x7d01
257 #define DID_MTL_P_SKU2 0x7d02
258 #define DID_MTL_P_SKU3 0x7d14
260 static int get_mchbar(struct pci_dev *pdev, u64 *mchbar)
270 if (pci_read_config_dword(pdev, MCHBAR_OFFSET, &u.v_lo)) {
271 igen6_printk(KERN_ERR, "Failed to read lower MCHBAR\n");
275 if (pci_read_config_dword(pdev, MCHBAR_OFFSET + 4, &u.v_hi)) {
276 igen6_printk(KERN_ERR, "Failed to read upper MCHBAR\n");
280 if (!(u.v & MCHBAR_EN)) {
281 igen6_printk(KERN_ERR, "MCHBAR is disabled\n");
285 *mchbar = MCHBAR_BASE(u.v);
290 static bool ehl_ibecc_available(struct pci_dev *pdev)
294 if (pci_read_config_dword(pdev, CAPID_C_OFFSET, &v))
297 return !!(CAPID_C_IBECC & v);
300 static u64 ehl_err_addr_to_sys_addr(u64 eaddr, int mc)
305 static u64 ehl_err_addr_to_imc_addr(u64 eaddr, int mc)
307 if (eaddr < igen6_tolud)
310 if (igen6_tom <= _4GB)
311 return eaddr + igen6_tolud - _4GB;
314 return eaddr + igen6_tolud - igen6_tom;
319 static bool icl_ibecc_available(struct pci_dev *pdev)
323 if (pci_read_config_dword(pdev, CAPID_C_OFFSET, &v))
326 return !(CAPID_C_IBECC & v) &&
327 (boot_cpu_data.x86_stepping >= 1);
330 static bool tgl_ibecc_available(struct pci_dev *pdev)
334 if (pci_read_config_dword(pdev, CAPID_E_OFFSET, &v))
337 return !(CAPID_E_IBECC & v);
340 static bool mtl_p_ibecc_available(struct pci_dev *pdev)
344 if (pci_read_config_dword(pdev, CAPID_E_OFFSET, &v))
347 return !(CAPID_E_IBECC_BIT18 & v);
350 static bool mtl_ps_ibecc_available(struct pci_dev *pdev)
352 #define MCHBAR_MEMSS_IBECCDIS 0x13c00
353 void __iomem *window;
357 if (get_mchbar(pdev, &mchbar))
360 window = ioremap(mchbar, MCHBAR_SIZE * 2);
362 igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", mchbar);
366 val = readl(window + MCHBAR_MEMSS_IBECCDIS);
369 /* Bit6: 1 - IBECC is disabled, 0 - IBECC isn't disabled */
370 return !GET_BITFIELD(val, 6, 6);
373 static u64 mem_addr_to_sys_addr(u64 maddr)
375 if (maddr < igen6_tolud)
378 if (igen6_tom <= _4GB)
379 return maddr - igen6_tolud + _4GB;
382 return maddr - igen6_tolud + igen6_tom;
387 static u64 mem_slice_hash(u64 addr, u64 mask, u64 hash_init, int intlv_bit)
389 u64 hash_addr = addr & mask, hash = hash_init;
390 u64 intlv = (addr >> intlv_bit) & 1;
393 for (i = 6; i < 20; i++)
394 hash ^= (hash_addr >> i) & 1;
399 static u64 tgl_err_addr_to_mem_addr(u64 eaddr, int mc)
401 u64 maddr, hash, mask, ms_s_size;
405 ms_s_size = igen6_pvt->ms_s_size;
406 if (eaddr >= ms_s_size)
407 return eaddr + ms_s_size;
409 ms_hash = igen6_pvt->ms_hash;
411 mask = MEM_SLICE_HASH_MASK(ms_hash);
412 intlv_bit = MEM_SLICE_HASH_LSB_MASK_BIT(ms_hash) + 6;
414 maddr = GET_BITFIELD(eaddr, intlv_bit, 63) << (intlv_bit + 1) |
415 GET_BITFIELD(eaddr, 0, intlv_bit - 1);
417 hash = mem_slice_hash(maddr, mask, mc, intlv_bit);
419 return maddr | (hash << intlv_bit);
422 static u64 tgl_err_addr_to_sys_addr(u64 eaddr, int mc)
424 u64 maddr = tgl_err_addr_to_mem_addr(eaddr, mc);
426 return mem_addr_to_sys_addr(maddr);
429 static u64 tgl_err_addr_to_imc_addr(u64 eaddr, int mc)
434 static u64 adl_err_addr_to_sys_addr(u64 eaddr, int mc)
436 return mem_addr_to_sys_addr(eaddr);
439 static u64 adl_err_addr_to_imc_addr(u64 eaddr, int mc)
441 u64 imc_addr, ms_s_size = igen6_pvt->ms_s_size;
442 struct igen6_imc *imc = &igen6_pvt->imc[mc];
446 if (eaddr >= 2 * ms_s_size)
447 return eaddr - ms_s_size;
449 mc_hash = readl(imc->window + MAD_MC_HASH_OFFSET);
451 intlv_bit = MAC_MC_HASH_LSB(mc_hash) + 6;
453 imc_addr = GET_BITFIELD(eaddr, intlv_bit + 1, 63) << intlv_bit |
454 GET_BITFIELD(eaddr, 0, intlv_bit - 1);
459 static u64 rpl_p_err_addr(u64 ecclog)
461 return ECC_ERROR_LOG_ADDR45(ecclog);
464 static struct res_config ehl_cfg = {
467 .ibecc_base = 0xdc00,
468 .ibecc_available = ehl_ibecc_available,
469 .ibecc_error_log_offset = 0x170,
470 .err_addr_to_sys_addr = ehl_err_addr_to_sys_addr,
471 .err_addr_to_imc_addr = ehl_err_addr_to_imc_addr,
474 static struct res_config icl_cfg = {
477 .ibecc_base = 0xd800,
478 .ibecc_error_log_offset = 0x170,
479 .ibecc_available = icl_ibecc_available,
480 .err_addr_to_sys_addr = ehl_err_addr_to_sys_addr,
481 .err_addr_to_imc_addr = ehl_err_addr_to_imc_addr,
484 static struct res_config tgl_cfg = {
485 .machine_check = true,
490 .ms_hash_offset = 0xac,
491 .ibecc_base = 0xd400,
492 .ibecc_error_log_offset = 0x170,
493 .ibecc_available = tgl_ibecc_available,
494 .err_addr_to_sys_addr = tgl_err_addr_to_sys_addr,
495 .err_addr_to_imc_addr = tgl_err_addr_to_imc_addr,
498 static struct res_config adl_cfg = {
499 .machine_check = true,
502 .ibecc_base = 0xd400,
503 .ibecc_error_log_offset = 0x68,
504 .ibecc_available = tgl_ibecc_available,
505 .err_addr_to_sys_addr = adl_err_addr_to_sys_addr,
506 .err_addr_to_imc_addr = adl_err_addr_to_imc_addr,
509 static struct res_config adl_n_cfg = {
510 .machine_check = true,
513 .ibecc_base = 0xd400,
514 .ibecc_error_log_offset = 0x68,
515 .ibecc_available = tgl_ibecc_available,
516 .err_addr_to_sys_addr = adl_err_addr_to_sys_addr,
517 .err_addr_to_imc_addr = adl_err_addr_to_imc_addr,
520 static struct res_config rpl_p_cfg = {
521 .machine_check = true,
524 .ibecc_base = 0xd400,
525 .ibecc_error_log_offset = 0x68,
526 .ibecc_available = tgl_ibecc_available,
527 .err_addr = rpl_p_err_addr,
528 .err_addr_to_sys_addr = adl_err_addr_to_sys_addr,
529 .err_addr_to_imc_addr = adl_err_addr_to_imc_addr,
532 static struct res_config mtl_ps_cfg = {
533 .machine_check = true,
536 .ibecc_base = 0xd400,
537 .ibecc_error_log_offset = 0x170,
538 .ibecc_available = mtl_ps_ibecc_available,
539 .err_addr_to_sys_addr = adl_err_addr_to_sys_addr,
540 .err_addr_to_imc_addr = adl_err_addr_to_imc_addr,
543 static struct res_config mtl_p_cfg = {
544 .machine_check = true,
547 .ibecc_base = 0xd400,
548 .ibecc_error_log_offset = 0x170,
549 .ibecc_available = mtl_p_ibecc_available,
550 .err_addr_to_sys_addr = adl_err_addr_to_sys_addr,
551 .err_addr_to_imc_addr = adl_err_addr_to_imc_addr,
554 static const struct pci_device_id igen6_pci_tbl[] = {
555 { PCI_VDEVICE(INTEL, DID_EHL_SKU5), (kernel_ulong_t)&ehl_cfg },
556 { PCI_VDEVICE(INTEL, DID_EHL_SKU6), (kernel_ulong_t)&ehl_cfg },
557 { PCI_VDEVICE(INTEL, DID_EHL_SKU7), (kernel_ulong_t)&ehl_cfg },
558 { PCI_VDEVICE(INTEL, DID_EHL_SKU8), (kernel_ulong_t)&ehl_cfg },
559 { PCI_VDEVICE(INTEL, DID_EHL_SKU9), (kernel_ulong_t)&ehl_cfg },
560 { PCI_VDEVICE(INTEL, DID_EHL_SKU10), (kernel_ulong_t)&ehl_cfg },
561 { PCI_VDEVICE(INTEL, DID_EHL_SKU11), (kernel_ulong_t)&ehl_cfg },
562 { PCI_VDEVICE(INTEL, DID_EHL_SKU12), (kernel_ulong_t)&ehl_cfg },
563 { PCI_VDEVICE(INTEL, DID_EHL_SKU13), (kernel_ulong_t)&ehl_cfg },
564 { PCI_VDEVICE(INTEL, DID_EHL_SKU14), (kernel_ulong_t)&ehl_cfg },
565 { PCI_VDEVICE(INTEL, DID_EHL_SKU15), (kernel_ulong_t)&ehl_cfg },
566 { PCI_VDEVICE(INTEL, DID_ICL_SKU8), (kernel_ulong_t)&icl_cfg },
567 { PCI_VDEVICE(INTEL, DID_ICL_SKU10), (kernel_ulong_t)&icl_cfg },
568 { PCI_VDEVICE(INTEL, DID_ICL_SKU11), (kernel_ulong_t)&icl_cfg },
569 { PCI_VDEVICE(INTEL, DID_ICL_SKU12), (kernel_ulong_t)&icl_cfg },
570 { PCI_VDEVICE(INTEL, DID_TGL_SKU), (kernel_ulong_t)&tgl_cfg },
571 { PCI_VDEVICE(INTEL, DID_ADL_SKU1), (kernel_ulong_t)&adl_cfg },
572 { PCI_VDEVICE(INTEL, DID_ADL_SKU2), (kernel_ulong_t)&adl_cfg },
573 { PCI_VDEVICE(INTEL, DID_ADL_SKU3), (kernel_ulong_t)&adl_cfg },
574 { PCI_VDEVICE(INTEL, DID_ADL_SKU4), (kernel_ulong_t)&adl_cfg },
575 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU1), (kernel_ulong_t)&adl_n_cfg },
576 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU2), (kernel_ulong_t)&adl_n_cfg },
577 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU3), (kernel_ulong_t)&adl_n_cfg },
578 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU4), (kernel_ulong_t)&adl_n_cfg },
579 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU5), (kernel_ulong_t)&adl_n_cfg },
580 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU6), (kernel_ulong_t)&adl_n_cfg },
581 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU7), (kernel_ulong_t)&adl_n_cfg },
582 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU8), (kernel_ulong_t)&adl_n_cfg },
583 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU9), (kernel_ulong_t)&adl_n_cfg },
584 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU10), (kernel_ulong_t)&adl_n_cfg },
585 { PCI_VDEVICE(INTEL, DID_ADL_N_SKU11), (kernel_ulong_t)&adl_n_cfg },
586 { PCI_VDEVICE(INTEL, DID_RPL_P_SKU1), (kernel_ulong_t)&rpl_p_cfg },
587 { PCI_VDEVICE(INTEL, DID_RPL_P_SKU2), (kernel_ulong_t)&rpl_p_cfg },
588 { PCI_VDEVICE(INTEL, DID_RPL_P_SKU3), (kernel_ulong_t)&rpl_p_cfg },
589 { PCI_VDEVICE(INTEL, DID_RPL_P_SKU4), (kernel_ulong_t)&rpl_p_cfg },
590 { PCI_VDEVICE(INTEL, DID_RPL_P_SKU5), (kernel_ulong_t)&rpl_p_cfg },
591 { PCI_VDEVICE(INTEL, DID_MTL_PS_SKU1), (kernel_ulong_t)&mtl_ps_cfg },
592 { PCI_VDEVICE(INTEL, DID_MTL_PS_SKU2), (kernel_ulong_t)&mtl_ps_cfg },
593 { PCI_VDEVICE(INTEL, DID_MTL_PS_SKU3), (kernel_ulong_t)&mtl_ps_cfg },
594 { PCI_VDEVICE(INTEL, DID_MTL_PS_SKU4), (kernel_ulong_t)&mtl_ps_cfg },
595 { PCI_VDEVICE(INTEL, DID_MTL_P_SKU1), (kernel_ulong_t)&mtl_p_cfg },
596 { PCI_VDEVICE(INTEL, DID_MTL_P_SKU2), (kernel_ulong_t)&mtl_p_cfg },
597 { PCI_VDEVICE(INTEL, DID_MTL_P_SKU3), (kernel_ulong_t)&mtl_p_cfg },
600 MODULE_DEVICE_TABLE(pci, igen6_pci_tbl);
602 static enum dev_type get_width(int dimm_l, u32 mad_dimm)
604 u32 w = dimm_l ? MAD_DIMM_CH_DLW(mad_dimm) :
605 MAD_DIMM_CH_DSW(mad_dimm);
619 static enum mem_type get_memory_type(u32 mad_inter)
621 u32 t = MAD_INTER_CHANNEL_DDR_TYPE(mad_inter);
639 static int decode_chan_idx(u64 addr, u64 mask, int intlv_bit)
641 u64 hash_addr = addr & mask, hash = 0;
642 u64 intlv = (addr >> intlv_bit) & 1;
645 for (i = 6; i < 20; i++)
646 hash ^= (hash_addr >> i) & 1;
648 return (int)hash ^ intlv;
651 static u64 decode_channel_addr(u64 addr, int intlv_bit)
655 /* Remove the interleave bit and shift upper part down to fill gap */
656 channel_addr = GET_BITFIELD(addr, intlv_bit + 1, 63) << intlv_bit;
657 channel_addr |= GET_BITFIELD(addr, 0, intlv_bit - 1);
662 static void decode_addr(u64 addr, u32 hash, u64 s_size, int l_map,
663 int *idx, u64 *sub_addr)
665 int intlv_bit = CHANNEL_HASH_LSB_MASK_BIT(hash) + 6;
667 if (addr > 2 * s_size) {
668 *sub_addr = addr - s_size;
673 if (CHANNEL_HASH_MODE(hash)) {
674 *sub_addr = decode_channel_addr(addr, intlv_bit);
675 *idx = decode_chan_idx(addr, CHANNEL_HASH_MASK(hash), intlv_bit);
677 *sub_addr = decode_channel_addr(addr, 6);
678 *idx = GET_BITFIELD(addr, 6, 6);
682 static int igen6_decode(struct decoded_addr *res)
684 struct igen6_imc *imc = &igen6_pvt->imc[res->mc];
685 u64 addr = res->imc_addr, sub_addr, s_size;
689 if (addr >= igen6_tom) {
690 edac_dbg(0, "Address 0x%llx out of range\n", addr);
695 hash = readl(imc->window + CHANNEL_HASH_OFFSET);
696 s_size = imc->ch_s_size;
697 l_map = imc->ch_l_map;
698 decode_addr(addr, hash, s_size, l_map, &idx, &sub_addr);
699 res->channel_idx = idx;
700 res->channel_addr = sub_addr;
702 /* Decode sub-channel/DIMM */
703 hash = readl(imc->window + CHANNEL_EHASH_OFFSET);
704 s_size = imc->dimm_s_size[idx];
705 l_map = imc->dimm_l_map[idx];
706 decode_addr(res->channel_addr, hash, s_size, l_map, &idx, &sub_addr);
707 res->sub_channel_idx = idx;
708 res->sub_channel_addr = sub_addr;
713 static void igen6_output_error(struct decoded_addr *res,
714 struct mem_ctl_info *mci, u64 ecclog)
716 enum hw_event_mc_err_type type = ecclog & ECC_ERROR_LOG_UE ?
717 HW_EVENT_ERR_UNCORRECTED :
718 HW_EVENT_ERR_CORRECTED;
720 edac_mc_handle_error(type, mci, 1,
721 res->sys_addr >> PAGE_SHIFT,
722 res->sys_addr & ~PAGE_MASK,
723 ECC_ERROR_LOG_SYND(ecclog),
724 res->channel_idx, res->sub_channel_idx,
728 static struct gen_pool *ecclog_gen_pool_create(void)
730 struct gen_pool *pool;
732 pool = gen_pool_create(ilog2(sizeof(struct ecclog_node)), -1);
736 if (gen_pool_add(pool, (unsigned long)ecclog_buf, ECCLOG_POOL_SIZE, -1)) {
737 gen_pool_destroy(pool);
744 static int ecclog_gen_pool_add(int mc, u64 ecclog)
746 struct ecclog_node *node;
748 node = (void *)gen_pool_alloc(ecclog_pool, sizeof(*node));
753 node->ecclog = ecclog;
754 llist_add(&node->llnode, &ecclog_llist);
760 * Either the memory-mapped I/O status register ECC_ERROR_LOG or the PCI
761 * configuration space status register ERRSTS can indicate whether a
762 * correctable error or an uncorrectable error occurred. We only use the
763 * ECC_ERROR_LOG register to check error type, but need to clear both
764 * registers to enable future error events.
766 static u64 ecclog_read_and_clear(struct igen6_imc *imc)
768 u64 ecclog = readq(imc->window + ECC_ERROR_LOG_OFFSET);
770 if (ecclog & (ECC_ERROR_LOG_CE | ECC_ERROR_LOG_UE)) {
771 /* Clear CE/UE bits by writing 1s */
772 writeq(ecclog, imc->window + ECC_ERROR_LOG_OFFSET);
779 static void errsts_clear(struct igen6_imc *imc)
783 if (pci_read_config_word(imc->pdev, ERRSTS_OFFSET, &errsts)) {
784 igen6_printk(KERN_ERR, "Failed to read ERRSTS\n");
788 /* Clear CE/UE bits by writing 1s */
789 if (errsts & (ERRSTS_CE | ERRSTS_UE))
790 pci_write_config_word(imc->pdev, ERRSTS_OFFSET, errsts);
793 static int errcmd_enable_error_reporting(bool enable)
795 struct igen6_imc *imc = &igen6_pvt->imc[0];
799 rc = pci_read_config_word(imc->pdev, ERRCMD_OFFSET, &errcmd);
804 errcmd |= ERRCMD_CE | ERRSTS_UE;
806 errcmd &= ~(ERRCMD_CE | ERRSTS_UE);
808 rc = pci_write_config_word(imc->pdev, ERRCMD_OFFSET, errcmd);
815 static int ecclog_handler(void)
817 struct igen6_imc *imc;
821 for (i = 0; i < res_cfg->num_imc; i++) {
822 imc = &igen6_pvt->imc[i];
824 /* errsts_clear() isn't NMI-safe. Delay it in the IRQ context */
826 ecclog = ecclog_read_and_clear(imc);
830 if (!ecclog_gen_pool_add(i, ecclog))
831 irq_work_queue(&ecclog_irq_work);
839 static void ecclog_work_cb(struct work_struct *work)
841 struct ecclog_node *node, *tmp;
842 struct mem_ctl_info *mci;
843 struct llist_node *head;
844 struct decoded_addr res;
847 head = llist_del_all(&ecclog_llist);
851 llist_for_each_entry_safe(node, tmp, head, llnode) {
852 memset(&res, 0, sizeof(res));
853 if (res_cfg->err_addr)
854 eaddr = res_cfg->err_addr(node->ecclog);
856 eaddr = ECC_ERROR_LOG_ADDR(node->ecclog) <<
857 ECC_ERROR_LOG_ADDR_SHIFT;
859 res.sys_addr = res_cfg->err_addr_to_sys_addr(eaddr, res.mc);
860 res.imc_addr = res_cfg->err_addr_to_imc_addr(eaddr, res.mc);
862 mci = igen6_pvt->imc[res.mc].mci;
864 edac_dbg(2, "MC %d, ecclog = 0x%llx\n", node->mc, node->ecclog);
865 igen6_mc_printk(mci, KERN_DEBUG, "HANDLING IBECC MEMORY ERROR\n");
866 igen6_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", res.sys_addr);
868 if (!igen6_decode(&res))
869 igen6_output_error(&res, mci, node->ecclog);
871 gen_pool_free(ecclog_pool, (unsigned long)node, sizeof(*node));
875 static void ecclog_irq_work_cb(struct irq_work *irq_work)
879 for (i = 0; i < res_cfg->num_imc; i++)
880 errsts_clear(&igen6_pvt->imc[i]);
882 if (!llist_empty(&ecclog_llist))
883 schedule_work(&ecclog_work);
886 static int ecclog_nmi_handler(unsigned int cmd, struct pt_regs *regs)
888 unsigned char reason;
890 if (!ecclog_handler())
894 * Both In-Band ECC correctable error and uncorrectable error are
895 * reported by SERR# NMI. The NMI generic code (see pci_serr_error())
896 * doesn't clear the bit NMI_REASON_CLEAR_SERR (in port 0x61) to
897 * re-enable the SERR# NMI after NMI handling. So clear this bit here
898 * to re-enable SERR# NMI for receiving future In-Band ECC errors.
900 reason = x86_platform.get_nmi_reason() & NMI_REASON_CLEAR_MASK;
901 reason |= NMI_REASON_CLEAR_SERR;
902 outb(reason, NMI_REASON_PORT);
903 reason &= ~NMI_REASON_CLEAR_SERR;
904 outb(reason, NMI_REASON_PORT);
909 static int ecclog_mce_handler(struct notifier_block *nb, unsigned long val,
912 struct mce *mce = (struct mce *)data;
915 if (mce->kflags & MCE_HANDLED_CEC)
919 * Ignore unless this is a memory related error.
920 * We don't check the bit MCI_STATUS_ADDRV of MCi_STATUS here,
921 * since this bit isn't set on some CPU (e.g., Tiger Lake UP3).
923 if ((mce->status & 0xefff) >> 7 != 1)
926 if (mce->mcgstatus & MCG_STATUS_MCIP)
931 edac_dbg(0, "CPU %d: Machine Check %s: 0x%llx Bank %d: 0x%llx\n",
932 mce->extcpu, type, mce->mcgstatus,
933 mce->bank, mce->status);
934 edac_dbg(0, "TSC 0x%llx\n", mce->tsc);
935 edac_dbg(0, "ADDR 0x%llx\n", mce->addr);
936 edac_dbg(0, "MISC 0x%llx\n", mce->misc);
937 edac_dbg(0, "PROCESSOR %u:0x%x TIME %llu SOCKET %u APIC 0x%x\n",
938 mce->cpuvendor, mce->cpuid, mce->time,
939 mce->socketid, mce->apicid);
941 * We just use the Machine Check for the memory error notification.
942 * Each memory controller is associated with an IBECC instance.
943 * Directly read and clear the error information(error address and
944 * error type) on all the IBECC instances so that we know on which
945 * memory controller the memory error(s) occurred.
947 if (!ecclog_handler())
950 mce->kflags |= MCE_HANDLED_EDAC;
955 static struct notifier_block ecclog_mce_dec = {
956 .notifier_call = ecclog_mce_handler,
957 .priority = MCE_PRIO_EDAC,
960 static bool igen6_check_ecc(struct igen6_imc *imc)
962 u32 activate = readl(imc->window + IBECC_ACTIVATE_OFFSET);
964 return !!(activate & IBECC_ACTIVATE_EN);
967 static int igen6_get_dimm_config(struct mem_ctl_info *mci)
969 struct igen6_imc *imc = mci->pvt_info;
970 u32 mad_inter, mad_intra, mad_dimm;
971 int i, j, ndimms, mc = imc->mc;
972 struct dimm_info *dimm;
980 mad_inter = readl(imc->window + MAD_INTER_CHANNEL_OFFSET);
981 mtype = get_memory_type(mad_inter);
982 ecc = igen6_check_ecc(imc);
983 imc->ch_s_size = MAD_INTER_CHANNEL_CH_S_SIZE(mad_inter);
984 imc->ch_l_map = MAD_INTER_CHANNEL_CH_L_MAP(mad_inter);
986 for (i = 0; i < NUM_CHANNELS; i++) {
987 mad_intra = readl(imc->window + MAD_INTRA_CH0_OFFSET + i * 4);
988 mad_dimm = readl(imc->window + MAD_DIMM_CH0_OFFSET + i * 4);
990 imc->dimm_l_size[i] = MAD_DIMM_CH_DIMM_L_SIZE(mad_dimm);
991 imc->dimm_s_size[i] = MAD_DIMM_CH_DIMM_S_SIZE(mad_dimm);
992 imc->dimm_l_map[i] = MAD_INTRA_CH_DIMM_L_MAP(mad_intra);
993 imc->size += imc->dimm_s_size[i];
994 imc->size += imc->dimm_l_size[i];
997 for (j = 0; j < NUM_DIMMS; j++) {
998 dimm = edac_get_dimm(mci, i, j, 0);
1000 if (j ^ imc->dimm_l_map[i]) {
1001 dtype = get_width(0, mad_dimm);
1002 dsize = imc->dimm_s_size[i];
1004 dtype = get_width(1, mad_dimm);
1005 dsize = imc->dimm_l_size[i];
1012 dimm->mtype = mtype;
1013 dimm->dtype = dtype;
1014 dimm->nr_pages = MiB_TO_PAGES(dsize >> 20);
1015 dimm->edac_mode = EDAC_SECDED;
1016 snprintf(dimm->label, sizeof(dimm->label),
1017 "MC#%d_Chan#%d_DIMM#%d", mc, i, j);
1018 edac_dbg(0, "MC %d, Channel %d, DIMM %d, Size %llu MiB (%u pages)\n",
1019 mc, i, j, dsize >> 20, dimm->nr_pages);
1024 if (ndimms && !ecc) {
1025 igen6_printk(KERN_ERR, "MC%d In-Band ECC is disabled\n", mc);
1030 edac_dbg(0, "MC %d, total size %llu MiB\n", mc, imc->size >> 20);
1035 #ifdef CONFIG_EDAC_DEBUG
1036 /* Top of upper usable DRAM */
1037 static u64 igen6_touud;
1038 #define TOUUD_OFFSET 0xa8
1040 static void igen6_reg_dump(struct igen6_imc *imc)
1044 edac_dbg(2, "CHANNEL_HASH : 0x%x\n",
1045 readl(imc->window + CHANNEL_HASH_OFFSET));
1046 edac_dbg(2, "CHANNEL_EHASH : 0x%x\n",
1047 readl(imc->window + CHANNEL_EHASH_OFFSET));
1048 edac_dbg(2, "MAD_INTER_CHANNEL: 0x%x\n",
1049 readl(imc->window + MAD_INTER_CHANNEL_OFFSET));
1050 edac_dbg(2, "ECC_ERROR_LOG : 0x%llx\n",
1051 readq(imc->window + ECC_ERROR_LOG_OFFSET));
1053 for (i = 0; i < NUM_CHANNELS; i++) {
1054 edac_dbg(2, "MAD_INTRA_CH%d : 0x%x\n", i,
1055 readl(imc->window + MAD_INTRA_CH0_OFFSET + i * 4));
1056 edac_dbg(2, "MAD_DIMM_CH%d : 0x%x\n", i,
1057 readl(imc->window + MAD_DIMM_CH0_OFFSET + i * 4));
1059 edac_dbg(2, "TOLUD : 0x%x", igen6_tolud);
1060 edac_dbg(2, "TOUUD : 0x%llx", igen6_touud);
1061 edac_dbg(2, "TOM : 0x%llx", igen6_tom);
1064 static struct dentry *igen6_test;
1066 static int debugfs_u64_set(void *data, u64 val)
1070 if ((val >= igen6_tolud && val < _4GB) || val >= igen6_touud) {
1071 edac_dbg(0, "Address 0x%llx out of range\n", val);
1075 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
1077 val >>= ECC_ERROR_LOG_ADDR_SHIFT;
1078 ecclog = (val << ECC_ERROR_LOG_ADDR_SHIFT) | ECC_ERROR_LOG_CE;
1080 if (!ecclog_gen_pool_add(0, ecclog))
1081 irq_work_queue(&ecclog_irq_work);
1085 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
1087 static void igen6_debug_setup(void)
1089 igen6_test = edac_debugfs_create_dir("igen6_test");
1093 if (!edac_debugfs_create_file("addr", 0200, igen6_test,
1094 NULL, &fops_u64_wo)) {
1095 debugfs_remove(igen6_test);
1100 static void igen6_debug_teardown(void)
1102 debugfs_remove_recursive(igen6_test);
1105 static void igen6_reg_dump(struct igen6_imc *imc) {}
1106 static void igen6_debug_setup(void) {}
1107 static void igen6_debug_teardown(void) {}
1110 static int igen6_pci_setup(struct pci_dev *pdev, u64 *mchbar)
1122 if (!res_cfg->ibecc_available(pdev)) {
1123 edac_dbg(2, "No In-Band ECC IP\n");
1127 if (pci_read_config_dword(pdev, TOLUD_OFFSET, &igen6_tolud)) {
1128 igen6_printk(KERN_ERR, "Failed to read TOLUD\n");
1132 igen6_tolud &= GENMASK(31, 20);
1134 if (pci_read_config_dword(pdev, TOM_OFFSET, &u.v_lo)) {
1135 igen6_printk(KERN_ERR, "Failed to read lower TOM\n");
1139 if (pci_read_config_dword(pdev, TOM_OFFSET + 4, &u.v_hi)) {
1140 igen6_printk(KERN_ERR, "Failed to read upper TOM\n");
1144 igen6_tom = u.v & GENMASK_ULL(38, 20);
1146 if (get_mchbar(pdev, mchbar))
1149 #ifdef CONFIG_EDAC_DEBUG
1150 if (pci_read_config_dword(pdev, TOUUD_OFFSET, &u.v_lo))
1151 edac_dbg(2, "Failed to read lower TOUUD\n");
1152 else if (pci_read_config_dword(pdev, TOUUD_OFFSET + 4, &u.v_hi))
1153 edac_dbg(2, "Failed to read upper TOUUD\n");
1155 igen6_touud = u.v & GENMASK_ULL(38, 20);
1163 static int igen6_register_mci(int mc, u64 mchbar, struct pci_dev *pdev)
1165 struct edac_mc_layer layers[2];
1166 struct mem_ctl_info *mci;
1167 struct igen6_imc *imc;
1168 void __iomem *window;
1173 mchbar += mc * MCHBAR_SIZE;
1174 window = ioremap(mchbar, MCHBAR_SIZE);
1176 igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", mchbar);
1180 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1181 layers[0].size = NUM_CHANNELS;
1182 layers[0].is_virt_csrow = false;
1183 layers[1].type = EDAC_MC_LAYER_SLOT;
1184 layers[1].size = NUM_DIMMS;
1185 layers[1].is_virt_csrow = true;
1187 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 0);
1193 mci->ctl_name = kasprintf(GFP_KERNEL, "Intel_client_SoC MC#%d", mc);
1194 if (!mci->ctl_name) {
1199 mci->mtype_cap = MEM_FLAG_LPDDR4 | MEM_FLAG_DDR4;
1200 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
1201 mci->edac_cap = EDAC_FLAG_SECDED;
1202 mci->mod_name = EDAC_MOD_STR;
1203 mci->dev_name = pci_name(pdev);
1204 mci->pvt_info = &igen6_pvt->imc[mc];
1206 imc = mci->pvt_info;
1207 device_initialize(&imc->dev);
1209 * EDAC core uses mci->pdev(pointer of structure device) as
1210 * memory controller ID. The client SoCs attach one or more
1211 * memory controllers to single pci_dev (single pci_dev->dev
1212 * can be for multiple memory controllers).
1214 * To make mci->pdev unique, assign pci_dev->dev to mci->pdev
1215 * for the first memory controller and assign a unique imc->dev
1216 * to mci->pdev for each non-first memory controller.
1218 mci->pdev = mc ? &imc->dev : &pdev->dev;
1221 imc->window = window;
1223 igen6_reg_dump(imc);
1225 rc = igen6_get_dimm_config(mci);
1229 rc = edac_mc_add_mc(mci);
1231 igen6_printk(KERN_ERR, "Failed to register mci#%d\n", mc);
1238 kfree(mci->ctl_name);
1246 static void igen6_unregister_mcis(void)
1248 struct mem_ctl_info *mci;
1249 struct igen6_imc *imc;
1254 for (i = 0; i < res_cfg->num_imc; i++) {
1255 imc = &igen6_pvt->imc[i];
1260 edac_mc_del_mc(mci->pdev);
1261 kfree(mci->ctl_name);
1263 iounmap(imc->window);
1267 static int igen6_mem_slice_setup(u64 mchbar)
1269 struct igen6_imc *imc = &igen6_pvt->imc[0];
1270 u64 base = mchbar + res_cfg->cmf_base;
1271 u32 offset = res_cfg->ms_hash_offset;
1272 u32 size = res_cfg->cmf_size;
1273 u64 ms_s_size, ms_hash;
1279 if (imc[0].size < imc[1].size) {
1280 ms_s_size = imc[0].size;
1283 ms_s_size = imc[1].size;
1287 igen6_pvt->ms_s_size = ms_s_size;
1288 igen6_pvt->ms_l_map = ms_l_map;
1290 edac_dbg(0, "ms_s_size: %llu MiB, ms_l_map %d\n",
1291 ms_s_size >> 20, ms_l_map);
1296 cmf = ioremap(base, size);
1298 igen6_printk(KERN_ERR, "Failed to ioremap cmf 0x%llx\n", base);
1302 ms_hash = readq(cmf + offset);
1303 igen6_pvt->ms_hash = ms_hash;
1305 edac_dbg(0, "MEM_SLICE_HASH: 0x%llx\n", ms_hash);
1312 static int register_err_handler(void)
1316 if (res_cfg->machine_check) {
1317 mce_register_decode_chain(&ecclog_mce_dec);
1321 rc = register_nmi_handler(NMI_SERR, ecclog_nmi_handler,
1324 igen6_printk(KERN_ERR, "Failed to register NMI handler\n");
1331 static void unregister_err_handler(void)
1333 if (res_cfg->machine_check) {
1334 mce_unregister_decode_chain(&ecclog_mce_dec);
1338 unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME);
1341 static int igen6_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1348 igen6_pvt = kzalloc(sizeof(*igen6_pvt), GFP_KERNEL);
1352 res_cfg = (struct res_config *)ent->driver_data;
1354 rc = igen6_pci_setup(pdev, &mchbar);
1358 for (i = 0; i < res_cfg->num_imc; i++) {
1359 rc = igen6_register_mci(i, mchbar, pdev);
1364 if (res_cfg->num_imc > 1) {
1365 rc = igen6_mem_slice_setup(mchbar);
1370 ecclog_pool = ecclog_gen_pool_create();
1376 INIT_WORK(&ecclog_work, ecclog_work_cb);
1377 init_irq_work(&ecclog_irq_work, ecclog_irq_work_cb);
1379 rc = register_err_handler();
1383 /* Enable error reporting */
1384 rc = errcmd_enable_error_reporting(true);
1386 igen6_printk(KERN_ERR, "Failed to enable error reporting\n");
1390 /* Check if any pending errors before/during the registration of the error handler */
1393 igen6_debug_setup();
1396 unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME);
1398 gen_pool_destroy(ecclog_pool);
1400 igen6_unregister_mcis();
1406 static void igen6_remove(struct pci_dev *pdev)
1410 igen6_debug_teardown();
1411 errcmd_enable_error_reporting(false);
1412 unregister_err_handler();
1413 irq_work_sync(&ecclog_irq_work);
1414 flush_work(&ecclog_work);
1415 gen_pool_destroy(ecclog_pool);
1416 igen6_unregister_mcis();
1420 static struct pci_driver igen6_driver = {
1421 .name = EDAC_MOD_STR,
1422 .probe = igen6_probe,
1423 .remove = igen6_remove,
1424 .id_table = igen6_pci_tbl,
1427 static int __init igen6_init(void)
1434 if (ghes_get_devices())
1437 owner = edac_get_owner();
1438 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
1441 edac_op_state = EDAC_OPSTATE_NMI;
1443 rc = pci_register_driver(&igen6_driver);
1447 igen6_printk(KERN_INFO, "%s\n", IGEN6_REVISION);
1452 static void __exit igen6_exit(void)
1456 pci_unregister_driver(&igen6_driver);
1459 module_init(igen6_init);
1460 module_exit(igen6_exit);
1462 MODULE_LICENSE("GPL v2");
1463 MODULE_AUTHOR("Qiuxu Zhuo");
1464 MODULE_DESCRIPTION("MC Driver for Intel client SoC using In-Band ECC");