1 /* Intel i7 core/Nehalem Memory Controller kernel module
3 * This driver supports the memory controllers found on the Intel
4 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
11 * Copyright (c) 2009-2010 by:
12 * Mauro Carvalho Chehab <mchehab@redhat.com>
14 * Red Hat Inc. http://www.redhat.com
16 * Forked and adapted from the i5400_edac driver
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/pci_ids.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/dmi.h>
35 #include <linux/edac.h>
36 #include <linux/mmzone.h>
37 #include <linux/smp.h>
39 #include <asm/processor.h>
40 #include <asm/div64.h>
42 #include "edac_core.h"
45 static LIST_HEAD(i7core_edac_list);
46 static DEFINE_MUTEX(i7core_edac_lock);
49 static int use_pci_fixup;
50 module_param(use_pci_fixup, int, 0444);
51 MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
53 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
54 * registers start at bus 255, and are not reported by BIOS.
55 * We currently find devices with only 2 sockets. In order to support more QPI
56 * Quick Path Interconnect, just increment this number.
58 #define MAX_SOCKET_BUSES 2
62 * Alter this version for the module when modifications are made
64 #define I7CORE_REVISION " Ver: 1.0.0"
65 #define EDAC_MOD_STR "i7core_edac"
70 #define i7core_printk(level, fmt, arg...) \
71 edac_printk(level, "i7core", fmt, ##arg)
73 #define i7core_mc_printk(mci, level, fmt, arg...) \
74 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
77 * i7core Memory Controller Registers
80 /* OFFSETS for Device 0 Function 0 */
82 #define MC_CFG_CONTROL 0x90
83 #define MC_CFG_UNLOCK 0x02
84 #define MC_CFG_LOCK 0x00
86 /* OFFSETS for Device 3 Function 0 */
88 #define MC_CONTROL 0x48
89 #define MC_STATUS 0x4c
90 #define MC_MAX_DOD 0x64
93 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
94 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
97 #define MC_TEST_ERR_RCV1 0x60
98 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
100 #define MC_TEST_ERR_RCV0 0x64
101 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
102 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
104 /* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
105 #define MC_SSRCONTROL 0x48
106 #define SSR_MODE_DISABLE 0x00
107 #define SSR_MODE_ENABLE 0x01
108 #define SSR_MODE_MASK 0x03
110 #define MC_SCRUB_CONTROL 0x4c
111 #define STARTSCRUB (1 << 24)
112 #define SCRUBINTERVAL_MASK 0xffffff
114 #define MC_COR_ECC_CNT_0 0x80
115 #define MC_COR_ECC_CNT_1 0x84
116 #define MC_COR_ECC_CNT_2 0x88
117 #define MC_COR_ECC_CNT_3 0x8c
118 #define MC_COR_ECC_CNT_4 0x90
119 #define MC_COR_ECC_CNT_5 0x94
121 #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
122 #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
125 /* OFFSETS for Devices 4,5 and 6 Function 0 */
127 #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
128 #define THREE_DIMMS_PRESENT (1 << 24)
129 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
130 #define QUAD_RANK_PRESENT (1 << 22)
131 #define REGISTERED_DIMM (1 << 15)
133 #define MC_CHANNEL_MAPPER 0x60
134 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
135 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
137 #define MC_CHANNEL_RANK_PRESENT 0x7c
138 #define RANK_PRESENT_MASK 0xffff
140 #define MC_CHANNEL_ADDR_MATCH 0xf0
141 #define MC_CHANNEL_ERROR_MASK 0xf8
142 #define MC_CHANNEL_ERROR_INJECT 0xfc
143 #define INJECT_ADDR_PARITY 0x10
144 #define INJECT_ECC 0x08
145 #define MASK_CACHELINE 0x06
146 #define MASK_FULL_CACHELINE 0x06
147 #define MASK_MSB32_CACHELINE 0x04
148 #define MASK_LSB32_CACHELINE 0x02
149 #define NO_MASK_CACHELINE 0x00
150 #define REPEAT_EN 0x01
152 /* OFFSETS for Devices 4,5 and 6 Function 1 */
154 #define MC_DOD_CH_DIMM0 0x48
155 #define MC_DOD_CH_DIMM1 0x4c
156 #define MC_DOD_CH_DIMM2 0x50
157 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
158 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
159 #define DIMM_PRESENT_MASK (1 << 9)
160 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
161 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
162 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
163 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
164 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
165 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
166 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
167 #define MC_DOD_NUMCOL_MASK 3
168 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
170 #define MC_RANK_PRESENT 0x7c
172 #define MC_SAG_CH_0 0x80
173 #define MC_SAG_CH_1 0x84
174 #define MC_SAG_CH_2 0x88
175 #define MC_SAG_CH_3 0x8c
176 #define MC_SAG_CH_4 0x90
177 #define MC_SAG_CH_5 0x94
178 #define MC_SAG_CH_6 0x98
179 #define MC_SAG_CH_7 0x9c
181 #define MC_RIR_LIMIT_CH_0 0x40
182 #define MC_RIR_LIMIT_CH_1 0x44
183 #define MC_RIR_LIMIT_CH_2 0x48
184 #define MC_RIR_LIMIT_CH_3 0x4C
185 #define MC_RIR_LIMIT_CH_4 0x50
186 #define MC_RIR_LIMIT_CH_5 0x54
187 #define MC_RIR_LIMIT_CH_6 0x58
188 #define MC_RIR_LIMIT_CH_7 0x5C
189 #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
191 #define MC_RIR_WAY_CH 0x80
192 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
193 #define MC_RIR_WAY_RANK_MASK 0x7
200 #define MAX_DIMMS 3 /* Max DIMMS per channel */
201 #define MAX_MCR_FUNC 4
202 #define MAX_CHAN_FUNC 3
212 struct i7core_inject {
219 /* Error address mask */
220 int channel, dimm, rank, bank, page, col;
223 struct i7core_channel {
228 struct pci_id_descr {
235 struct pci_id_table {
236 const struct pci_id_descr *descr;
241 struct list_head list;
243 struct pci_dev **pdev;
245 struct mem_ctl_info *mci;
249 struct pci_dev *pci_noncore;
250 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
251 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
253 struct i7core_dev *i7core_dev;
255 struct i7core_info info;
256 struct i7core_inject inject;
257 struct i7core_channel channel[NUM_CHANS];
259 int ce_count_available;
261 /* ECC corrected errors counts per udimm */
262 unsigned long udimm_ce_count[MAX_DIMMS];
263 int udimm_last_ce_count[MAX_DIMMS];
264 /* ECC corrected errors counts per rdimm */
265 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
266 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
268 bool is_registered, enable_scrub;
270 /* Fifo double buffers */
271 struct mce mce_entry[MCE_LOG_LEN];
272 struct mce mce_outentry[MCE_LOG_LEN];
274 /* Fifo in/out counters */
275 unsigned mce_in, mce_out;
277 /* Count indicator to show errors not got */
278 unsigned mce_overrun;
280 /* DCLK Frequency used for computing scrub rate */
283 /* Struct to control EDAC polling */
284 struct edac_pci_ctl_info *i7core_pci;
287 #define PCI_DESCR(device, function, device_id) \
289 .func = (function), \
290 .dev_id = (device_id)
292 static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
293 /* Memory controller */
294 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
295 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
296 /* Exists only for RDIMM */
297 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
298 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
301 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
302 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
303 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
304 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
307 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
308 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
309 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
310 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
313 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
314 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
315 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
316 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
318 /* Generic Non-core registers */
320 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
321 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
322 * the probing code needs to test for the other address in case of
323 * failure of this one
325 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
329 static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
330 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
331 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
332 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
334 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
335 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
336 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
337 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
339 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
340 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
341 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
342 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
345 * This is the PCI device has an alternate address on some
346 * processors like Core i7 860
348 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
351 static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
352 /* Memory controller */
353 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
354 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
355 /* Exists only for RDIMM */
356 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
357 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
360 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
361 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
362 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
363 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
366 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
367 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
368 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
369 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
372 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
373 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
374 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
375 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
377 /* Generic Non-core registers */
378 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
382 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
383 static const struct pci_id_table pci_dev_table[] = {
384 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
385 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
386 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
387 {0,} /* 0 terminated list. */
391 * pci_device_id table for which devices we are looking for
393 static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = {
394 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
395 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
396 {0,} /* 0 terminated list. */
399 /****************************************************************************
400 Anciliary status routines
401 ****************************************************************************/
403 /* MC_CONTROL bits */
404 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
405 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
408 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
409 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
411 /* MC_MAX_DOD read functions */
412 static inline int numdimms(u32 dimms)
414 return (dimms & 0x3) + 1;
417 static inline int numrank(u32 rank)
419 static int ranks[4] = { 1, 2, 4, -EINVAL };
421 return ranks[rank & 0x3];
424 static inline int numbank(u32 bank)
426 static int banks[4] = { 4, 8, 16, -EINVAL };
428 return banks[bank & 0x3];
431 static inline int numrow(u32 row)
433 static int rows[8] = {
434 1 << 12, 1 << 13, 1 << 14, 1 << 15,
435 1 << 16, -EINVAL, -EINVAL, -EINVAL,
438 return rows[row & 0x7];
441 static inline int numcol(u32 col)
443 static int cols[8] = {
444 1 << 10, 1 << 11, 1 << 12, -EINVAL,
446 return cols[col & 0x3];
449 static struct i7core_dev *get_i7core_dev(u8 socket)
451 struct i7core_dev *i7core_dev;
453 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
454 if (i7core_dev->socket == socket)
461 static struct i7core_dev *alloc_i7core_dev(u8 socket,
462 const struct pci_id_table *table)
464 struct i7core_dev *i7core_dev;
466 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
470 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
472 if (!i7core_dev->pdev) {
477 i7core_dev->socket = socket;
478 i7core_dev->n_devs = table->n_devs;
479 list_add_tail(&i7core_dev->list, &i7core_edac_list);
484 static void free_i7core_dev(struct i7core_dev *i7core_dev)
486 list_del(&i7core_dev->list);
487 kfree(i7core_dev->pdev);
491 /****************************************************************************
492 Memory check routines
493 ****************************************************************************/
495 static int get_dimm_config(struct mem_ctl_info *mci)
497 struct i7core_pvt *pvt = mci->pvt_info;
498 struct pci_dev *pdev;
502 struct dimm_info *dimm;
504 /* Get data from the MC register, function 0 */
505 pdev = pvt->pci_mcr[0];
509 /* Device 3 function 0 reads */
510 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
511 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
512 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
513 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
515 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
516 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
517 pvt->info.max_dod, pvt->info.ch_map);
519 if (ECC_ENABLED(pvt)) {
520 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
522 mode = EDAC_S8ECD8ED;
524 mode = EDAC_S4ECD4ED;
526 debugf0("ECC disabled\n");
530 /* FIXME: need to handle the error codes */
531 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
533 numdimms(pvt->info.max_dod),
534 numrank(pvt->info.max_dod >> 2),
535 numbank(pvt->info.max_dod >> 4),
536 numrow(pvt->info.max_dod >> 6),
537 numcol(pvt->info.max_dod >> 9));
539 for (i = 0; i < NUM_CHANS; i++) {
540 u32 data, dimm_dod[3], value[8];
542 if (!pvt->pci_ch[i][0])
545 if (!CH_ACTIVE(pvt, i)) {
546 debugf0("Channel %i is not active\n", i);
549 if (CH_DISABLED(pvt, i)) {
550 debugf0("Channel %i is disabled\n", i);
554 /* Devices 4-6 function 0 */
555 pci_read_config_dword(pvt->pci_ch[i][0],
556 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
558 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
561 if (data & REGISTERED_DIMM)
566 if (data & THREE_DIMMS_PRESENT)
567 pvt->channel[i].dimms = 3;
568 else if (data & SINGLE_QUAD_RANK_PRESENT)
569 pvt->channel[i].dimms = 1;
571 pvt->channel[i].dimms = 2;
574 /* Devices 4-6 function 1 */
575 pci_read_config_dword(pvt->pci_ch[i][1],
576 MC_DOD_CH_DIMM0, &dimm_dod[0]);
577 pci_read_config_dword(pvt->pci_ch[i][1],
578 MC_DOD_CH_DIMM1, &dimm_dod[1]);
579 pci_read_config_dword(pvt->pci_ch[i][1],
580 MC_DOD_CH_DIMM2, &dimm_dod[2]);
582 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
583 "%d ranks, %cDIMMs\n",
585 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
587 pvt->channel[i].ranks,
588 (data & REGISTERED_DIMM) ? 'R' : 'U');
590 for (j = 0; j < 3; j++) {
591 u32 banks, ranks, rows, cols;
594 if (!DIMM_PRESENT(dimm_dod[j]))
597 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
599 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
600 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
601 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
602 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
604 /* DDR3 has 8 I/O banks */
605 size = (rows * cols * banks * ranks) >> (20 - 3);
607 debugf0("\tdimm %d %d Mb offset: %x, "
608 "bank: %d, rank: %d, row: %#x, col: %#x\n",
610 RANKOFFSET(dimm_dod[j]),
611 banks, ranks, rows, cols);
613 npages = MiB_TO_PAGES(size);
615 dimm->nr_pages = npages;
619 dimm->dtype = DEV_X4;
622 dimm->dtype = DEV_X8;
625 dimm->dtype = DEV_X16;
628 dimm->dtype = DEV_UNKNOWN;
631 snprintf(dimm->label, sizeof(dimm->label),
632 "CPU#%uChannel#%u_DIMM#%u",
633 pvt->i7core_dev->socket, i, j);
635 dimm->edac_mode = mode;
639 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
640 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
641 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
642 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
643 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
644 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
645 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
646 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
647 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
648 for (j = 0; j < 8; j++)
649 debugf1("\t\t%#x\t%#x\t%#x\n",
650 (value[j] >> 27) & 0x1,
651 (value[j] >> 24) & 0x7,
652 (value[j] & ((1 << 24) - 1)));
658 /****************************************************************************
659 Error insertion routines
660 ****************************************************************************/
662 /* The i7core has independent error injection features per channel.
663 However, to have a simpler code, we don't allow enabling error injection
664 on more than one channel.
665 Also, since a change at an inject parameter will be applied only at enable,
666 we're disabling error injection on all write calls to the sysfs nodes that
667 controls the error code injection.
669 static int disable_inject(const struct mem_ctl_info *mci)
671 struct i7core_pvt *pvt = mci->pvt_info;
673 pvt->inject.enable = 0;
675 if (!pvt->pci_ch[pvt->inject.channel][0])
678 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
679 MC_CHANNEL_ERROR_INJECT, 0);
685 * i7core inject inject.section
687 * accept and store error injection inject.section value
688 * bit 0 - refers to the lower 32-byte half cacheline
689 * bit 1 - refers to the upper 32-byte half cacheline
691 static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
692 const char *data, size_t count)
694 struct i7core_pvt *pvt = mci->pvt_info;
698 if (pvt->inject.enable)
701 rc = strict_strtoul(data, 10, &value);
702 if ((rc < 0) || (value > 3))
705 pvt->inject.section = (u32) value;
709 static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
712 struct i7core_pvt *pvt = mci->pvt_info;
713 return sprintf(data, "0x%08x\n", pvt->inject.section);
719 * accept and store error injection inject.section value
720 * bit 0 - repeat enable - Enable error repetition
721 * bit 1 - inject ECC error
722 * bit 2 - inject parity error
724 static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
725 const char *data, size_t count)
727 struct i7core_pvt *pvt = mci->pvt_info;
731 if (pvt->inject.enable)
734 rc = strict_strtoul(data, 10, &value);
735 if ((rc < 0) || (value > 7))
738 pvt->inject.type = (u32) value;
742 static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
745 struct i7core_pvt *pvt = mci->pvt_info;
746 return sprintf(data, "0x%08x\n", pvt->inject.type);
750 * i7core_inject_inject.eccmask_store
752 * The type of error (UE/CE) will depend on the inject.eccmask value:
753 * Any bits set to a 1 will flip the corresponding ECC bit
754 * Correctable errors can be injected by flipping 1 bit or the bits within
755 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
756 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
757 * uncorrectable error to be injected.
759 static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
760 const char *data, size_t count)
762 struct i7core_pvt *pvt = mci->pvt_info;
766 if (pvt->inject.enable)
769 rc = strict_strtoul(data, 10, &value);
773 pvt->inject.eccmask = (u32) value;
777 static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
780 struct i7core_pvt *pvt = mci->pvt_info;
781 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
787 * The type of error (UE/CE) will depend on the inject.eccmask value:
788 * Any bits set to a 1 will flip the corresponding ECC bit
789 * Correctable errors can be injected by flipping 1 bit or the bits within
790 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
791 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
792 * uncorrectable error to be injected.
795 #define DECLARE_ADDR_MATCH(param, limit) \
796 static ssize_t i7core_inject_store_##param( \
797 struct mem_ctl_info *mci, \
798 const char *data, size_t count) \
800 struct i7core_pvt *pvt; \
804 debugf1("%s()\n", __func__); \
805 pvt = mci->pvt_info; \
807 if (pvt->inject.enable) \
808 disable_inject(mci); \
810 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
813 rc = strict_strtoul(data, 10, &value); \
814 if ((rc < 0) || (value >= limit)) \
818 pvt->inject.param = value; \
823 static ssize_t i7core_inject_show_##param( \
824 struct mem_ctl_info *mci, \
827 struct i7core_pvt *pvt; \
829 pvt = mci->pvt_info; \
830 debugf1("%s() pvt=%p\n", __func__, pvt); \
831 if (pvt->inject.param < 0) \
832 return sprintf(data, "any\n"); \
834 return sprintf(data, "%d\n", pvt->inject.param);\
837 #define ATTR_ADDR_MATCH(param) \
841 .mode = (S_IRUGO | S_IWUSR) \
843 .show = i7core_inject_show_##param, \
844 .store = i7core_inject_store_##param, \
847 DECLARE_ADDR_MATCH(channel, 3);
848 DECLARE_ADDR_MATCH(dimm, 3);
849 DECLARE_ADDR_MATCH(rank, 4);
850 DECLARE_ADDR_MATCH(bank, 32);
851 DECLARE_ADDR_MATCH(page, 0x10000);
852 DECLARE_ADDR_MATCH(col, 0x4000);
854 static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
859 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
860 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
863 for (count = 0; count < 10; count++) {
866 pci_write_config_dword(dev, where, val);
867 pci_read_config_dword(dev, where, &read);
873 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
874 "write=%08x. Read=%08x\n",
875 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
882 * This routine prepares the Memory Controller for error injection.
883 * The error will be injected when some process tries to write to the
884 * memory that matches the given criteria.
885 * The criteria can be set in terms of a mask where dimm, rank, bank, page
886 * and col can be specified.
887 * A -1 value for any of the mask items will make the MCU to ignore
888 * that matching criteria for error injection.
890 * It should be noticed that the error will only happen after a write operation
891 * on a memory that matches the condition. if REPEAT_EN is not enabled at
892 * inject mask, then it will produce just one error. Otherwise, it will repeat
893 * until the injectmask would be cleaned.
895 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
896 * is reliable enough to check if the MC is using the
897 * three channels. However, this is not clear at the datasheet.
899 static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
900 const char *data, size_t count)
902 struct i7core_pvt *pvt = mci->pvt_info;
908 if (!pvt->pci_ch[pvt->inject.channel][0])
911 rc = strict_strtoul(data, 10, &enable);
916 pvt->inject.enable = 1;
922 /* Sets pvt->inject.dimm mask */
923 if (pvt->inject.dimm < 0)
926 if (pvt->channel[pvt->inject.channel].dimms > 2)
927 mask |= (pvt->inject.dimm & 0x3LL) << 35;
929 mask |= (pvt->inject.dimm & 0x1LL) << 36;
932 /* Sets pvt->inject.rank mask */
933 if (pvt->inject.rank < 0)
936 if (pvt->channel[pvt->inject.channel].dimms > 2)
937 mask |= (pvt->inject.rank & 0x1LL) << 34;
939 mask |= (pvt->inject.rank & 0x3LL) << 34;
942 /* Sets pvt->inject.bank mask */
943 if (pvt->inject.bank < 0)
946 mask |= (pvt->inject.bank & 0x15LL) << 30;
948 /* Sets pvt->inject.page mask */
949 if (pvt->inject.page < 0)
952 mask |= (pvt->inject.page & 0xffff) << 14;
954 /* Sets pvt->inject.column mask */
955 if (pvt->inject.col < 0)
958 mask |= (pvt->inject.col & 0x3fff);
962 * bits 1-2: MASK_HALF_CACHELINE
964 * bit 4: INJECT_ADDR_PARITY
967 injectmask = (pvt->inject.type & 1) |
968 (pvt->inject.section & 0x3) << 1 |
969 (pvt->inject.type & 0x6) << (3 - 1);
971 /* Unlock writes to registers - this register is write only */
972 pci_write_config_dword(pvt->pci_noncore,
973 MC_CFG_CONTROL, 0x2);
975 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
976 MC_CHANNEL_ADDR_MATCH, mask);
977 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
978 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
980 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
981 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
983 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
984 MC_CHANNEL_ERROR_INJECT, injectmask);
987 * This is something undocumented, based on my tests
988 * Without writing 8 to this register, errors aren't injected. Not sure
991 pci_write_config_dword(pvt->pci_noncore,
994 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
996 mask, pvt->inject.eccmask, injectmask);
1002 static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
1005 struct i7core_pvt *pvt = mci->pvt_info;
1008 if (!pvt->pci_ch[pvt->inject.channel][0])
1011 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1012 MC_CHANNEL_ERROR_INJECT, &injectmask);
1014 debugf0("Inject error read: 0x%018x\n", injectmask);
1016 if (injectmask & 0x0c)
1017 pvt->inject.enable = 1;
1019 return sprintf(data, "%d\n", pvt->inject.enable);
1022 #define DECLARE_COUNTER(param) \
1023 static ssize_t i7core_show_counter_##param( \
1024 struct mem_ctl_info *mci, \
1027 struct i7core_pvt *pvt = mci->pvt_info; \
1029 debugf1("%s() \n", __func__); \
1030 if (!pvt->ce_count_available || (pvt->is_registered)) \
1031 return sprintf(data, "data unavailable\n"); \
1032 return sprintf(data, "%lu\n", \
1033 pvt->udimm_ce_count[param]); \
1036 #define ATTR_COUNTER(param) \
1039 .name = __stringify(udimm##param), \
1040 .mode = (S_IRUGO | S_IWUSR) \
1042 .show = i7core_show_counter_##param \
1053 static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
1054 ATTR_ADDR_MATCH(channel),
1055 ATTR_ADDR_MATCH(dimm),
1056 ATTR_ADDR_MATCH(rank),
1057 ATTR_ADDR_MATCH(bank),
1058 ATTR_ADDR_MATCH(page),
1059 ATTR_ADDR_MATCH(col),
1060 { } /* End of list */
1063 static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
1064 .name = "inject_addrmatch",
1065 .mcidev_attr = i7core_addrmatch_attrs,
1068 static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
1072 { .attr = { .name = NULL } }
1075 static const struct mcidev_sysfs_group i7core_udimm_counters = {
1076 .name = "all_channel_counts",
1077 .mcidev_attr = i7core_udimm_counters_attrs,
1080 static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
1083 .name = "inject_section",
1084 .mode = (S_IRUGO | S_IWUSR)
1086 .show = i7core_inject_section_show,
1087 .store = i7core_inject_section_store,
1090 .name = "inject_type",
1091 .mode = (S_IRUGO | S_IWUSR)
1093 .show = i7core_inject_type_show,
1094 .store = i7core_inject_type_store,
1097 .name = "inject_eccmask",
1098 .mode = (S_IRUGO | S_IWUSR)
1100 .show = i7core_inject_eccmask_show,
1101 .store = i7core_inject_eccmask_store,
1103 .grp = &i7core_inject_addrmatch,
1106 .name = "inject_enable",
1107 .mode = (S_IRUGO | S_IWUSR)
1109 .show = i7core_inject_enable_show,
1110 .store = i7core_inject_enable_store,
1112 { } /* End of list */
1115 static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
1118 .name = "inject_section",
1119 .mode = (S_IRUGO | S_IWUSR)
1121 .show = i7core_inject_section_show,
1122 .store = i7core_inject_section_store,
1125 .name = "inject_type",
1126 .mode = (S_IRUGO | S_IWUSR)
1128 .show = i7core_inject_type_show,
1129 .store = i7core_inject_type_store,
1132 .name = "inject_eccmask",
1133 .mode = (S_IRUGO | S_IWUSR)
1135 .show = i7core_inject_eccmask_show,
1136 .store = i7core_inject_eccmask_store,
1138 .grp = &i7core_inject_addrmatch,
1141 .name = "inject_enable",
1142 .mode = (S_IRUGO | S_IWUSR)
1144 .show = i7core_inject_enable_show,
1145 .store = i7core_inject_enable_store,
1147 .grp = &i7core_udimm_counters,
1149 { } /* End of list */
1152 /****************************************************************************
1153 Device initialization routines: put/get, init/exit
1154 ****************************************************************************/
1157 * i7core_put_all_devices 'put' all the devices that we have
1158 * reserved via 'get'
1160 static void i7core_put_devices(struct i7core_dev *i7core_dev)
1164 debugf0(__FILE__ ": %s()\n", __func__);
1165 for (i = 0; i < i7core_dev->n_devs; i++) {
1166 struct pci_dev *pdev = i7core_dev->pdev[i];
1169 debugf0("Removing dev %02x:%02x.%d\n",
1171 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1176 static void i7core_put_all_devices(void)
1178 struct i7core_dev *i7core_dev, *tmp;
1180 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
1181 i7core_put_devices(i7core_dev);
1182 free_i7core_dev(i7core_dev);
1186 static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
1188 struct pci_dev *pdev = NULL;
1192 * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
1193 * aren't announced by acpi. So, we need to use a legacy scan probing
1196 while (table && table->descr) {
1197 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1198 if (unlikely(!pdev)) {
1199 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1200 pcibios_scan_specific_bus(255-i);
1207 static unsigned i7core_pci_lastbus(void)
1209 int last_bus = 0, bus;
1210 struct pci_bus *b = NULL;
1212 while ((b = pci_find_next_bus(b)) != NULL) {
1214 debugf0("Found bus %d\n", bus);
1219 debugf0("Last bus %d\n", last_bus);
1225 * i7core_get_all_devices Find and perform 'get' operation on the MCH's
1226 * device/functions we want to reference for this driver
1228 * Need to 'get' device 16 func 1 and func 2
1230 static int i7core_get_onedevice(struct pci_dev **prev,
1231 const struct pci_id_table *table,
1232 const unsigned devno,
1233 const unsigned last_bus)
1235 struct i7core_dev *i7core_dev;
1236 const struct pci_id_descr *dev_descr = &table->descr[devno];
1238 struct pci_dev *pdev = NULL;
1242 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1243 dev_descr->dev_id, *prev);
1246 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1247 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1248 * to probe for the alternate address in case of failure
1250 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
1251 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1252 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
1254 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
1255 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1256 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1265 if (dev_descr->optional)
1271 i7core_printk(KERN_INFO,
1272 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1273 dev_descr->dev, dev_descr->func,
1274 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1276 /* End of list, leave */
1279 bus = pdev->bus->number;
1281 socket = last_bus - bus;
1283 i7core_dev = get_i7core_dev(socket);
1285 i7core_dev = alloc_i7core_dev(socket, table);
1292 if (i7core_dev->pdev[devno]) {
1293 i7core_printk(KERN_ERR,
1294 "Duplicated device for "
1295 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1296 bus, dev_descr->dev, dev_descr->func,
1297 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1302 i7core_dev->pdev[devno] = pdev;
1305 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1306 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1307 i7core_printk(KERN_ERR,
1308 "Device PCI ID %04x:%04x "
1309 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
1310 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1311 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1312 bus, dev_descr->dev, dev_descr->func);
1316 /* Be sure that the device is enabled */
1317 if (unlikely(pci_enable_device(pdev) < 0)) {
1318 i7core_printk(KERN_ERR,
1320 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1321 bus, dev_descr->dev, dev_descr->func,
1322 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1326 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1327 socket, bus, dev_descr->dev,
1329 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1332 * As stated on drivers/pci/search.c, the reference count for
1333 * @from is always decremented if it is not %NULL. So, as we need
1334 * to get all devices up to null, we need to do a get for the device
1343 static int i7core_get_all_devices(void)
1345 int i, rc, last_bus;
1346 struct pci_dev *pdev = NULL;
1347 const struct pci_id_table *table = pci_dev_table;
1349 last_bus = i7core_pci_lastbus();
1351 while (table && table->descr) {
1352 for (i = 0; i < table->n_devs; i++) {
1355 rc = i7core_get_onedevice(&pdev, table, i,
1362 i7core_put_all_devices();
1373 static int mci_bind_devs(struct mem_ctl_info *mci,
1374 struct i7core_dev *i7core_dev)
1376 struct i7core_pvt *pvt = mci->pvt_info;
1377 struct pci_dev *pdev;
1381 pvt->is_registered = false;
1382 pvt->enable_scrub = false;
1383 for (i = 0; i < i7core_dev->n_devs; i++) {
1384 pdev = i7core_dev->pdev[i];
1388 func = PCI_FUNC(pdev->devfn);
1389 slot = PCI_SLOT(pdev->devfn);
1391 if (unlikely(func > MAX_MCR_FUNC))
1393 pvt->pci_mcr[func] = pdev;
1394 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1395 if (unlikely(func > MAX_CHAN_FUNC))
1397 pvt->pci_ch[slot - 4][func] = pdev;
1398 } else if (!slot && !func) {
1399 pvt->pci_noncore = pdev;
1401 /* Detect the processor family */
1402 switch (pdev->device) {
1403 case PCI_DEVICE_ID_INTEL_I7_NONCORE:
1404 family = "Xeon 35xx/ i7core";
1405 pvt->enable_scrub = false;
1407 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT:
1408 family = "i7-800/i5-700";
1409 pvt->enable_scrub = false;
1411 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE:
1412 family = "Xeon 34xx";
1413 pvt->enable_scrub = false;
1415 case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT:
1416 family = "Xeon 55xx";
1417 pvt->enable_scrub = true;
1419 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2:
1420 family = "Xeon 56xx / i7-900";
1421 pvt->enable_scrub = true;
1425 pvt->enable_scrub = false;
1427 debugf0("Detected a processor type %s\n", family);
1431 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1432 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1433 pdev, i7core_dev->socket);
1435 if (PCI_SLOT(pdev->devfn) == 3 &&
1436 PCI_FUNC(pdev->devfn) == 2)
1437 pvt->is_registered = true;
1443 i7core_printk(KERN_ERR, "Device %d, function %d "
1444 "is out of the expected range\n",
1449 /****************************************************************************
1450 Error check routines
1451 ****************************************************************************/
1452 static void i7core_rdimm_update_errcount(struct mem_ctl_info *mci,
1459 for (i = 0; i < add; i++) {
1460 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
1461 chan, dimm, -1, "error", "", NULL);
1465 static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
1471 struct i7core_pvt *pvt = mci->pvt_info;
1472 int add0 = 0, add1 = 0, add2 = 0;
1473 /* Updates CE counters if it is not the first time here */
1474 if (pvt->ce_count_available) {
1475 /* Updates CE counters */
1477 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1478 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1479 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
1483 pvt->rdimm_ce_count[chan][2] += add2;
1487 pvt->rdimm_ce_count[chan][1] += add1;
1491 pvt->rdimm_ce_count[chan][0] += add0;
1493 pvt->ce_count_available = 1;
1495 /* Store the new values */
1496 pvt->rdimm_last_ce_count[chan][2] = new2;
1497 pvt->rdimm_last_ce_count[chan][1] = new1;
1498 pvt->rdimm_last_ce_count[chan][0] = new0;
1500 /*updated the edac core */
1502 i7core_rdimm_update_errcount(mci, chan, 0, add0);
1504 i7core_rdimm_update_errcount(mci, chan, 1, add1);
1506 i7core_rdimm_update_errcount(mci, chan, 2, add2);
1510 static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1512 struct i7core_pvt *pvt = mci->pvt_info;
1514 int i, new0, new1, new2;
1516 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
1517 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
1519 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
1521 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
1523 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
1525 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
1527 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1529 for (i = 0 ; i < 3; i++) {
1530 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1531 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1532 /*if the channel has 3 dimms*/
1533 if (pvt->channel[i].dimms > 2) {
1534 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1535 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1536 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1538 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1539 DIMM_BOT_COR_ERR(rcv[i][0]);
1540 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1541 DIMM_BOT_COR_ERR(rcv[i][1]);
1545 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
1549 /* This function is based on the device 3 function 4 registers as described on:
1550 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1551 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1552 * also available at:
1553 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1555 static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1557 struct i7core_pvt *pvt = mci->pvt_info;
1559 int new0, new1, new2;
1561 if (!pvt->pci_mcr[4]) {
1562 debugf0("%s MCR registers not found\n", __func__);
1566 /* Corrected test errors */
1567 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1568 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
1570 /* Store the new values */
1571 new2 = DIMM2_COR_ERR(rcv1);
1572 new1 = DIMM1_COR_ERR(rcv0);
1573 new0 = DIMM0_COR_ERR(rcv0);
1575 /* Updates CE counters if it is not the first time here */
1576 if (pvt->ce_count_available) {
1577 /* Updates CE counters */
1578 int add0, add1, add2;
1580 add2 = new2 - pvt->udimm_last_ce_count[2];
1581 add1 = new1 - pvt->udimm_last_ce_count[1];
1582 add0 = new0 - pvt->udimm_last_ce_count[0];
1586 pvt->udimm_ce_count[2] += add2;
1590 pvt->udimm_ce_count[1] += add1;
1594 pvt->udimm_ce_count[0] += add0;
1596 if (add0 | add1 | add2)
1597 i7core_printk(KERN_ERR, "New Corrected error(s): "
1598 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1601 pvt->ce_count_available = 1;
1603 /* Store the new values */
1604 pvt->udimm_last_ce_count[2] = new2;
1605 pvt->udimm_last_ce_count[1] = new1;
1606 pvt->udimm_last_ce_count[0] = new0;
1610 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1611 * Architectures Software Developer’s Manual Volume 3B.
1612 * Nehalem are defined as family 0x06, model 0x1a
1614 * The MCA registers used here are the following ones:
1615 * struct mce field MCA Register
1616 * m->status MSR_IA32_MC8_STATUS
1617 * m->addr MSR_IA32_MC8_ADDR
1618 * m->misc MSR_IA32_MC8_MISC
1619 * In the case of Nehalem, the error information is masked at .status and .misc
1622 static void i7core_mce_output_error(struct mem_ctl_info *mci,
1623 const struct mce *m)
1625 struct i7core_pvt *pvt = mci->pvt_info;
1626 char *type, *optype, *err, *msg;
1627 enum hw_event_mc_err_type tp_event;
1628 unsigned long error = m->status & 0x1ff0000l;
1629 bool uncorrected_error = m->mcgstatus & 1ll << 61;
1630 bool ripv = m->mcgstatus & 1;
1631 u32 optypenum = (m->status >> 4) & 0x07;
1632 u32 core_err_cnt = (m->status >> 38) & 0x7fff;
1633 u32 dimm = (m->misc >> 16) & 0x3;
1634 u32 channel = (m->misc >> 18) & 0x3;
1635 u32 syndrome = m->misc >> 32;
1636 u32 errnum = find_first_bit(&error, 32);
1638 if (uncorrected_error) {
1641 tp_event = HW_EVENT_ERR_FATAL;
1644 tp_event = HW_EVENT_ERR_UNCORRECTED;
1648 tp_event = HW_EVENT_ERR_CORRECTED;
1651 switch (optypenum) {
1653 optype = "generic undef request";
1656 optype = "read error";
1659 optype = "write error";
1662 optype = "addr/cmd error";
1665 optype = "scrubbing error";
1668 optype = "reserved";
1674 err = "read ECC error";
1677 err = "RAS ECC error";
1680 err = "write parity error";
1683 err = "redundacy loss";
1689 err = "memory range error";
1692 err = "RTID out of range";
1695 err = "address parity error";
1698 err = "byte enable parity error";
1704 msg = kasprintf(GFP_ATOMIC,
1705 "addr=0x%08llx cpu=%d count=%d Err=%08llx:%08llx (%s: %s))\n",
1706 (long long) m->addr, m->cpu, core_err_cnt,
1707 (long long)m->status, (long long)m->misc, optype, err);
1710 * Call the helper to output message
1711 * FIXME: what to do if core_err_cnt > 1? Currently, it generates
1714 if (uncorrected_error || !pvt->is_registered)
1715 edac_mc_handle_error(tp_event, mci,
1716 m->addr >> PAGE_SHIFT,
1717 m->addr & ~PAGE_MASK,
1726 * i7core_check_error Retrieve and process errors reported by the
1727 * hardware. Called by the Core module.
1729 static void i7core_check_error(struct mem_ctl_info *mci)
1731 struct i7core_pvt *pvt = mci->pvt_info;
1737 * MCE first step: Copy all mce errors into a temporary buffer
1738 * We use a double buffering here, to reduce the risk of
1742 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1745 goto check_ce_error;
1747 m = pvt->mce_outentry;
1748 if (pvt->mce_in + count > MCE_LOG_LEN) {
1749 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1751 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1757 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1759 pvt->mce_in += count;
1762 if (pvt->mce_overrun) {
1763 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1766 pvt->mce_overrun = 0;
1770 * MCE second step: parse errors and display
1772 for (i = 0; i < count; i++)
1773 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
1776 * Now, let's increment CE error counts
1779 if (!pvt->is_registered)
1780 i7core_udimm_check_mc_ecc_err(mci);
1782 i7core_rdimm_check_mc_ecc_err(mci);
1786 * i7core_mce_check_error Replicates mcelog routine to get errors
1787 * This routine simply queues mcelog errors, and
1788 * return. The error itself should be handled later
1789 * by i7core_check_error.
1790 * WARNING: As this routine should be called at NMI time, extra care should
1791 * be taken to avoid deadlocks, and to be as fast as possible.
1793 static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
1796 struct mce *mce = (struct mce *)data;
1797 struct i7core_dev *i7_dev;
1798 struct mem_ctl_info *mci;
1799 struct i7core_pvt *pvt;
1801 i7_dev = get_i7core_dev(mce->socketid);
1806 pvt = mci->pvt_info;
1809 * Just let mcelog handle it if the error is
1810 * outside the memory controller
1812 if (((mce->status & 0xffff) >> 7) != 1)
1815 /* Bank 8 registers are the only ones that we know how to handle */
1820 /* Only handle if it is the right mc controller */
1821 if (mce->socketid != pvt->i7core_dev->socket)
1826 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1832 /* Copy memory error at the ringbuffer */
1833 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1835 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1837 /* Handle fatal errors immediately */
1838 if (mce->mcgstatus & 1)
1839 i7core_check_error(mci);
1841 /* Advise mcelog that the errors were handled */
1845 static struct notifier_block i7_mce_dec = {
1846 .notifier_call = i7core_mce_check_error,
1849 struct memdev_dmi_entry {
1853 u16 phys_mem_array_handle;
1854 u16 mem_err_info_handle;
1871 u16 conf_mem_clk_speed;
1872 } __attribute__((__packed__));
1876 * Decode the DRAM Clock Frequency, be paranoid, make sure that all
1877 * memory devices show the same speed, and if they don't then consider
1878 * all speeds to be invalid.
1880 static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq)
1882 int *dclk_freq = _dclk_freq;
1883 u16 dmi_mem_clk_speed;
1885 if (*dclk_freq == -1)
1888 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
1889 struct memdev_dmi_entry *memdev_dmi_entry =
1890 (struct memdev_dmi_entry *)dh;
1891 unsigned long conf_mem_clk_speed_offset =
1892 (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed -
1893 (unsigned long)&memdev_dmi_entry->type;
1894 unsigned long speed_offset =
1895 (unsigned long)&memdev_dmi_entry->speed -
1896 (unsigned long)&memdev_dmi_entry->type;
1898 /* Check that a DIMM is present */
1899 if (memdev_dmi_entry->size == 0)
1903 * Pick the configured speed if it's available, otherwise
1904 * pick the DIMM speed, or we don't have a speed.
1906 if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) {
1908 memdev_dmi_entry->conf_mem_clk_speed;
1909 } else if (memdev_dmi_entry->length > speed_offset) {
1910 dmi_mem_clk_speed = memdev_dmi_entry->speed;
1916 if (*dclk_freq == 0) {
1917 /* First pass, speed was 0 */
1918 if (dmi_mem_clk_speed > 0) {
1919 /* Set speed if a valid speed is read */
1920 *dclk_freq = dmi_mem_clk_speed;
1922 /* Otherwise we don't have a valid speed */
1925 } else if (*dclk_freq > 0 &&
1926 *dclk_freq != dmi_mem_clk_speed) {
1928 * If we have a speed, check that all DIMMS are the same
1929 * speed, otherwise set the speed as invalid.
1937 * The default DCLK frequency is used as a fallback if we
1938 * fail to find anything reliable in the DMI. The value
1939 * is taken straight from the datasheet.
1941 #define DEFAULT_DCLK_FREQ 800
1943 static int get_dclk_freq(void)
1947 dmi_walk(decode_dclk, (void *)&dclk_freq);
1950 return DEFAULT_DCLK_FREQ;
1956 * set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate
1957 * to hardware according to SCRUBINTERVAL formula
1958 * found in datasheet.
1960 static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
1962 struct i7core_pvt *pvt = mci->pvt_info;
1963 struct pci_dev *pdev;
1967 /* Get data from the MC register, function 2 */
1968 pdev = pvt->pci_mcr[2];
1972 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub);
1975 /* Prepare to disable petrol scrub */
1976 dw_scrub &= ~STARTSCRUB;
1977 /* Stop the patrol scrub engine */
1978 write_and_test(pdev, MC_SCRUB_CONTROL,
1979 dw_scrub & ~SCRUBINTERVAL_MASK);
1981 /* Get current status of scrub rate and set bit to disable */
1982 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
1983 dw_ssr &= ~SSR_MODE_MASK;
1984 dw_ssr |= SSR_MODE_DISABLE;
1986 const int cache_line_size = 64;
1987 const u32 freq_dclk_mhz = pvt->dclk_freq;
1988 unsigned long long scrub_interval;
1990 * Translate the desired scrub rate to a register value and
1991 * program the corresponding register value.
1993 scrub_interval = (unsigned long long)freq_dclk_mhz *
1994 cache_line_size * 1000000;
1995 do_div(scrub_interval, new_bw);
1997 if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK)
2000 dw_scrub = SCRUBINTERVAL_MASK & scrub_interval;
2002 /* Start the patrol scrub engine */
2003 pci_write_config_dword(pdev, MC_SCRUB_CONTROL,
2004 STARTSCRUB | dw_scrub);
2006 /* Get current status of scrub rate and set bit to enable */
2007 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
2008 dw_ssr &= ~SSR_MODE_MASK;
2009 dw_ssr |= SSR_MODE_ENABLE;
2011 /* Disable or enable scrubbing */
2012 pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr);
2018 * get_sdram_scrub_rate This routine convert current scrub rate value
2019 * into byte/sec bandwidth accourding to
2020 * SCRUBINTERVAL formula found in datasheet.
2022 static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
2024 struct i7core_pvt *pvt = mci->pvt_info;
2025 struct pci_dev *pdev;
2026 const u32 cache_line_size = 64;
2027 const u32 freq_dclk_mhz = pvt->dclk_freq;
2028 unsigned long long scrub_rate;
2031 /* Get data from the MC register, function 2 */
2032 pdev = pvt->pci_mcr[2];
2036 /* Get current scrub control data */
2037 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval);
2039 /* Mask highest 8-bits to 0 */
2040 scrubval &= SCRUBINTERVAL_MASK;
2044 /* Calculate scrub rate value into byte/sec bandwidth */
2045 scrub_rate = (unsigned long long)freq_dclk_mhz *
2046 1000000 * cache_line_size;
2047 do_div(scrub_rate, scrubval);
2048 return (int)scrub_rate;
2051 static void enable_sdram_scrub_setting(struct mem_ctl_info *mci)
2053 struct i7core_pvt *pvt = mci->pvt_info;
2056 /* Unlock writes to pci registers */
2057 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2059 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2060 pci_lock | MC_CFG_UNLOCK);
2062 mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
2063 mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
2066 static void disable_sdram_scrub_setting(struct mem_ctl_info *mci)
2068 struct i7core_pvt *pvt = mci->pvt_info;
2071 /* Lock writes to pci registers */
2072 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2074 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2075 pci_lock | MC_CFG_LOCK);
2078 static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
2080 pvt->i7core_pci = edac_pci_create_generic_ctl(
2081 &pvt->i7core_dev->pdev[0]->dev,
2083 if (unlikely(!pvt->i7core_pci))
2084 i7core_printk(KERN_WARNING,
2085 "Unable to setup PCI error report via EDAC\n");
2088 static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
2090 if (likely(pvt->i7core_pci))
2091 edac_pci_release_generic_ctl(pvt->i7core_pci);
2093 i7core_printk(KERN_ERR,
2094 "Couldn't find mem_ctl_info for socket %d\n",
2095 pvt->i7core_dev->socket);
2096 pvt->i7core_pci = NULL;
2099 static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
2101 struct mem_ctl_info *mci = i7core_dev->mci;
2102 struct i7core_pvt *pvt;
2104 if (unlikely(!mci || !mci->pvt_info)) {
2105 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
2106 __func__, &i7core_dev->pdev[0]->dev);
2108 i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
2112 pvt = mci->pvt_info;
2114 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
2115 __func__, mci, &i7core_dev->pdev[0]->dev);
2117 /* Disable scrubrate setting */
2118 if (pvt->enable_scrub)
2119 disable_sdram_scrub_setting(mci);
2121 mce_unregister_decode_chain(&i7_mce_dec);
2123 /* Disable EDAC polling */
2124 i7core_pci_ctl_release(pvt);
2126 /* Remove MC sysfs nodes */
2127 edac_mc_del_mc(mci->dev);
2129 debugf1("%s: free mci struct\n", mci->ctl_name);
2130 kfree(mci->ctl_name);
2132 i7core_dev->mci = NULL;
2135 static int i7core_register_mci(struct i7core_dev *i7core_dev)
2137 struct mem_ctl_info *mci;
2138 struct i7core_pvt *pvt;
2140 struct edac_mc_layer layers[2];
2142 /* allocate a new MC control structure */
2144 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2145 layers[0].size = NUM_CHANS;
2146 layers[0].is_virt_csrow = false;
2147 layers[1].type = EDAC_MC_LAYER_SLOT;
2148 layers[1].size = MAX_DIMMS;
2149 layers[1].is_virt_csrow = true;
2150 mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers,
2155 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
2156 __func__, mci, &i7core_dev->pdev[0]->dev);
2158 pvt = mci->pvt_info;
2159 memset(pvt, 0, sizeof(*pvt));
2161 /* Associates i7core_dev and mci for future usage */
2162 pvt->i7core_dev = i7core_dev;
2163 i7core_dev->mci = mci;
2166 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
2167 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
2170 mci->mtype_cap = MEM_FLAG_DDR3;
2171 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2172 mci->edac_cap = EDAC_FLAG_NONE;
2173 mci->mod_name = "i7core_edac.c";
2174 mci->mod_ver = I7CORE_REVISION;
2175 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
2176 i7core_dev->socket);
2177 mci->dev_name = pci_name(i7core_dev->pdev[0]);
2178 mci->ctl_page_to_phys = NULL;
2180 /* Store pci devices at mci for faster access */
2181 rc = mci_bind_devs(mci, i7core_dev);
2182 if (unlikely(rc < 0))
2185 if (pvt->is_registered)
2186 mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs;
2188 mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs;
2190 /* Get dimm basic config */
2191 get_dimm_config(mci);
2192 /* record ptr to the generic device */
2193 mci->dev = &i7core_dev->pdev[0]->dev;
2194 /* Set the function pointer to an actual operation function */
2195 mci->edac_check = i7core_check_error;
2197 /* Enable scrubrate setting */
2198 if (pvt->enable_scrub)
2199 enable_sdram_scrub_setting(mci);
2201 /* add this new MC control structure to EDAC's list of MCs */
2202 if (unlikely(edac_mc_add_mc(mci))) {
2203 debugf0("MC: " __FILE__
2204 ": %s(): failed edac_mc_add_mc()\n", __func__);
2205 /* FIXME: perhaps some code should go here that disables error
2206 * reporting if we just enabled it
2213 /* Default error mask is any memory */
2214 pvt->inject.channel = 0;
2215 pvt->inject.dimm = -1;
2216 pvt->inject.rank = -1;
2217 pvt->inject.bank = -1;
2218 pvt->inject.page = -1;
2219 pvt->inject.col = -1;
2221 /* allocating generic PCI control info */
2222 i7core_pci_ctl_create(pvt);
2224 /* DCLK for scrub rate setting */
2225 pvt->dclk_freq = get_dclk_freq();
2227 mce_register_decode_chain(&i7_mce_dec);
2232 kfree(mci->ctl_name);
2234 i7core_dev->mci = NULL;
2239 * i7core_probe Probe for ONE instance of device to see if it is
2242 * 0 for FOUND a device
2243 * < 0 for error code
2246 static int __devinit i7core_probe(struct pci_dev *pdev,
2247 const struct pci_device_id *id)
2250 struct i7core_dev *i7core_dev;
2252 /* get the pci devices we want to reserve for our use */
2253 mutex_lock(&i7core_edac_lock);
2256 * All memory controllers are allocated at the first pass.
2258 if (unlikely(probed >= 1)) {
2259 mutex_unlock(&i7core_edac_lock);
2264 rc = i7core_get_all_devices();
2265 if (unlikely(rc < 0))
2268 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
2270 rc = i7core_register_mci(i7core_dev);
2271 if (unlikely(rc < 0))
2276 * Nehalem-EX uses a different memory controller. However, as the
2277 * memory controller is not visible on some Nehalem/Nehalem-EP, we
2278 * need to indirectly probe via a X58 PCI device. The same devices
2279 * are found on (some) Nehalem-EX. So, on those machines, the
2280 * probe routine needs to return -ENODEV, as the actual Memory
2281 * Controller registers won't be detected.
2288 i7core_printk(KERN_INFO,
2289 "Driver loaded, %d memory controller(s) found.\n",
2292 mutex_unlock(&i7core_edac_lock);
2296 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2297 i7core_unregister_mci(i7core_dev);
2299 i7core_put_all_devices();
2301 mutex_unlock(&i7core_edac_lock);
2306 * i7core_remove destructor for one instance of device
2309 static void __devexit i7core_remove(struct pci_dev *pdev)
2311 struct i7core_dev *i7core_dev;
2313 debugf0(__FILE__ ": %s()\n", __func__);
2316 * we have a trouble here: pdev value for removal will be wrong, since
2317 * it will point to the X58 register used to detect that the machine
2318 * is a Nehalem or upper design. However, due to the way several PCI
2319 * devices are grouped together to provide MC functionality, we need
2320 * to use a different method for releasing the devices
2323 mutex_lock(&i7core_edac_lock);
2325 if (unlikely(!probed)) {
2326 mutex_unlock(&i7core_edac_lock);
2330 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2331 i7core_unregister_mci(i7core_dev);
2333 /* Release PCI resources */
2334 i7core_put_all_devices();
2338 mutex_unlock(&i7core_edac_lock);
2341 MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2344 * i7core_driver pci_driver structure for this module
2347 static struct pci_driver i7core_driver = {
2348 .name = "i7core_edac",
2349 .probe = i7core_probe,
2350 .remove = __devexit_p(i7core_remove),
2351 .id_table = i7core_pci_tbl,
2355 * i7core_init Module entry function
2356 * Try to initialize this module for its devices
2358 static int __init i7core_init(void)
2362 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2364 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2368 i7core_xeon_pci_fixup(pci_dev_table);
2370 pci_rc = pci_register_driver(&i7core_driver);
2375 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2382 * i7core_exit() Module exit function
2383 * Unregister the driver
2385 static void __exit i7core_exit(void)
2387 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2388 pci_unregister_driver(&i7core_driver);
2391 module_init(i7core_init);
2392 module_exit(i7core_exit);
2394 MODULE_LICENSE("GPL");
2395 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2396 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2397 MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2400 module_param(edac_op_state, int, 0444);
2401 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");