opp: Allow dev_pm_opp_get_opp_table() to return -EPROBE_DEFER
[linux-2.6-microblaze.git] / drivers / edac / i3000_edac.c
1 /*
2  * Intel 3000/3010 Memory Controller kernel module
3  * Copyright (C) 2007 Akamai Technologies, Inc.
4  * Shamelessly copied from:
5  *      Intel D82875P Memory Controller kernel module
6  *      (C) 2003 Linux Networx (http://lnxi.com)
7  *
8  * This file may be distributed under the terms of the
9  * GNU General Public License.
10  */
11
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/edac.h>
17 #include "edac_module.h"
18
19 #define EDAC_MOD_STR            "i3000_edac"
20
21 #define I3000_RANKS             8
22 #define I3000_RANKS_PER_CHANNEL 4
23 #define I3000_CHANNELS          2
24
25 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
26
27 #define I3000_MCHBAR            0x44    /* MCH Memory Mapped Register BAR */
28 #define I3000_MCHBAR_MASK       0xffffc000
29 #define I3000_MMR_WINDOW_SIZE   16384
30
31 #define I3000_EDEAP     0x70    /* Extended DRAM Error Address Pointer (8b)
32                                  *
33                                  * 7:1   reserved
34                                  * 0     bit 32 of address
35                                  */
36 #define I3000_DEAP      0x58    /* DRAM Error Address Pointer (32b)
37                                  *
38                                  * 31:7  address
39                                  * 6:1   reserved
40                                  * 0     Error channel 0/1
41                                  */
42 #define I3000_DEAP_GRAIN                (1 << 7)
43
44 /*
45  * Helper functions to decode the DEAP/EDEAP hardware registers.
46  *
47  * The type promotion here is deliberate; we're deriving an
48  * unsigned long pfn and offset from hardware regs which are u8/u32.
49  */
50
51 static inline unsigned long deap_pfn(u8 edeap, u32 deap)
52 {
53         deap >>= PAGE_SHIFT;
54         deap |= (edeap & 1) << (32 - PAGE_SHIFT);
55         return deap;
56 }
57
58 static inline unsigned long deap_offset(u32 deap)
59 {
60         return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
61 }
62
63 static inline int deap_channel(u32 deap)
64 {
65         return deap & 1;
66 }
67
68 #define I3000_DERRSYN   0x5c    /* DRAM Error Syndrome (8b)
69                                  *
70                                  *  7:0  DRAM ECC Syndrome
71                                  */
72
73 #define I3000_ERRSTS    0xc8    /* Error Status Register (16b)
74                                  *
75                                  * 15:12 reserved
76                                  * 11    MCH Thermal Sensor Event
77                                  *         for SMI/SCI/SERR
78                                  * 10    reserved
79                                  *  9    LOCK to non-DRAM Memory Flag (LCKF)
80                                  *  8    Received Refresh Timeout Flag (RRTOF)
81                                  *  7:2  reserved
82                                  *  1    Multi-bit DRAM ECC Error Flag (DMERR)
83                                  *  0    Single-bit DRAM ECC Error Flag (DSERR)
84                                  */
85 #define I3000_ERRSTS_BITS       0x0b03  /* bits which indicate errors */
86 #define I3000_ERRSTS_UE         0x0002
87 #define I3000_ERRSTS_CE         0x0001
88
89 #define I3000_ERRCMD    0xca    /* Error Command (16b)
90                                  *
91                                  * 15:12 reserved
92                                  * 11    SERR on MCH Thermal Sensor Event
93                                  *         (TSESERR)
94                                  * 10    reserved
95                                  *  9    SERR on LOCK to non-DRAM Memory
96                                  *         (LCKERR)
97                                  *  8    SERR on DRAM Refresh Timeout
98                                  *         (DRTOERR)
99                                  *  7:2  reserved
100                                  *  1    SERR Multi-Bit DRAM ECC Error
101                                  *         (DMERR)
102                                  *  0    SERR on Single-Bit ECC Error
103                                  *         (DSERR)
104                                  */
105
106 /* Intel  MMIO register space - device 0 function 0 - MMR space */
107
108 #define I3000_DRB_SHIFT 25      /* 32MiB grain */
109
110 #define I3000_C0DRB     0x100   /* Channel 0 DRAM Rank Boundary (8b x 4)
111                                  *
112                                  * 7:0   Channel 0 DRAM Rank Boundary Address
113                                  */
114 #define I3000_C1DRB     0x180   /* Channel 1 DRAM Rank Boundary (8b x 4)
115                                  *
116                                  * 7:0   Channel 1 DRAM Rank Boundary Address
117                                  */
118
119 #define I3000_C0DRA     0x108   /* Channel 0 DRAM Rank Attribute (8b x 2)
120                                  *
121                                  * 7     reserved
122                                  * 6:4   DRAM odd Rank Attribute
123                                  * 3     reserved
124                                  * 2:0   DRAM even Rank Attribute
125                                  *
126                                  * Each attribute defines the page
127                                  * size of the corresponding rank:
128                                  *     000: unpopulated
129                                  *     001: reserved
130                                  *     010: 4 KB
131                                  *     011: 8 KB
132                                  *     100: 16 KB
133                                  *     Others: reserved
134                                  */
135 #define I3000_C1DRA     0x188   /* Channel 1 DRAM Rank Attribute (8b x 2) */
136
137 static inline unsigned char odd_rank_attrib(unsigned char dra)
138 {
139         return (dra & 0x70) >> 4;
140 }
141
142 static inline unsigned char even_rank_attrib(unsigned char dra)
143 {
144         return dra & 0x07;
145 }
146
147 #define I3000_C0DRC0    0x120   /* DRAM Controller Mode 0 (32b)
148                                  *
149                                  * 31:30 reserved
150                                  * 29    Initialization Complete (IC)
151                                  * 28:11 reserved
152                                  * 10:8  Refresh Mode Select (RMS)
153                                  * 7     reserved
154                                  * 6:4   Mode Select (SMS)
155                                  * 3:2   reserved
156                                  * 1:0   DRAM Type (DT)
157                                  */
158
159 #define I3000_C0DRC1    0x124   /* DRAM Controller Mode 1 (32b)
160                                  *
161                                  * 31    Enhanced Addressing Enable (ENHADE)
162                                  * 30:0  reserved
163                                  */
164
165 enum i3000p_chips {
166         I3000 = 0,
167 };
168
169 struct i3000_dev_info {
170         const char *ctl_name;
171 };
172
173 struct i3000_error_info {
174         u16 errsts;
175         u8 derrsyn;
176         u8 edeap;
177         u32 deap;
178         u16 errsts2;
179 };
180
181 static const struct i3000_dev_info i3000_devs[] = {
182         [I3000] = {
183                 .ctl_name = "i3000"},
184 };
185
186 static struct pci_dev *mci_pdev;
187 static int i3000_registered = 1;
188 static struct edac_pci_ctl_info *i3000_pci;
189
190 static void i3000_get_error_info(struct mem_ctl_info *mci,
191                                  struct i3000_error_info *info)
192 {
193         struct pci_dev *pdev;
194
195         pdev = to_pci_dev(mci->pdev);
196
197         /*
198          * This is a mess because there is no atomic way to read all the
199          * registers at once and the registers can transition from CE being
200          * overwritten by UE.
201          */
202         pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
203         if (!(info->errsts & I3000_ERRSTS_BITS))
204                 return;
205         pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
206         pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
207         pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
208         pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
209
210         /*
211          * If the error is the same for both reads then the first set
212          * of reads is valid.  If there is a change then there is a CE
213          * with no info and the second set of reads is valid and
214          * should be UE info.
215          */
216         if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
217                 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
218                 pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
219                 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
220         }
221
222         /*
223          * Clear any error bits.
224          * (Yes, we really clear bits by writing 1 to them.)
225          */
226         pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
227                          I3000_ERRSTS_BITS);
228 }
229
230 static int i3000_process_error_info(struct mem_ctl_info *mci,
231                                 struct i3000_error_info *info,
232                                 int handle_errors)
233 {
234         int row, multi_chan, channel;
235         unsigned long pfn, offset;
236
237         multi_chan = mci->csrows[0]->nr_channels - 1;
238
239         if (!(info->errsts & I3000_ERRSTS_BITS))
240                 return 0;
241
242         if (!handle_errors)
243                 return 1;
244
245         if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
246                 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
247                                      -1, -1, -1,
248                                      "UE overwrote CE", "");
249                 info->errsts = info->errsts2;
250         }
251
252         pfn = deap_pfn(info->edeap, info->deap);
253         offset = deap_offset(info->deap);
254         channel = deap_channel(info->deap);
255
256         row = edac_mc_find_csrow_by_page(mci, pfn);
257
258         if (info->errsts & I3000_ERRSTS_UE)
259                 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
260                                      pfn, offset, 0,
261                                      row, -1, -1,
262                                      "i3000 UE", "");
263         else
264                 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
265                                      pfn, offset, info->derrsyn,
266                                      row, multi_chan ? channel : 0, -1,
267                                      "i3000 CE", "");
268
269         return 1;
270 }
271
272 static void i3000_check(struct mem_ctl_info *mci)
273 {
274         struct i3000_error_info info;
275
276         edac_dbg(1, "MC%d\n", mci->mc_idx);
277         i3000_get_error_info(mci, &info);
278         i3000_process_error_info(mci, &info, 1);
279 }
280
281 static int i3000_is_interleaved(const unsigned char *c0dra,
282                                 const unsigned char *c1dra,
283                                 const unsigned char *c0drb,
284                                 const unsigned char *c1drb)
285 {
286         int i;
287
288         /*
289          * If the channels aren't populated identically then
290          * we're not interleaved.
291          */
292         for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
293                 if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
294                         even_rank_attrib(c0dra[i]) !=
295                                                 even_rank_attrib(c1dra[i]))
296                         return 0;
297
298         /*
299          * If the rank boundaries for the two channels are different
300          * then we're not interleaved.
301          */
302         for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
303                 if (c0drb[i] != c1drb[i])
304                         return 0;
305
306         return 1;
307 }
308
309 static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
310 {
311         int rc;
312         int i, j;
313         struct mem_ctl_info *mci = NULL;
314         struct edac_mc_layer layers[2];
315         unsigned long last_cumul_size, nr_pages;
316         int interleaved, nr_channels;
317         unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
318         unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
319         unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
320         unsigned long mchbar;
321         void __iomem *window;
322
323         edac_dbg(0, "MC:\n");
324
325         pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
326         mchbar &= I3000_MCHBAR_MASK;
327         window = ioremap(mchbar, I3000_MMR_WINDOW_SIZE);
328         if (!window) {
329                 printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
330                         mchbar);
331                 return -ENODEV;
332         }
333
334         c0dra[0] = readb(window + I3000_C0DRA + 0);     /* ranks 0,1 */
335         c0dra[1] = readb(window + I3000_C0DRA + 1);     /* ranks 2,3 */
336         c1dra[0] = readb(window + I3000_C1DRA + 0);     /* ranks 0,1 */
337         c1dra[1] = readb(window + I3000_C1DRA + 1);     /* ranks 2,3 */
338
339         for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
340                 c0drb[i] = readb(window + I3000_C0DRB + i);
341                 c1drb[i] = readb(window + I3000_C1DRB + i);
342         }
343
344         iounmap(window);
345
346         /*
347          * Figure out how many channels we have.
348          *
349          * If we have what the datasheet calls "asymmetric channels"
350          * (essentially the same as what was called "virtual single
351          * channel mode" in the i82875) then it's a single channel as
352          * far as EDAC is concerned.
353          */
354         interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
355         nr_channels = interleaved ? 2 : 1;
356
357         layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
358         layers[0].size = I3000_RANKS / nr_channels;
359         layers[0].is_virt_csrow = true;
360         layers[1].type = EDAC_MC_LAYER_CHANNEL;
361         layers[1].size = nr_channels;
362         layers[1].is_virt_csrow = false;
363         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
364         if (!mci)
365                 return -ENOMEM;
366
367         edac_dbg(3, "MC: init mci\n");
368
369         mci->pdev = &pdev->dev;
370         mci->mtype_cap = MEM_FLAG_DDR2;
371
372         mci->edac_ctl_cap = EDAC_FLAG_SECDED;
373         mci->edac_cap = EDAC_FLAG_SECDED;
374
375         mci->mod_name = EDAC_MOD_STR;
376         mci->ctl_name = i3000_devs[dev_idx].ctl_name;
377         mci->dev_name = pci_name(pdev);
378         mci->edac_check = i3000_check;
379         mci->ctl_page_to_phys = NULL;
380
381         /*
382          * The dram rank boundary (DRB) reg values are boundary addresses
383          * for each DRAM rank with a granularity of 32MB.  DRB regs are
384          * cumulative; the last one will contain the total memory
385          * contained in all ranks.
386          *
387          * If we're in interleaved mode then we're only walking through
388          * the ranks of controller 0, so we double all the values we see.
389          */
390         for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
391                 u8 value;
392                 u32 cumul_size;
393                 struct csrow_info *csrow = mci->csrows[i];
394
395                 value = drb[i];
396                 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
397                 if (interleaved)
398                         cumul_size <<= 1;
399                 edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
400                 if (cumul_size == last_cumul_size)
401                         continue;
402
403                 csrow->first_page = last_cumul_size;
404                 csrow->last_page = cumul_size - 1;
405                 nr_pages = cumul_size - last_cumul_size;
406                 last_cumul_size = cumul_size;
407
408                 for (j = 0; j < nr_channels; j++) {
409                         struct dimm_info *dimm = csrow->channels[j]->dimm;
410
411                         dimm->nr_pages = nr_pages / nr_channels;
412                         dimm->grain = I3000_DEAP_GRAIN;
413                         dimm->mtype = MEM_DDR2;
414                         dimm->dtype = DEV_UNKNOWN;
415                         dimm->edac_mode = EDAC_UNKNOWN;
416                 }
417         }
418
419         /*
420          * Clear any error bits.
421          * (Yes, we really clear bits by writing 1 to them.)
422          */
423         pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
424                          I3000_ERRSTS_BITS);
425
426         rc = -ENODEV;
427         if (edac_mc_add_mc(mci)) {
428                 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
429                 goto fail;
430         }
431
432         /* allocating generic PCI control info */
433         i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
434         if (!i3000_pci) {
435                 printk(KERN_WARNING
436                         "%s(): Unable to create PCI control\n",
437                         __func__);
438                 printk(KERN_WARNING
439                         "%s(): PCI error report via EDAC not setup\n",
440                         __func__);
441         }
442
443         /* get this far and it's successful */
444         edac_dbg(3, "MC: success\n");
445         return 0;
446
447 fail:
448         if (mci)
449                 edac_mc_free(mci);
450
451         return rc;
452 }
453
454 /* returns count (>= 0), or negative on error */
455 static int i3000_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
456 {
457         int rc;
458
459         edac_dbg(0, "MC:\n");
460
461         if (pci_enable_device(pdev) < 0)
462                 return -EIO;
463
464         rc = i3000_probe1(pdev, ent->driver_data);
465         if (!mci_pdev)
466                 mci_pdev = pci_dev_get(pdev);
467
468         return rc;
469 }
470
471 static void i3000_remove_one(struct pci_dev *pdev)
472 {
473         struct mem_ctl_info *mci;
474
475         edac_dbg(0, "\n");
476
477         if (i3000_pci)
478                 edac_pci_release_generic_ctl(i3000_pci);
479
480         mci = edac_mc_del_mc(&pdev->dev);
481         if (!mci)
482                 return;
483
484         edac_mc_free(mci);
485 }
486
487 static const struct pci_device_id i3000_pci_tbl[] = {
488         {
489          PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
490          I3000},
491         {
492          0,
493          }                      /* 0 terminated list. */
494 };
495
496 MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
497
498 static struct pci_driver i3000_driver = {
499         .name = EDAC_MOD_STR,
500         .probe = i3000_init_one,
501         .remove = i3000_remove_one,
502         .id_table = i3000_pci_tbl,
503 };
504
505 static int __init i3000_init(void)
506 {
507         int pci_rc;
508
509         edac_dbg(3, "MC:\n");
510
511         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
512         opstate_init();
513
514         pci_rc = pci_register_driver(&i3000_driver);
515         if (pci_rc < 0)
516                 goto fail0;
517
518         if (!mci_pdev) {
519                 i3000_registered = 0;
520                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
521                                         PCI_DEVICE_ID_INTEL_3000_HB, NULL);
522                 if (!mci_pdev) {
523                         edac_dbg(0, "i3000 pci_get_device fail\n");
524                         pci_rc = -ENODEV;
525                         goto fail1;
526                 }
527
528                 pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
529                 if (pci_rc < 0) {
530                         edac_dbg(0, "i3000 init fail\n");
531                         pci_rc = -ENODEV;
532                         goto fail1;
533                 }
534         }
535
536         return 0;
537
538 fail1:
539         pci_unregister_driver(&i3000_driver);
540
541 fail0:
542         pci_dev_put(mci_pdev);
543
544         return pci_rc;
545 }
546
547 static void __exit i3000_exit(void)
548 {
549         edac_dbg(3, "MC:\n");
550
551         pci_unregister_driver(&i3000_driver);
552         if (!i3000_registered) {
553                 i3000_remove_one(mci_pdev);
554                 pci_dev_put(mci_pdev);
555         }
556 }
557
558 module_init(i3000_init);
559 module_exit(i3000_exit);
560
561 MODULE_LICENSE("GPL");
562 MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
563 MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
564
565 module_param(edac_op_state, int, 0444);
566 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");