2 * GHES/EDAC Linux driver
4 * This file may be distributed under the terms of the GNU General Public
7 * Copyright (c) 2013 by Mauro Carvalho Chehab
9 * Red Hat Inc. http://www.redhat.com
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <acpi/ghes.h>
15 #include <linux/edac.h>
16 #include <linux/dmi.h>
17 #include "edac_module.h"
18 #include <ras/ras_event.h>
20 struct ghes_edac_pvt {
21 struct list_head list;
23 struct mem_ctl_info *mci;
25 /* Buffers for the error handling routine */
26 char detail_location[240];
27 char other_detail[160];
31 static atomic_t ghes_init = ATOMIC_INIT(0);
32 static struct ghes_edac_pvt *ghes_pvt;
35 * Sync with other, potentially concurrent callers of
36 * ghes_edac_report_mem_error(). We don't know what the
37 * "inventive" firmware would do.
39 static DEFINE_SPINLOCK(ghes_lock);
41 /* "ghes_edac.force_load=1" skips the platform check */
42 static bool __read_mostly force_load;
43 module_param(force_load, bool, 0);
45 /* Memory Device - Type 17 of SMBIOS spec */
46 struct memdev_dmi_entry {
50 u16 phys_mem_array_handle;
51 u16 mem_err_info_handle;
68 u16 conf_mem_clk_speed;
69 } __attribute__((__packed__));
71 struct ghes_edac_dimm_fill {
72 struct mem_ctl_info *mci;
76 static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
80 if (dh->type == DMI_ENTRY_MEM_DEVICE)
84 static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
86 struct ghes_edac_dimm_fill *dimm_fill = arg;
87 struct mem_ctl_info *mci = dimm_fill->mci;
89 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
90 struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
91 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
93 dimm_fill->count, 0, 0);
95 if (entry->size == 0xffff) {
96 pr_info("Can't get DIMM%i size\n",
98 dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
99 } else if (entry->size == 0x7fff) {
100 dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
102 if (entry->size & 1 << 15)
103 dimm->nr_pages = MiB_TO_PAGES((entry->size &
106 dimm->nr_pages = MiB_TO_PAGES(entry->size);
109 switch (entry->memory_type) {
111 if (entry->type_detail & 1 << 13)
112 dimm->mtype = MEM_RDDR;
114 dimm->mtype = MEM_DDR;
117 if (entry->type_detail & 1 << 13)
118 dimm->mtype = MEM_RDDR2;
120 dimm->mtype = MEM_DDR2;
123 dimm->mtype = MEM_FB_DDR2;
126 if (entry->type_detail & 1 << 13)
127 dimm->mtype = MEM_RDDR3;
129 dimm->mtype = MEM_DDR3;
132 if (entry->type_detail & 1 << 6)
133 dimm->mtype = MEM_RMBS;
134 else if ((entry->type_detail & ((1 << 7) | (1 << 13)))
135 == ((1 << 7) | (1 << 13)))
136 dimm->mtype = MEM_RDR;
137 else if (entry->type_detail & 1 << 7)
138 dimm->mtype = MEM_SDR;
139 else if (entry->type_detail & 1 << 9)
140 dimm->mtype = MEM_EDO;
142 dimm->mtype = MEM_UNKNOWN;
146 * Actually, we can only detect if the memory has bits for
149 if (entry->total_width == entry->data_width)
150 dimm->edac_mode = EDAC_NONE;
152 dimm->edac_mode = EDAC_SECDED;
154 dimm->dtype = DEV_UNKNOWN;
155 dimm->grain = 128; /* Likely, worse case */
158 * FIXME: It shouldn't be hard to also fill the DIMM labels
161 if (dimm->nr_pages) {
162 edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
163 dimm_fill->count, edac_mem_types[dimm->mtype],
164 PAGES_TO_MiB(dimm->nr_pages),
165 (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
166 edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
167 entry->memory_type, entry->type_detail,
168 entry->total_width, entry->data_width);
175 void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
176 struct cper_sec_mem_err *mem_err)
178 enum hw_event_mc_err_type type;
179 struct edac_raw_error_desc *e;
180 struct mem_ctl_info *mci;
181 struct ghes_edac_pvt *pvt = ghes_pvt;
187 pr_err("Internal error: Can't find EDAC structure\n");
192 * We can do the locking below because GHES defers error processing
193 * from NMI to IRQ context. Whenever that changes, we'd at least
196 if (WARN_ON_ONCE(in_nmi()))
199 spin_lock_irqsave(&ghes_lock, flags);
202 e = &mci->error_desc;
204 /* Cleans the error report buffer */
205 memset(e, 0, sizeof (*e));
207 strcpy(e->label, "unknown label");
209 e->other_detail = pvt->other_detail;
213 *pvt->other_detail = '\0';
217 case GHES_SEV_CORRECTED:
218 type = HW_EVENT_ERR_CORRECTED;
220 case GHES_SEV_RECOVERABLE:
221 type = HW_EVENT_ERR_UNCORRECTED;
224 type = HW_EVENT_ERR_FATAL;
228 type = HW_EVENT_ERR_INFO;
231 edac_dbg(1, "error validation_bits: 0x%08llx\n",
232 (long long)mem_err->validation_bits);
234 /* Error type, mapped on e->msg */
235 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
237 switch (mem_err->error_type) {
239 p += sprintf(p, "Unknown");
242 p += sprintf(p, "No error");
245 p += sprintf(p, "Single-bit ECC");
248 p += sprintf(p, "Multi-bit ECC");
251 p += sprintf(p, "Single-symbol ChipKill ECC");
254 p += sprintf(p, "Multi-symbol ChipKill ECC");
257 p += sprintf(p, "Master abort");
260 p += sprintf(p, "Target abort");
263 p += sprintf(p, "Parity Error");
266 p += sprintf(p, "Watchdog timeout");
269 p += sprintf(p, "Invalid address");
272 p += sprintf(p, "Mirror Broken");
275 p += sprintf(p, "Memory Sparing");
278 p += sprintf(p, "Scrub corrected error");
281 p += sprintf(p, "Scrub uncorrected error");
284 p += sprintf(p, "Physical Memory Map-out event");
287 p += sprintf(p, "reserved error (%d)",
288 mem_err->error_type);
291 strcpy(pvt->msg, "unknown error");
295 if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
296 e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT;
297 e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK;
301 if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
302 e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK);
304 /* Memory error location, mapped on e->location */
306 if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
307 p += sprintf(p, "node:%d ", mem_err->node);
308 if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
309 p += sprintf(p, "card:%d ", mem_err->card);
310 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
311 p += sprintf(p, "module:%d ", mem_err->module);
312 if (mem_err->validation_bits & CPER_MEM_VALID_RANK_NUMBER)
313 p += sprintf(p, "rank:%d ", mem_err->rank);
314 if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
315 p += sprintf(p, "bank:%d ", mem_err->bank);
316 if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
317 p += sprintf(p, "row:%d ", mem_err->row);
318 if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
319 p += sprintf(p, "col:%d ", mem_err->column);
320 if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
321 p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
322 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
323 const char *bank = NULL, *device = NULL;
324 dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
325 if (bank != NULL && device != NULL)
326 p += sprintf(p, "DIMM location:%s %s ", bank, device);
328 p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
329 mem_err->mem_dev_handle);
334 /* All other fields are mapped on e->other_detail */
335 p = pvt->other_detail;
336 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
337 u64 status = mem_err->error_status;
339 p += sprintf(p, "status(0x%016llx): ", (long long)status);
340 switch ((status >> 8) & 0xff) {
342 p += sprintf(p, "Error detected internal to the component ");
345 p += sprintf(p, "Error detected in the bus ");
348 p += sprintf(p, "Storage error in DRAM memory ");
351 p += sprintf(p, "Storage error in TLB ");
354 p += sprintf(p, "Storage error in cache ");
357 p += sprintf(p, "Error in one or more functional units ");
360 p += sprintf(p, "component failed self test ");
363 p += sprintf(p, "Overflow or undervalue of internal queue ");
366 p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
369 p += sprintf(p, "Improper access error ");
372 p += sprintf(p, "Access to a memory address which is not mapped to any component ");
375 p += sprintf(p, "Loss of Lockstep ");
378 p += sprintf(p, "Response not associated with a request ");
381 p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
384 p += sprintf(p, "Detection of a PATH_ERROR ");
387 p += sprintf(p, "Bus operation timeout ");
390 p += sprintf(p, "A read was issued to data that has been poisoned ");
393 p += sprintf(p, "reserved ");
397 if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
398 p += sprintf(p, "requestorID: 0x%016llx ",
399 (long long)mem_err->requestor_id);
400 if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
401 p += sprintf(p, "responderID: 0x%016llx ",
402 (long long)mem_err->responder_id);
403 if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
404 p += sprintf(p, "targetID: 0x%016llx ",
405 (long long)mem_err->responder_id);
406 if (p > pvt->other_detail)
409 /* Generate the trace event */
410 grain_bits = fls_long(e->grain);
411 snprintf(pvt->detail_location, sizeof(pvt->detail_location),
412 "APEI location: %s %s", e->location, e->other_detail);
413 trace_mc_event(type, e->msg, e->label, e->error_count,
414 mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
415 (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
416 grain_bits, e->syndrome, pvt->detail_location);
418 edac_raw_mc_handle_error(type, mci, e);
419 spin_unlock_irqrestore(&ghes_lock, flags);
423 * Known systems that are safe to enable this module.
425 static struct acpi_platform_list plat_list[] = {
426 {"HPE ", "Server ", 0, ACPI_SIG_FADT, all_versions},
430 int ghes_edac_register(struct ghes *ghes, struct device *dev)
433 int rc, num_dimm = 0;
434 struct mem_ctl_info *mci;
435 struct edac_mc_layer layers[1];
436 struct ghes_edac_dimm_fill dimm_fill;
439 /* Check if safe to enable on this system */
440 idx = acpi_match_platform_list(plat_list);
441 if (!force_load && idx < 0)
445 * We have only one logical memory controller to which all DIMMs belong.
447 if (atomic_inc_return(&ghes_init) > 1)
450 /* Get the number of DIMMs */
451 dmi_walk(ghes_edac_count_dimms, &num_dimm);
453 /* Check if we've got a bogus BIOS */
459 layers[0].type = EDAC_MC_LAYER_ALL_MEM;
460 layers[0].size = num_dimm;
461 layers[0].is_virt_csrow = true;
463 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));
465 pr_info("Can't allocate memory for EDAC data\n");
469 ghes_pvt = mci->pvt_info;
470 ghes_pvt->ghes = ghes;
474 mci->mtype_cap = MEM_FLAG_EMPTY;
475 mci->edac_ctl_cap = EDAC_FLAG_NONE;
476 mci->edac_cap = EDAC_FLAG_NONE;
477 mci->mod_name = "ghes_edac.c";
478 mci->ctl_name = "ghes_edac";
479 mci->dev_name = "ghes";
482 pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
483 pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
484 pr_info("work on such system. Use this driver with caution\n");
485 } else if (idx < 0) {
486 pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
487 pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
488 pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
489 pr_info("If you find incorrect reports, please contact your hardware vendor\n");
490 pr_info("to correct its BIOS.\n");
491 pr_info("This system has %d DIMM sockets.\n", num_dimm);
497 dmi_walk(ghes_edac_dmidecode, &dimm_fill);
499 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
500 mci->n_layers, 0, 0, 0);
504 dimm->mtype = MEM_UNKNOWN;
505 dimm->dtype = DEV_UNKNOWN;
506 dimm->edac_mode = EDAC_SECDED;
509 rc = edac_mc_add_mc(mci);
511 pr_info("Can't register at EDAC core\n");
518 void ghes_edac_unregister(struct ghes *ghes)
520 struct mem_ctl_info *mci;
523 edac_mc_del_mc(mci->pdev);