drivers/edac/edac_mc.c

   1 /*
   2  * edac_mc kernel module
   3  * (C) 2005, 2006 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Thayne Harbaugh
   8  * Based on work by Dan Hollis <goemon at anime dot net> and others.
   9  *      http://www.anime.net/~goemon/linux-ecc/
  10  *
  11  * Modified by Dave Peterson and Doug Thompson
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/proc_fs.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/smp.h>
  20 #include <linux/init.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/highmem.h>
  23 #include <linux/timer.h>
  24 #include <linux/slab.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/list.h>
  28 #include <linux/ctype.h>
  29 #include <linux/edac.h>
  30 #include <linux/bitops.h>
  31 #include <linux/uaccess.h>
  32 #include <asm/page.h>
  33 #include "edac_mc.h"
  34 #include "edac_module.h"
  35 #include <ras/ras_event.h>
  36
  37 #ifdef CONFIG_EDAC_ATOMIC_SCRUB
  38 #include <asm/edac.h>
  39 #else
  40 #define edac_atomic_scrub(va, size) do { } while (0)
  41 #endif
  42
  43 int edac_op_state = EDAC_OPSTATE_INVAL;
  44 EXPORT_SYMBOL_GPL(edac_op_state);
  45
  46 static int edac_report = EDAC_REPORTING_ENABLED;
  47
  48 /* lock to memory controller's control array */
  49 static DEFINE_MUTEX(mem_ctls_mutex);
  50 static LIST_HEAD(mc_devices);
  51
  52 /*
  53  * Used to lock EDAC MC to just one module, avoiding two drivers e. g.
  54  *      apei/ghes and i7core_edac to be used at the same time.
  55  */
  56 static const char *edac_mc_owner;
  57
  58 int edac_get_report_status(void)
  59 {
  60         return edac_report;
  61 }
  62 EXPORT_SYMBOL_GPL(edac_get_report_status);
  63
  64 void edac_set_report_status(int new)
  65 {
  66         if (new == EDAC_REPORTING_ENABLED ||
  67             new == EDAC_REPORTING_DISABLED ||
  68             new == EDAC_REPORTING_FORCE)
  69                 edac_report = new;
  70 }
  71 EXPORT_SYMBOL_GPL(edac_set_report_status);
  72
  73 static int edac_report_set(const char *str, const struct kernel_param *kp)
  74 {
  75         if (!str)
  76                 return -EINVAL;
  77
  78         if (!strncmp(str, "on", 2))
  79                 edac_report = EDAC_REPORTING_ENABLED;
  80         else if (!strncmp(str, "off", 3))
  81                 edac_report = EDAC_REPORTING_DISABLED;
  82         else if (!strncmp(str, "force", 5))
  83                 edac_report = EDAC_REPORTING_FORCE;
  84
  85         return 0;
  86 }
  87
  88 static int edac_report_get(char *buffer, const struct kernel_param *kp)
  89 {
  90         int ret = 0;
  91
  92         switch (edac_report) {
  93         case EDAC_REPORTING_ENABLED:
  94                 ret = sprintf(buffer, "on");
  95                 break;
  96         case EDAC_REPORTING_DISABLED:
  97                 ret = sprintf(buffer, "off");
  98                 break;
  99         case EDAC_REPORTING_FORCE:
 100                 ret = sprintf(buffer, "force");
 101                 break;
 102         default:
 103                 ret = -EINVAL;
 104                 break;
 105         }
 106
 107         return ret;
 108 }
 109
 110 static const struct kernel_param_ops edac_report_ops = {
 111         .set = edac_report_set,
 112         .get = edac_report_get,
 113 };
 114
 115 module_param_cb(edac_report, &edac_report_ops, &edac_report, 0644);
 116
 117 unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf,
 118                                  unsigned len)
 119 {
 120         struct mem_ctl_info *mci = dimm->mci;
 121         int i, n, count = 0;
 122         char *p = buf;
 123
 124         for (i = 0; i < mci->n_layers; i++) {
 125                 n = snprintf(p, len, "%s %d ",
 126                               edac_layer_name[mci->layers[i].type],
 127                               dimm->location[i]);
 128                 p += n;
 129                 len -= n;
 130                 count += n;
 131                 if (!len)
 132                         break;
 133         }
 134
 135         return count;
 136 }
 137
 138 #ifdef CONFIG_EDAC_DEBUG
 139
 140 static void edac_mc_dump_channel(struct rank_info *chan)
 141 {
 142         edac_dbg(4, "  channel->chan_idx = %d\n", chan->chan_idx);
 143         edac_dbg(4, "    channel = %p\n", chan);
 144         edac_dbg(4, "    channel->csrow = %p\n", chan->csrow);
 145         edac_dbg(4, "    channel->dimm = %p\n", chan->dimm);
 146 }
 147
 148 static void edac_mc_dump_dimm(struct dimm_info *dimm, int number)
 149 {
 150         char location[80];
 151
 152         edac_dimm_info_location(dimm, location, sizeof(location));
 153
 154         edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n",
 155                  dimm->mci->csbased ? "rank" : "dimm",
 156                  number, location, dimm->csrow, dimm->cschannel);
 157         edac_dbg(4, "  dimm = %p\n", dimm);
 158         edac_dbg(4, "  dimm->label = '%s'\n", dimm->label);
 159         edac_dbg(4, "  dimm->nr_pages = 0x%x\n", dimm->nr_pages);
 160         edac_dbg(4, "  dimm->grain = %d\n", dimm->grain);
 161         edac_dbg(4, "  dimm->nr_pages = 0x%x\n", dimm->nr_pages);
 162 }
 163
 164 static void edac_mc_dump_csrow(struct csrow_info *csrow)
 165 {
 166         edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx);
 167         edac_dbg(4, "  csrow = %p\n", csrow);
 168         edac_dbg(4, "  csrow->first_page = 0x%lx\n", csrow->first_page);
 169         edac_dbg(4, "  csrow->last_page = 0x%lx\n", csrow->last_page);
 170         edac_dbg(4, "  csrow->page_mask = 0x%lx\n", csrow->page_mask);
 171         edac_dbg(4, "  csrow->nr_channels = %d\n", csrow->nr_channels);
 172         edac_dbg(4, "  csrow->channels = %p\n", csrow->channels);
 173         edac_dbg(4, "  csrow->mci = %p\n", csrow->mci);
 174 }
 175
 176 static void edac_mc_dump_mci(struct mem_ctl_info *mci)
 177 {
 178         edac_dbg(3, "\tmci = %p\n", mci);
 179         edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap);
 180         edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap);
 181         edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap);
 182         edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check);
 183         edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n",
 184                  mci->nr_csrows, mci->csrows);
 185         edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n",
 186                  mci->tot_dimms, mci->dimms);
 187         edac_dbg(3, "\tdev = %p\n", mci->pdev);
 188         edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n",
 189                  mci->mod_name, mci->ctl_name);
 190         edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info);
 191 }
 192
 193 #endif                          /* CONFIG_EDAC_DEBUG */
 194
 195 const char * const edac_mem_types[] = {
 196         [MEM_EMPTY]     = "Empty",
 197         [MEM_RESERVED]  = "Reserved",
 198         [MEM_UNKNOWN]   = "Unknown",
 199         [MEM_FPM]       = "FPM",
 200         [MEM_EDO]       = "EDO",
 201         [MEM_BEDO]      = "BEDO",
 202         [MEM_SDR]       = "Unbuffered-SDR",
 203         [MEM_RDR]       = "Registered-SDR",
 204         [MEM_DDR]       = "Unbuffered-DDR",
 205         [MEM_RDDR]      = "Registered-DDR",
 206         [MEM_RMBS]      = "RMBS",
 207         [MEM_DDR2]      = "Unbuffered-DDR2",
 208         [MEM_FB_DDR2]   = "FullyBuffered-DDR2",
 209         [MEM_RDDR2]     = "Registered-DDR2",
 210         [MEM_XDR]       = "XDR",
 211         [MEM_DDR3]      = "Unbuffered-DDR3",
 212         [MEM_RDDR3]     = "Registered-DDR3",
 213         [MEM_LRDDR3]    = "Load-Reduced-DDR3-RAM",
 214         [MEM_DDR4]      = "Unbuffered-DDR4",
 215         [MEM_RDDR4]     = "Registered-DDR4",
 216         [MEM_LRDDR4]    = "Load-Reduced-DDR4-RAM",
 217         [MEM_NVDIMM]    = "Non-volatile-RAM",
 218 };
 219 EXPORT_SYMBOL_GPL(edac_mem_types);
 220
 221 /**
 222  * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation
 223  * @p:          pointer to a pointer with the memory offset to be used. At
 224  *              return, this will be incremented to point to the next offset
 225  * @size:       Size of the data structure to be reserved
 226  * @n_elems:    Number of elements that should be reserved
 227  *
 228  * If 'size' is a constant, the compiler will optimize this whole function
 229  * down to either a no-op or the addition of a constant to the value of '*p'.
 230  *
 231  * The 'p' pointer is absolutely needed to keep the proper advancing
 232  * further in memory to the proper offsets when allocating the struct along
 233  * with its embedded structs, as edac_device_alloc_ctl_info() does it
 234  * above, for example.
 235  *
 236  * At return, the pointer 'p' will be incremented to be used on a next call
 237  * to this function.
 238  */
 239 void *edac_align_ptr(void **p, unsigned size, int n_elems)
 240 {
 241         unsigned align, r;
 242         void *ptr = *p;
 243
 244         *p += size * n_elems;
 245
 246         /*
 247          * 'p' can possibly be an unaligned item X such that sizeof(X) is
 248          * 'size'.  Adjust 'p' so that its alignment is at least as
 249          * stringent as what the compiler would provide for X and return
 250          * the aligned result.
 251          * Here we assume that the alignment of a "long long" is the most
 252          * stringent alignment that the compiler will ever provide by default.
 253          * As far as I know, this is a reasonable assumption.
 254          */
 255         if (size > sizeof(long))
 256                 align = sizeof(long long);
 257         else if (size > sizeof(int))
 258                 align = sizeof(long);
 259         else if (size > sizeof(short))
 260                 align = sizeof(int);
 261         else if (size > sizeof(char))
 262                 align = sizeof(short);
 263         else
 264                 return (char *)ptr;
 265
 266         r = (unsigned long)p % align;
 267
 268         if (r == 0)
 269                 return (char *)ptr;
 270
 271         *p += align - r;
 272
 273         return (void *)(((unsigned long)ptr) + align - r);
 274 }
 275
 276 static void _edac_mc_free(struct mem_ctl_info *mci)
 277 {
 278         int i, chn, row;
 279         struct csrow_info *csr;
 280         const unsigned int tot_dimms = mci->tot_dimms;
 281         const unsigned int tot_channels = mci->num_cschannel;
 282         const unsigned int tot_csrows = mci->nr_csrows;
 283
 284         if (mci->dimms) {
 285                 for (i = 0; i < tot_dimms; i++)
 286                         kfree(mci->dimms[i]);
 287                 kfree(mci->dimms);
 288         }
 289         if (mci->csrows) {
 290                 for (row = 0; row < tot_csrows; row++) {
 291                         csr = mci->csrows[row];
 292                         if (csr) {
 293                                 if (csr->channels) {
 294                                         for (chn = 0; chn < tot_channels; chn++)
 295                                                 kfree(csr->channels[chn]);
 296                                         kfree(csr->channels);
 297                                 }
 298                                 kfree(csr);
 299                         }
 300                 }
 301                 kfree(mci->csrows);
 302         }
 303         kfree(mci);
 304 }
 305
 306 struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
 307                                    unsigned n_layers,
 308                                    struct edac_mc_layer *layers,
 309                                    unsigned sz_pvt)
 310 {
 311         struct mem_ctl_info *mci;
 312         struct edac_mc_layer *layer;
 313         struct csrow_info *csr;
 314         struct rank_info *chan;
 315         struct dimm_info *dimm;
 316         u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
 317         unsigned pos[EDAC_MAX_LAYERS];
 318         unsigned size, tot_dimms = 1, count = 1;
 319         unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0;
 320         void *pvt, *p, *ptr = NULL;
 321         int i, j, row, chn, n, len, off;
 322         bool per_rank = false;
 323
 324         BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0);
 325         /*
 326          * Calculate the total amount of dimms and csrows/cschannels while
 327          * in the old API emulation mode
 328          */
 329         for (i = 0; i < n_layers; i++) {
 330                 tot_dimms *= layers[i].size;
 331                 if (layers[i].is_virt_csrow)
 332                         tot_csrows *= layers[i].size;
 333                 else
 334                         tot_channels *= layers[i].size;
 335
 336                 if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT)
 337                         per_rank = true;
 338         }
 339
 340         /* Figure out the offsets of the various items from the start of an mc
 341          * structure.  We want the alignment of each item to be at least as
 342          * stringent as what the compiler would provide if we could simply
 343          * hardcode everything into a single struct.
 344          */
 345         mci = edac_align_ptr(&ptr, sizeof(*mci), 1);
 346         layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers);
 347         for (i = 0; i < n_layers; i++) {
 348                 count *= layers[i].size;
 349                 edac_dbg(4, "errcount layer %d size %d\n", i, count);
 350                 ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
 351                 ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
 352                 tot_errcount += 2 * count;
 353         }
 354
 355         edac_dbg(4, "allocating %d error counters\n", tot_errcount);
 356         pvt = edac_align_ptr(&ptr, sz_pvt, 1);
 357         size = ((unsigned long)pvt) + sz_pvt;
 358
 359         edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n",
 360                  size,
 361                  tot_dimms,
 362                  per_rank ? "ranks" : "dimms",
 363                  tot_csrows * tot_channels);
 364
 365         mci = kzalloc(size, GFP_KERNEL);
 366         if (mci == NULL)
 367                 return NULL;
 368
 369         /* Adjust pointers so they point within the memory we just allocated
 370          * rather than an imaginary chunk of memory located at address 0.
 371          */
 372         layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer));
 373         for (i = 0; i < n_layers; i++) {
 374                 mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i]));
 375                 mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i]));
 376         }
 377         pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL;
 378
 379         /* setup index and various internal pointers */
 380         mci->mc_idx = mc_num;
 381         mci->tot_dimms = tot_dimms;
 382         mci->pvt_info = pvt;
 383         mci->n_layers = n_layers;
 384         mci->layers = layer;
 385         memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
 386         mci->nr_csrows = tot_csrows;
 387         mci->num_cschannel = tot_channels;
 388         mci->csbased = per_rank;
 389
 390         /*
 391          * Alocate and fill the csrow/channels structs
 392          */
 393         mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL);
 394         if (!mci->csrows)
 395                 goto error;
 396         for (row = 0; row < tot_csrows; row++) {
 397                 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL);
 398                 if (!csr)
 399                         goto error;
 400                 mci->csrows[row] = csr;
 401                 csr->csrow_idx = row;
 402                 csr->mci = mci;
 403                 csr->nr_channels = tot_channels;
 404                 csr->channels = kcalloc(tot_channels, sizeof(*csr->channels),
 405                                         GFP_KERNEL);
 406                 if (!csr->channels)
 407                         goto error;
 408
 409                 for (chn = 0; chn < tot_channels; chn++) {
 410                         chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL);
 411                         if (!chan)
 412                                 goto error;
 413                         csr->channels[chn] = chan;
 414                         chan->chan_idx = chn;
 415                         chan->csrow = csr;
 416                 }
 417         }
 418
 419         /*
 420          * Allocate and fill the dimm structs
 421          */
 422         mci->dimms  = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL);
 423         if (!mci->dimms)
 424                 goto error;
 425
 426         memset(&pos, 0, sizeof(pos));
 427         row = 0;
 428         chn = 0;
 429         for (i = 0; i < tot_dimms; i++) {
 430                 chan = mci->csrows[row]->channels[chn];
 431                 off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]);
 432                 if (off < 0 || off >= tot_dimms) {
 433                         edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n");
 434                         goto error;
 435                 }
 436
 437                 dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL);
 438                 if (!dimm)
 439                         goto error;
 440                 mci->dimms[off] = dimm;
 441                 dimm->mci = mci;
 442
 443                 /*
 444                  * Copy DIMM location and initialize it.
 445                  */
 446                 len = sizeof(dimm->label);
 447                 p = dimm->label;
 448                 n = snprintf(p, len, "mc#%u", mc_num);
 449                 p += n;
 450                 len -= n;
 451                 for (j = 0; j < n_layers; j++) {
 452                         n = snprintf(p, len, "%s#%u",
 453                                      edac_layer_name[layers[j].type],
 454                                      pos[j]);
 455                         p += n;
 456                         len -= n;
 457                         dimm->location[j] = pos[j];
 458
 459                         if (len <= 0)
 460                                 break;
 461                 }
 462
 463                 /* Link it to the csrows old API data */
 464                 chan->dimm = dimm;
 465                 dimm->csrow = row;
 466                 dimm->cschannel = chn;
 467
 468                 /* Increment csrow location */
 469                 if (layers[0].is_virt_csrow) {
 470                         chn++;
 471                         if (chn == tot_channels) {
 472                                 chn = 0;
 473                                 row++;
 474                         }
 475                 } else {
 476                         row++;
 477                         if (row == tot_csrows) {
 478                                 row = 0;
 479                                 chn++;
 480                         }
 481                 }
 482
 483                 /* Increment dimm location */
 484                 for (j = n_layers - 1; j >= 0; j--) {
 485                         pos[j]++;
 486                         if (pos[j] < layers[j].size)
 487                                 break;
 488                         pos[j] = 0;
 489                 }
 490         }
 491
 492         mci->op_state = OP_ALLOC;
 493
 494         return mci;
 495
 496 error:
 497         _edac_mc_free(mci);
 498
 499         return NULL;
 500 }
 501 EXPORT_SYMBOL_GPL(edac_mc_alloc);
 502
 503 void edac_mc_free(struct mem_ctl_info *mci)
 504 {
 505         edac_dbg(1, "\n");
 506
 507         /* If we're not yet registered with sysfs free only what was allocated
 508          * in edac_mc_alloc().
 509          */
 510         if (!device_is_registered(&mci->dev)) {
 511                 _edac_mc_free(mci);
 512                 return;
 513         }
 514
 515         /* the mci instance is freed here, when the sysfs object is dropped */
 516         edac_unregister_sysfs(mci);
 517 }
 518 EXPORT_SYMBOL_GPL(edac_mc_free);
 519
 520 bool edac_has_mcs(void)
 521 {
 522         bool ret;
 523
 524         mutex_lock(&mem_ctls_mutex);
 525
 526         ret = list_empty(&mc_devices);
 527
 528         mutex_unlock(&mem_ctls_mutex);
 529
 530         return !ret;
 531 }
 532 EXPORT_SYMBOL_GPL(edac_has_mcs);
 533
 534 /* Caller must hold mem_ctls_mutex */
 535 static struct mem_ctl_info *__find_mci_by_dev(struct device *dev)
 536 {
 537         struct mem_ctl_info *mci;
 538         struct list_head *item;
 539
 540         edac_dbg(3, "\n");
 541
 542         list_for_each(item, &mc_devices) {
 543                 mci = list_entry(item, struct mem_ctl_info, link);
 544
 545                 if (mci->pdev == dev)
 546                         return mci;
 547         }
 548
 549         return NULL;
 550 }
 551
 552 /**
 553  * find_mci_by_dev
 554  *
 555  *      scan list of controllers looking for the one that manages
 556  *      the 'dev' device
 557  * @dev: pointer to a struct device related with the MCI
 558  */
 559 struct mem_ctl_info *find_mci_by_dev(struct device *dev)
 560 {
 561         struct mem_ctl_info *ret;
 562
 563         mutex_lock(&mem_ctls_mutex);
 564         ret = __find_mci_by_dev(dev);
 565         mutex_unlock(&mem_ctls_mutex);
 566
 567         return ret;
 568 }
 569 EXPORT_SYMBOL_GPL(find_mci_by_dev);
 570
 571 /*
 572  * edac_mc_workq_function
 573  *      performs the operation scheduled by a workq request
 574  */
 575 static void edac_mc_workq_function(struct work_struct *work_req)
 576 {
 577         struct delayed_work *d_work = to_delayed_work(work_req);
 578         struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work);
 579
 580         mutex_lock(&mem_ctls_mutex);
 581
 582         if (mci->op_state != OP_RUNNING_POLL) {
 583                 mutex_unlock(&mem_ctls_mutex);
 584                 return;
 585         }
 586
 587         if (edac_op_state == EDAC_OPSTATE_POLL)
 588                 mci->edac_check(mci);
 589
 590         mutex_unlock(&mem_ctls_mutex);
 591
 592         /* Queue ourselves again. */
 593         edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
 594 }
 595
 596 /*
 597  * edac_mc_reset_delay_period(unsigned long value)
 598  *
 599  *      user space has updated our poll period value, need to
 600  *      reset our workq delays
 601  */
 602 void edac_mc_reset_delay_period(unsigned long value)
 603 {
 604         struct mem_ctl_info *mci;
 605         struct list_head *item;
 606
 607         mutex_lock(&mem_ctls_mutex);
 608
 609         list_for_each(item, &mc_devices) {
 610                 mci = list_entry(item, struct mem_ctl_info, link);
 611
 612                 if (mci->op_state == OP_RUNNING_POLL)
 613                         edac_mod_work(&mci->work, value);
 614         }
 615         mutex_unlock(&mem_ctls_mutex);
 616 }
 617
 618
 619
 620 /* Return 0 on success, 1 on failure.
 621  * Before calling this function, caller must
 622  * assign a unique value to mci->mc_idx.
 623  *
 624  *      locking model:
 625  *
 626  *              called with the mem_ctls_mutex lock held
 627  */
 628 static int add_mc_to_global_list(struct mem_ctl_info *mci)
 629 {
 630         struct list_head *item, *insert_before;
 631         struct mem_ctl_info *p;
 632
 633         insert_before = &mc_devices;
 634
 635         p = __find_mci_by_dev(mci->pdev);
 636         if (unlikely(p != NULL))
 637                 goto fail0;
 638
 639         list_for_each(item, &mc_devices) {
 640                 p = list_entry(item, struct mem_ctl_info, link);
 641
 642                 if (p->mc_idx >= mci->mc_idx) {
 643                         if (unlikely(p->mc_idx == mci->mc_idx))
 644                                 goto fail1;
 645
 646                         insert_before = item;
 647                         break;
 648                 }
 649         }
 650
 651         list_add_tail_rcu(&mci->link, insert_before);
 652         return 0;
 653
 654 fail0:
 655         edac_printk(KERN_WARNING, EDAC_MC,
 656                 "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev),
 657                 edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx);
 658         return 1;
 659
 660 fail1:
 661         edac_printk(KERN_WARNING, EDAC_MC,
 662                 "bug in low-level driver: attempt to assign\n"
 663                 "    duplicate mc_idx %d in %s()\n", p->mc_idx, __func__);
 664         return 1;
 665 }
 666
 667 static int del_mc_from_global_list(struct mem_ctl_info *mci)
 668 {
 669         list_del_rcu(&mci->link);
 670
 671         /* these are for safe removal of devices from global list while
 672          * NMI handlers may be traversing list
 673          */
 674         synchronize_rcu();
 675         INIT_LIST_HEAD(&mci->link);
 676
 677         return list_empty(&mc_devices);
 678 }
 679
 680 struct mem_ctl_info *edac_mc_find(int idx)
 681 {
 682         struct mem_ctl_info *mci;
 683         struct list_head *item;
 684
 685         mutex_lock(&mem_ctls_mutex);
 686
 687         list_for_each(item, &mc_devices) {
 688                 mci = list_entry(item, struct mem_ctl_info, link);
 689                 if (mci->mc_idx == idx)
 690                         goto unlock;
 691         }
 692
 693         mci = NULL;
 694 unlock:
 695         mutex_unlock(&mem_ctls_mutex);
 696         return mci;
 697 }
 698 EXPORT_SYMBOL(edac_mc_find);
 699
 700 const char *edac_get_owner(void)
 701 {
 702         return edac_mc_owner;
 703 }
 704 EXPORT_SYMBOL_GPL(edac_get_owner);
 705
 706 /* FIXME - should a warning be printed if no error detection? correction? */
 707 int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
 708                                const struct attribute_group **groups)
 709 {
 710         int ret = -EINVAL;
 711         edac_dbg(0, "\n");
 712
 713 #ifdef CONFIG_EDAC_DEBUG
 714         if (edac_debug_level >= 3)
 715                 edac_mc_dump_mci(mci);
 716
 717         if (edac_debug_level >= 4) {
 718                 int i;
 719
 720                 for (i = 0; i < mci->nr_csrows; i++) {
 721                         struct csrow_info *csrow = mci->csrows[i];
 722                         u32 nr_pages = 0;
 723                         int j;
 724
 725                         for (j = 0; j < csrow->nr_channels; j++)
 726                                 nr_pages += csrow->channels[j]->dimm->nr_pages;
 727                         if (!nr_pages)
 728                                 continue;
 729                         edac_mc_dump_csrow(csrow);
 730                         for (j = 0; j < csrow->nr_channels; j++)
 731                                 if (csrow->channels[j]->dimm->nr_pages)
 732                                         edac_mc_dump_channel(csrow->channels[j]);
 733                 }
 734                 for (i = 0; i < mci->tot_dimms; i++)
 735                         if (mci->dimms[i]->nr_pages)
 736                                 edac_mc_dump_dimm(mci->dimms[i], i);
 737         }
 738 #endif
 739         mutex_lock(&mem_ctls_mutex);
 740
 741         if (edac_mc_owner && edac_mc_owner != mci->mod_name) {
 742                 ret = -EPERM;
 743                 goto fail0;
 744         }
 745
 746         if (add_mc_to_global_list(mci))
 747                 goto fail0;
 748
 749         /* set load time so that error rate can be tracked */
 750         mci->start_time = jiffies;
 751
 752         mci->bus = edac_get_sysfs_subsys();
 753
 754         if (edac_create_sysfs_mci_device(mci, groups)) {
 755                 edac_mc_printk(mci, KERN_WARNING,
 756                         "failed to create sysfs device\n");
 757                 goto fail1;
 758         }
 759
 760         if (mci->edac_check) {
 761                 mci->op_state = OP_RUNNING_POLL;
 762
 763                 INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function);
 764                 edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
 765
 766         } else {
 767                 mci->op_state = OP_RUNNING_INTERRUPT;
 768         }
 769
 770         /* Report action taken */
 771         edac_mc_printk(mci, KERN_INFO,
 772                 "Giving out device to module %s controller %s: DEV %s (%s)\n",
 773                 mci->mod_name, mci->ctl_name, mci->dev_name,
 774                 edac_op_state_to_string(mci->op_state));
 775
 776         edac_mc_owner = mci->mod_name;
 777
 778         mutex_unlock(&mem_ctls_mutex);
 779         return 0;
 780
 781 fail1:
 782         del_mc_from_global_list(mci);
 783
 784 fail0:
 785         mutex_unlock(&mem_ctls_mutex);
 786         return ret;
 787 }
 788 EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups);
 789
 790 struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
 791 {
 792         struct mem_ctl_info *mci;
 793
 794         edac_dbg(0, "\n");
 795
 796         mutex_lock(&mem_ctls_mutex);
 797
 798         /* find the requested mci struct in the global list */
 799         mci = __find_mci_by_dev(dev);
 800         if (mci == NULL) {
 801                 mutex_unlock(&mem_ctls_mutex);
 802                 return NULL;
 803         }
 804
 805         /* mark MCI offline: */
 806         mci->op_state = OP_OFFLINE;
 807
 808         if (del_mc_from_global_list(mci))
 809                 edac_mc_owner = NULL;
 810
 811         mutex_unlock(&mem_ctls_mutex);
 812
 813         if (mci->edac_check)
 814                 edac_stop_work(&mci->work);
 815
 816         /* remove from sysfs */
 817         edac_remove_sysfs_mci_device(mci);
 818
 819         edac_printk(KERN_INFO, EDAC_MC,
 820                 "Removed device %d for %s %s: DEV %s\n", mci->mc_idx,
 821                 mci->mod_name, mci->ctl_name, edac_dev_name(mci));
 822
 823         return mci;
 824 }
 825 EXPORT_SYMBOL_GPL(edac_mc_del_mc);
 826
 827 static void edac_mc_scrub_block(unsigned long page, unsigned long offset,
 828                                 u32 size)
 829 {
 830         struct page *pg;
 831         void *virt_addr;
 832         unsigned long flags = 0;
 833
 834         edac_dbg(3, "\n");
 835
 836         /* ECC error page was not in our memory. Ignore it. */
 837         if (!pfn_valid(page))
 838                 return;
 839
 840         /* Find the actual page structure then map it and fix */
 841         pg = pfn_to_page(page);
 842
 843         if (PageHighMem(pg))
 844                 local_irq_save(flags);
 845
 846         virt_addr = kmap_atomic(pg);
 847
 848         /* Perform architecture specific atomic scrub operation */
 849         edac_atomic_scrub(virt_addr + offset, size);
 850
 851         /* Unmap and complete */
 852         kunmap_atomic(virt_addr);
 853
 854         if (PageHighMem(pg))
 855                 local_irq_restore(flags);
 856 }
 857
 858 /* FIXME - should return -1 */
 859 int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
 860 {
 861         struct csrow_info **csrows = mci->csrows;
 862         int row, i, j, n;
 863
 864         edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page);
 865         row = -1;
 866
 867         for (i = 0; i < mci->nr_csrows; i++) {
 868                 struct csrow_info *csrow = csrows[i];
 869                 n = 0;
 870                 for (j = 0; j < csrow->nr_channels; j++) {
 871                         struct dimm_info *dimm = csrow->channels[j]->dimm;
 872                         n += dimm->nr_pages;
 873                 }
 874                 if (n == 0)
 875                         continue;
 876
 877                 edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n",
 878                          mci->mc_idx,
 879                          csrow->first_page, page, csrow->last_page,
 880                          csrow->page_mask);
 881
 882                 if ((page >= csrow->first_page) &&
 883                     (page <= csrow->last_page) &&
 884                     ((page & csrow->page_mask) ==
 885                      (csrow->first_page & csrow->page_mask))) {
 886                         row = i;
 887                         break;
 888                 }
 889         }
 890
 891         if (row == -1)
 892                 edac_mc_printk(mci, KERN_ERR,
 893                         "could not look up page error address %lx\n",
 894                         (unsigned long)page);
 895
 896         return row;
 897 }
 898 EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page);
 899
 900 const char *edac_layer_name[] = {
 901         [EDAC_MC_LAYER_BRANCH] = "branch",
 902         [EDAC_MC_LAYER_CHANNEL] = "channel",
 903         [EDAC_MC_LAYER_SLOT] = "slot",
 904         [EDAC_MC_LAYER_CHIP_SELECT] = "csrow",
 905         [EDAC_MC_LAYER_ALL_MEM] = "memory",
 906 };
 907 EXPORT_SYMBOL_GPL(edac_layer_name);
 908
 909 static void edac_inc_ce_error(struct mem_ctl_info *mci,
 910                               bool enable_per_layer_report,
 911                               const int pos[EDAC_MAX_LAYERS],
 912                               const u16 count)
 913 {
 914         int i, index = 0;
 915
 916         mci->ce_mc += count;
 917
 918         if (!enable_per_layer_report) {
 919                 mci->ce_noinfo_count += count;
 920                 return;
 921         }
 922
 923         for (i = 0; i < mci->n_layers; i++) {
 924                 if (pos[i] < 0)
 925                         break;
 926                 index += pos[i];
 927                 mci->ce_per_layer[i][index] += count;
 928
 929                 if (i < mci->n_layers - 1)
 930                         index *= mci->layers[i + 1].size;
 931         }
 932 }
 933
 934 static void edac_inc_ue_error(struct mem_ctl_info *mci,
 935                                     bool enable_per_layer_report,
 936                                     const int pos[EDAC_MAX_LAYERS],
 937                                     const u16 count)
 938 {
 939         int i, index = 0;
 940
 941         mci->ue_mc += count;
 942
 943         if (!enable_per_layer_report) {
 944                 mci->ue_noinfo_count += count;
 945                 return;
 946         }
 947
 948         for (i = 0; i < mci->n_layers; i++) {
 949                 if (pos[i] < 0)
 950                         break;
 951                 index += pos[i];
 952                 mci->ue_per_layer[i][index] += count;
 953
 954                 if (i < mci->n_layers - 1)
 955                         index *= mci->layers[i + 1].size;
 956         }
 957 }
 958
 959 static void edac_ce_error(struct mem_ctl_info *mci,
 960                           const u16 error_count,
 961                           const int pos[EDAC_MAX_LAYERS],
 962                           const char *msg,
 963                           const char *location,
 964                           const char *label,
 965                           const char *detail,
 966                           const char *other_detail,
 967                           const bool enable_per_layer_report,
 968                           const unsigned long page_frame_number,
 969                           const unsigned long offset_in_page,
 970                           long grain)
 971 {
 972         unsigned long remapped_page;
 973         char *msg_aux = "";
 974
 975         if (*msg)
 976                 msg_aux = " ";
 977
 978         if (edac_mc_get_log_ce()) {
 979                 if (other_detail && *other_detail)
 980                         edac_mc_printk(mci, KERN_WARNING,
 981                                        "%d CE %s%son %s (%s %s - %s)\n",
 982                                        error_count, msg, msg_aux, label,
 983                                        location, detail, other_detail);
 984                 else
 985                         edac_mc_printk(mci, KERN_WARNING,
 986                                        "%d CE %s%son %s (%s %s)\n",
 987                                        error_count, msg, msg_aux, label,
 988                                        location, detail);
 989         }
 990         edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count);
 991
 992         if (mci->scrub_mode == SCRUB_SW_SRC) {
 993                 /*
 994                         * Some memory controllers (called MCs below) can remap
 995                         * memory so that it is still available at a different
 996                         * address when PCI devices map into memory.
 997                         * MC's that can't do this, lose the memory where PCI
 998                         * devices are mapped. This mapping is MC-dependent
 999                         * and so we call back into the MC driver for it to
1000                         * map the MC page to a physical (CPU) page which can
1001                         * then be mapped to a virtual page - which can then
1002                         * be scrubbed.
1003                         */
1004                 remapped_page = mci->ctl_page_to_phys ?
1005                         mci->ctl_page_to_phys(mci, page_frame_number) :
1006                         page_frame_number;
1007
1008                 edac_mc_scrub_block(remapped_page,
1009                                         offset_in_page, grain);
1010         }
1011 }
1012
1013 static void edac_ue_error(struct mem_ctl_info *mci,
1014                           const u16 error_count,
1015                           const int pos[EDAC_MAX_LAYERS],
1016                           const char *msg,
1017                           const char *location,
1018                           const char *label,
1019                           const char *detail,
1020                           const char *other_detail,
1021                           const bool enable_per_layer_report)
1022 {
1023         char *msg_aux = "";
1024
1025         if (*msg)
1026                 msg_aux = " ";
1027
1028         if (edac_mc_get_log_ue()) {
1029                 if (other_detail && *other_detail)
1030                         edac_mc_printk(mci, KERN_WARNING,
1031                                        "%d UE %s%son %s (%s %s - %s)\n",
1032                                        error_count, msg, msg_aux, label,
1033                                        location, detail, other_detail);
1034                 else
1035                         edac_mc_printk(mci, KERN_WARNING,
1036                                        "%d UE %s%son %s (%s %s)\n",
1037                                        error_count, msg, msg_aux, label,
1038                                        location, detail);
1039         }
1040
1041         if (edac_mc_get_panic_on_ue()) {
1042                 if (other_detail && *other_detail)
1043                         panic("UE %s%son %s (%s%s - %s)\n",
1044                               msg, msg_aux, label, location, detail, other_detail);
1045                 else
1046                         panic("UE %s%son %s (%s%s)\n",
1047                               msg, msg_aux, label, location, detail);
1048         }
1049
1050         edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count);
1051 }
1052
1053 void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type,
1054                               struct mem_ctl_info *mci,
1055                               struct edac_raw_error_desc *e)
1056 {
1057         char detail[80];
1058         int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
1059
1060         /* Memory type dependent details about the error */
1061         if (type == HW_EVENT_ERR_CORRECTED) {
1062                 snprintf(detail, sizeof(detail),
1063                         "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx",
1064                         e->page_frame_number, e->offset_in_page,
1065                         e->grain, e->syndrome);
1066                 edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label,
1067                               detail, e->other_detail, e->enable_per_layer_report,
1068                               e->page_frame_number, e->offset_in_page, e->grain);
1069         } else {
1070                 snprintf(detail, sizeof(detail),
1071                         "page:0x%lx offset:0x%lx grain:%ld",
1072                         e->page_frame_number, e->offset_in_page, e->grain);
1073
1074                 edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label,
1075                               detail, e->other_detail, e->enable_per_layer_report);
1076         }
1077
1078
1079 }
1080 EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error);
1081
1082 void edac_mc_handle_error(const enum hw_event_mc_err_type type,
1083                           struct mem_ctl_info *mci,
1084                           const u16 error_count,
1085                           const unsigned long page_frame_number,
1086                           const unsigned long offset_in_page,
1087                           const unsigned long syndrome,
1088                           const int top_layer,
1089                           const int mid_layer,
1090                           const int low_layer,
1091                           const char *msg,
1092                           const char *other_detail)
1093 {
1094         char *p;
1095         int row = -1, chan = -1;
1096         int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer };
1097         int i, n_labels = 0;
1098         u8 grain_bits;
1099         struct edac_raw_error_desc *e = &mci->error_desc;
1100
1101         edac_dbg(3, "MC%d\n", mci->mc_idx);
1102
1103         /* Fills the error report buffer */
1104         memset(e, 0, sizeof (*e));
1105         e->error_count = error_count;
1106         e->top_layer = top_layer;
1107         e->mid_layer = mid_layer;
1108         e->low_layer = low_layer;
1109         e->page_frame_number = page_frame_number;
1110         e->offset_in_page = offset_in_page;
1111         e->syndrome = syndrome;
1112         e->msg = msg;
1113         e->other_detail = other_detail;
1114
1115         /*
1116          * Check if the event report is consistent and if the memory
1117          * location is known. If it is known, enable_per_layer_report will be
1118          * true, the DIMM(s) label info will be filled and the per-layer
1119          * error counters will be incremented.
1120          */
1121         for (i = 0; i < mci->n_layers; i++) {
1122                 if (pos[i] >= (int)mci->layers[i].size) {
1123
1124                         edac_mc_printk(mci, KERN_ERR,
1125                                        "INTERNAL ERROR: %s value is out of range (%d >= %d)\n",
1126                                        edac_layer_name[mci->layers[i].type],
1127                                        pos[i], mci->layers[i].size);
1128                         /*
1129                          * Instead of just returning it, let's use what's
1130                          * known about the error. The increment routines and
1131                          * the DIMM filter logic will do the right thing by
1132                          * pointing the likely damaged DIMMs.
1133                          */
1134                         pos[i] = -1;
1135                 }
1136                 if (pos[i] >= 0)
1137                         e->enable_per_layer_report = true;
1138         }
1139
1140         /*
1141          * Get the dimm label/grain that applies to the match criteria.
1142          * As the error algorithm may not be able to point to just one memory
1143          * stick, the logic here will get all possible labels that could
1144          * pottentially be affected by the error.
1145          * On FB-DIMM memory controllers, for uncorrected errors, it is common
1146          * to have only the MC channel and the MC dimm (also called "branch")
1147          * but the channel is not known, as the memory is arranged in pairs,
1148          * where each memory belongs to a separate channel within the same
1149          * branch.
1150          */
1151         p = e->label;
1152         *p = '\0';
1153
1154         for (i = 0; i < mci->tot_dimms; i++) {
1155                 struct dimm_info *dimm = mci->dimms[i];
1156
1157                 if (top_layer >= 0 && top_layer != dimm->location[0])
1158                         continue;
1159                 if (mid_layer >= 0 && mid_layer != dimm->location[1])
1160                         continue;
1161                 if (low_layer >= 0 && low_layer != dimm->location[2])
1162                         continue;
1163
1164                 /* get the max grain, over the error match range */
1165                 if (dimm->grain > e->grain)
1166                         e->grain = dimm->grain;
1167
1168                 /*
1169                  * If the error is memory-controller wide, there's no need to
1170                  * seek for the affected DIMMs because the whole
1171                  * channel/memory controller/...  may be affected.
1172                  * Also, don't show errors for empty DIMM slots.
1173                  */
1174                 if (e->enable_per_layer_report && dimm->nr_pages) {
1175                         if (n_labels >= EDAC_MAX_LABELS) {
1176                                 e->enable_per_layer_report = false;
1177                                 break;
1178                         }
1179                         n_labels++;
1180                         if (p != e->label) {
1181                                 strcpy(p, OTHER_LABEL);
1182                                 p += strlen(OTHER_LABEL);
1183                         }
1184                         strcpy(p, dimm->label);
1185                         p += strlen(p);
1186                         *p = '\0';
1187
1188                         /*
1189                          * get csrow/channel of the DIMM, in order to allow
1190                          * incrementing the compat API counters
1191                          */
1192                         edac_dbg(4, "%s csrows map: (%d,%d)\n",
1193                                  mci->csbased ? "rank" : "dimm",
1194                                  dimm->csrow, dimm->cschannel);
1195                         if (row == -1)
1196                                 row = dimm->csrow;
1197                         else if (row >= 0 && row != dimm->csrow)
1198                                 row = -2;
1199
1200                         if (chan == -1)
1201                                 chan = dimm->cschannel;
1202                         else if (chan >= 0 && chan != dimm->cschannel)
1203                                 chan = -2;
1204                 }
1205         }
1206
1207         if (!e->enable_per_layer_report) {
1208                 strcpy(e->label, "any memory");
1209         } else {
1210                 edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan);
1211                 if (p == e->label)
1212                         strcpy(e->label, "unknown memory");
1213                 if (type == HW_EVENT_ERR_CORRECTED) {
1214                         if (row >= 0) {
1215                                 mci->csrows[row]->ce_count += error_count;
1216                                 if (chan >= 0)
1217                                         mci->csrows[row]->channels[chan]->ce_count += error_count;
1218                         }
1219                 } else
1220                         if (row >= 0)
1221                                 mci->csrows[row]->ue_count += error_count;
1222         }
1223
1224         /* Fill the RAM location data */
1225         p = e->location;
1226
1227         for (i = 0; i < mci->n_layers; i++) {
1228                 if (pos[i] < 0)
1229                         continue;
1230
1231                 p += sprintf(p, "%s:%d ",
1232                              edac_layer_name[mci->layers[i].type],
1233                              pos[i]);
1234         }
1235         if (p > e->location)
1236                 *(p - 1) = '\0';
1237
1238         /* Report the error via the trace interface */
1239         grain_bits = fls_long(e->grain) + 1;
1240
1241         if (IS_ENABLED(CONFIG_RAS))
1242                 trace_mc_event(type, e->msg, e->label, e->error_count,
1243                                mci->mc_idx, e->top_layer, e->mid_layer,
1244                                e->low_layer,
1245                                (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
1246                                grain_bits, e->syndrome, e->other_detail);
1247
1248         edac_raw_mc_handle_error(type, mci, e);
1249 }
1250 EXPORT_SYMBOL_GPL(edac_mc_handle_error);