1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 Pengutronix, Jan Luebbe <kernel@pengutronix.de>
6 #include <linux/kernel.h>
7 #include <linux/edac.h>
8 #include <linux/of_platform.h>
10 #include <asm/hardware/cache-l2x0.h>
11 #include <asm/hardware/cache-aurora-l2.h>
14 #include "edac_device.h"
15 #include "edac_module.h"
17 /************************ EDAC MC (DDR RAM) ********************************/
19 #define SDRAM_NUM_CS 4
21 #define SDRAM_CONFIG_REG 0x0
22 #define SDRAM_CONFIG_ECC_MASK BIT(18)
23 #define SDRAM_CONFIG_REGISTERED_MASK BIT(17)
24 #define SDRAM_CONFIG_BUS_WIDTH_MASK BIT(15)
26 #define SDRAM_ADDR_CTRL_REG 0x10
27 #define SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(cs) (20+cs)
28 #define SDRAM_ADDR_CTRL_SIZE_HIGH_MASK(cs) (0x1 << SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(cs))
29 #define SDRAM_ADDR_CTRL_ADDR_SEL_MASK(cs) BIT(16+cs)
30 #define SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(cs) (cs*4+2)
31 #define SDRAM_ADDR_CTRL_SIZE_LOW_MASK(cs) (0x3 << SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(cs))
32 #define SDRAM_ADDR_CTRL_STRUCT_OFFSET(cs) (cs*4)
33 #define SDRAM_ADDR_CTRL_STRUCT_MASK(cs) (0x3 << SDRAM_ADDR_CTRL_STRUCT_OFFSET(cs))
35 #define SDRAM_ERR_DATA_H_REG 0x40
36 #define SDRAM_ERR_DATA_L_REG 0x44
38 #define SDRAM_ERR_RECV_ECC_REG 0x48
39 #define SDRAM_ERR_RECV_ECC_VALUE_MASK 0xff
41 #define SDRAM_ERR_CALC_ECC_REG 0x4c
42 #define SDRAM_ERR_CALC_ECC_ROW_OFFSET 8
43 #define SDRAM_ERR_CALC_ECC_ROW_MASK (0xffff << SDRAM_ERR_CALC_ECC_ROW_OFFSET)
44 #define SDRAM_ERR_CALC_ECC_VALUE_MASK 0xff
46 #define SDRAM_ERR_ADDR_REG 0x50
47 #define SDRAM_ERR_ADDR_BANK_OFFSET 23
48 #define SDRAM_ERR_ADDR_BANK_MASK (0x7 << SDRAM_ERR_ADDR_BANK_OFFSET)
49 #define SDRAM_ERR_ADDR_COL_OFFSET 8
50 #define SDRAM_ERR_ADDR_COL_MASK (0x7fff << SDRAM_ERR_ADDR_COL_OFFSET)
51 #define SDRAM_ERR_ADDR_CS_OFFSET 1
52 #define SDRAM_ERR_ADDR_CS_MASK (0x3 << SDRAM_ERR_ADDR_CS_OFFSET)
53 #define SDRAM_ERR_ADDR_TYPE_MASK BIT(0)
55 #define SDRAM_ERR_CTRL_REG 0x54
56 #define SDRAM_ERR_CTRL_THR_OFFSET 16
57 #define SDRAM_ERR_CTRL_THR_MASK (0xff << SDRAM_ERR_CTRL_THR_OFFSET)
58 #define SDRAM_ERR_CTRL_PROP_MASK BIT(9)
60 #define SDRAM_ERR_SBE_COUNT_REG 0x58
61 #define SDRAM_ERR_DBE_COUNT_REG 0x5c
63 #define SDRAM_ERR_CAUSE_ERR_REG 0xd0
64 #define SDRAM_ERR_CAUSE_MSG_REG 0xd8
65 #define SDRAM_ERR_CAUSE_DBE_MASK BIT(1)
66 #define SDRAM_ERR_CAUSE_SBE_MASK BIT(0)
68 #define SDRAM_RANK_CTRL_REG 0x1e0
69 #define SDRAM_RANK_CTRL_EXIST_MASK(cs) BIT(cs)
71 struct axp_mc_drvdata {
75 /* bank interleaving */
76 bool cs_addr_sel[SDRAM_NUM_CS];
81 /* derived from "DRAM Address Multiplexing" in the ARAMDA XP Functional Spec */
82 static uint32_t axp_mc_calc_address(struct axp_mc_drvdata *drvdata,
83 uint8_t cs, uint8_t bank, uint16_t row,
86 if (drvdata->width == 8) {
88 if (drvdata->cs_addr_sel[cs])
89 /* bank interleaved */
90 return (((row & 0xfff8) << 16) |
91 ((bank & 0x7) << 16) |
93 ((col & 0x3ff) << 3));
95 return (((row & 0xffff << 16) |
96 ((bank & 0x7) << 13) |
97 ((col & 0x3ff)) << 3));
98 } else if (drvdata->width == 4) {
100 if (drvdata->cs_addr_sel[cs])
101 /* bank interleaved */
102 return (((row & 0xfff0) << 15) |
103 ((bank & 0x7) << 16) |
104 ((row & 0xf) << 12) |
105 ((col & 0x3ff) << 2));
107 return (((row & 0xffff << 15) |
108 ((bank & 0x7) << 12) |
109 ((col & 0x3ff)) << 2));
112 if (drvdata->cs_addr_sel[cs])
113 /* bank interleaved */
114 return (((row & 0xffe0) << 14) |
115 ((bank & 0x7) << 16) |
116 ((row & 0x1f) << 11) |
117 ((col & 0x3ff) << 1));
119 return (((row & 0xffff << 14) |
120 ((bank & 0x7) << 11) |
121 ((col & 0x3ff)) << 1));
125 static void axp_mc_check(struct mem_ctl_info *mci)
127 struct axp_mc_drvdata *drvdata = mci->pvt_info;
128 uint32_t data_h, data_l, recv_ecc, calc_ecc, addr;
129 uint32_t cnt_sbe, cnt_dbe, cause_err, cause_msg;
130 uint32_t row_val, col_val, bank_val, addr_val;
131 uint8_t syndrome_val, cs_val;
132 char *msg = drvdata->msg;
134 data_h = readl(drvdata->base + SDRAM_ERR_DATA_H_REG);
135 data_l = readl(drvdata->base + SDRAM_ERR_DATA_L_REG);
136 recv_ecc = readl(drvdata->base + SDRAM_ERR_RECV_ECC_REG);
137 calc_ecc = readl(drvdata->base + SDRAM_ERR_CALC_ECC_REG);
138 addr = readl(drvdata->base + SDRAM_ERR_ADDR_REG);
139 cnt_sbe = readl(drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
140 cnt_dbe = readl(drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
141 cause_err = readl(drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
142 cause_msg = readl(drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
144 /* clear cause registers */
145 writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK),
146 drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
147 writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK),
148 drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
150 /* clear error counter registers */
152 writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
154 writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
156 if (!cnt_sbe && !cnt_dbe)
159 if (!(addr & SDRAM_ERR_ADDR_TYPE_MASK)) {
163 dev_warn(mci->pdev, "inconsistent SBE count detected");
168 dev_warn(mci->pdev, "inconsistent DBE count detected");
171 /* report earlier errors */
173 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
174 cnt_sbe, /* error count */
175 0, 0, 0, /* pfn, offset, syndrome */
176 -1, -1, -1, /* top, mid, low layer */
178 "details unavailable (multiple errors)");
180 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
181 cnt_sbe, /* error count */
182 0, 0, 0, /* pfn, offset, syndrome */
183 -1, -1, -1, /* top, mid, low layer */
185 "details unavailable (multiple errors)");
187 /* report details for most recent error */
188 cs_val = (addr & SDRAM_ERR_ADDR_CS_MASK) >> SDRAM_ERR_ADDR_CS_OFFSET;
189 bank_val = (addr & SDRAM_ERR_ADDR_BANK_MASK) >> SDRAM_ERR_ADDR_BANK_OFFSET;
190 row_val = (calc_ecc & SDRAM_ERR_CALC_ECC_ROW_MASK) >> SDRAM_ERR_CALC_ECC_ROW_OFFSET;
191 col_val = (addr & SDRAM_ERR_ADDR_COL_MASK) >> SDRAM_ERR_ADDR_COL_OFFSET;
192 syndrome_val = (recv_ecc ^ calc_ecc) & 0xff;
193 addr_val = axp_mc_calc_address(drvdata, cs_val, bank_val, row_val,
195 msg += sprintf(msg, "row=0x%04x ", row_val); /* 11 chars */
196 msg += sprintf(msg, "bank=0x%x ", bank_val); /* 9 chars */
197 msg += sprintf(msg, "col=0x%04x ", col_val); /* 11 chars */
198 msg += sprintf(msg, "cs=%d", cs_val); /* 4 chars */
200 if (!(addr & SDRAM_ERR_ADDR_TYPE_MASK)) {
201 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
203 addr_val >> PAGE_SHIFT,
204 addr_val & ~PAGE_MASK,
206 cs_val, -1, -1, /* top, mid, low layer */
207 mci->ctl_name, drvdata->msg);
209 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
211 addr_val >> PAGE_SHIFT,
212 addr_val & ~PAGE_MASK,
214 cs_val, -1, -1, /* top, mid, low layer */
215 mci->ctl_name, drvdata->msg);
219 static void axp_mc_read_config(struct mem_ctl_info *mci)
221 struct axp_mc_drvdata *drvdata = mci->pvt_info;
222 uint32_t config, addr_ctrl, rank_ctrl;
223 unsigned int i, cs_struct, cs_size;
224 struct dimm_info *dimm;
226 config = readl(drvdata->base + SDRAM_CONFIG_REG);
227 if (config & SDRAM_CONFIG_BUS_WIDTH_MASK)
234 addr_ctrl = readl(drvdata->base + SDRAM_ADDR_CTRL_REG);
235 rank_ctrl = readl(drvdata->base + SDRAM_RANK_CTRL_REG);
236 for (i = 0; i < SDRAM_NUM_CS; i++) {
237 dimm = mci->dimms[i];
239 if (!(rank_ctrl & SDRAM_RANK_CTRL_EXIST_MASK(i)))
242 drvdata->cs_addr_sel[i] =
243 !!(addr_ctrl & SDRAM_ADDR_CTRL_ADDR_SEL_MASK(i));
245 cs_struct = (addr_ctrl & SDRAM_ADDR_CTRL_STRUCT_MASK(i)) >> SDRAM_ADDR_CTRL_STRUCT_OFFSET(i);
246 cs_size = ((addr_ctrl & SDRAM_ADDR_CTRL_SIZE_HIGH_MASK(i)) >> (SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(i) - 2) |
247 ((addr_ctrl & SDRAM_ADDR_CTRL_SIZE_LOW_MASK(i)) >> SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(i)));
251 dimm->nr_pages = 524288;
253 case 1: /* 256MBit */
254 dimm->nr_pages = 65536;
256 case 2: /* 512MBit */
257 dimm->nr_pages = 131072;
260 dimm->nr_pages = 262144;
263 dimm->nr_pages = 1048576;
266 dimm->nr_pages = 2097152;
270 dimm->dtype = cs_struct ? DEV_X16 : DEV_X8;
271 dimm->mtype = (config & SDRAM_CONFIG_REGISTERED_MASK) ?
272 MEM_RDDR3 : MEM_DDR3;
273 dimm->edac_mode = EDAC_SECDED;
277 static const struct of_device_id axp_mc_of_match[] = {
278 {.compatible = "marvell,armada-xp-sdram-controller",},
281 MODULE_DEVICE_TABLE(of, axp_mc_of_match);
283 static int axp_mc_probe(struct platform_device *pdev)
285 struct axp_mc_drvdata *drvdata;
286 struct edac_mc_layer layers[1];
287 const struct of_device_id *id;
288 struct mem_ctl_info *mci;
293 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
295 dev_err(&pdev->dev, "Unable to get mem resource\n");
299 base = devm_ioremap_resource(&pdev->dev, r);
301 dev_err(&pdev->dev, "Unable to map regs\n");
302 return PTR_ERR(base);
305 config = readl(base + SDRAM_CONFIG_REG);
306 if (!(config & SDRAM_CONFIG_ECC_MASK)) {
307 dev_warn(&pdev->dev, "SDRAM ECC is not enabled");
311 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
312 layers[0].size = SDRAM_NUM_CS;
313 layers[0].is_virt_csrow = true;
315 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*drvdata));
319 drvdata = mci->pvt_info;
320 drvdata->base = base;
321 mci->pdev = &pdev->dev;
322 platform_set_drvdata(pdev, mci);
324 id = of_match_device(axp_mc_of_match, &pdev->dev);
325 mci->edac_check = axp_mc_check;
326 mci->mtype_cap = MEM_FLAG_DDR3;
327 mci->edac_cap = EDAC_FLAG_SECDED;
328 mci->mod_name = pdev->dev.driver->name;
329 mci->ctl_name = id ? id->compatible : "unknown";
330 mci->dev_name = dev_name(&pdev->dev);
331 mci->scrub_mode = SCRUB_NONE;
333 axp_mc_read_config(mci);
335 /* configure SBE threshold */
336 /* it seems that SBEs are not captured otherwise */
337 writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);
339 /* clear cause registers */
340 writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
341 writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
343 /* clear counter registers */
344 writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
345 writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
347 if (edac_mc_add_mc(mci)) {
351 edac_op_state = EDAC_OPSTATE_POLL;
356 static int axp_mc_remove(struct platform_device *pdev)
358 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
360 edac_mc_del_mc(&pdev->dev);
362 platform_set_drvdata(pdev, NULL);
367 static struct platform_driver axp_mc_driver = {
368 .probe = axp_mc_probe,
369 .remove = axp_mc_remove,
371 .name = "armada_xp_mc_edac",
372 .of_match_table = of_match_ptr(axp_mc_of_match),
376 /************************ EDAC Device (L2 Cache) ***************************/
378 struct aurora_l2_drvdata {
383 /* error injection via debugfs */
384 uint32_t inject_addr;
385 uint32_t inject_mask;
388 struct dentry *debugfs;
391 #ifdef CONFIG_EDAC_DEBUG
392 static void aurora_l2_inject(struct aurora_l2_drvdata *drvdata)
394 drvdata->inject_addr &= AURORA_ERR_INJECT_CTL_ADDR_MASK;
395 drvdata->inject_ctl &= AURORA_ERR_INJECT_CTL_EN_MASK;
396 writel(0, drvdata->base + AURORA_ERR_INJECT_CTL_REG);
397 writel(drvdata->inject_mask, drvdata->base + AURORA_ERR_INJECT_MASK_REG);
398 writel(drvdata->inject_addr | drvdata->inject_ctl, drvdata->base + AURORA_ERR_INJECT_CTL_REG);
402 static void aurora_l2_check(struct edac_device_ctl_info *dci)
404 struct aurora_l2_drvdata *drvdata = dci->pvt_info;
405 uint32_t cnt, src, txn, err, attr_cap, addr_cap, way_cap;
406 unsigned int cnt_ce, cnt_ue;
407 char *msg = drvdata->msg;
408 size_t size = sizeof(drvdata->msg);
411 cnt = readl(drvdata->base + AURORA_ERR_CNT_REG);
412 attr_cap = readl(drvdata->base + AURORA_ERR_ATTR_CAP_REG);
413 addr_cap = readl(drvdata->base + AURORA_ERR_ADDR_CAP_REG);
414 way_cap = readl(drvdata->base + AURORA_ERR_WAY_CAP_REG);
416 cnt_ce = (cnt & AURORA_ERR_CNT_CE_MASK) >> AURORA_ERR_CNT_CE_OFFSET;
417 cnt_ue = (cnt & AURORA_ERR_CNT_UE_MASK) >> AURORA_ERR_CNT_UE_OFFSET;
418 /* clear error counter registers */
419 if (cnt_ce || cnt_ue)
420 writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG);
422 if (!(attr_cap & AURORA_ERR_ATTR_CAP_VALID))
423 goto clear_remaining;
425 src = (attr_cap & AURORA_ERR_ATTR_SRC_MSK) >> AURORA_ERR_ATTR_SRC_OFF;
427 len += snprintf(msg+len, size-len, "src=CPU%d ", src);
429 len += snprintf(msg+len, size-len, "src=IO ");
431 txn = (attr_cap & AURORA_ERR_ATTR_TXN_MSK) >> AURORA_ERR_ATTR_TXN_OFF;
434 len += snprintf(msg+len, size-len, "txn=Data-Read ");
437 len += snprintf(msg+len, size-len, "txn=Isn-Read ");
440 len += snprintf(msg+len, size-len, "txn=Clean-Flush ");
443 len += snprintf(msg+len, size-len, "txn=Eviction ");
446 len += snprintf(msg+len, size-len,
447 "txn=Read-Modify-Write ");
451 err = (attr_cap & AURORA_ERR_ATTR_ERR_MSK) >> AURORA_ERR_ATTR_ERR_OFF;
454 len += snprintf(msg+len, size-len, "err=CorrECC ");
457 len += snprintf(msg+len, size-len, "err=UnCorrECC ");
460 len += snprintf(msg+len, size-len, "err=TagParity ");
464 len += snprintf(msg+len, size-len, "addr=0x%x ", addr_cap & AURORA_ERR_ADDR_CAP_ADDR_MASK);
465 len += snprintf(msg+len, size-len, "index=0x%x ", (way_cap & AURORA_ERR_WAY_IDX_MSK) >> AURORA_ERR_WAY_IDX_OFF);
466 len += snprintf(msg+len, size-len, "way=0x%x", (way_cap & AURORA_ERR_WAY_CAP_WAY_MASK) >> AURORA_ERR_WAY_CAP_WAY_OFFSET);
468 /* clear error capture registers */
469 writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG);
471 /* UnCorrECC or TagParity */
474 edac_device_handle_ue(dci, 0, 0, drvdata->msg);
478 edac_device_handle_ce(dci, 0, 0, drvdata->msg);
482 /* report remaining errors */
484 edac_device_handle_ue(dci, 0, 0, "details unavailable (multiple errors)");
486 edac_device_handle_ue(dci, 0, 0, "details unavailable (multiple errors)");
489 static void aurora_l2_poll(struct edac_device_ctl_info *dci)
491 #ifdef CONFIG_EDAC_DEBUG
492 struct aurora_l2_drvdata *drvdata = dci->pvt_info;
495 aurora_l2_check(dci);
496 #ifdef CONFIG_EDAC_DEBUG
497 aurora_l2_inject(drvdata);
501 static const struct of_device_id aurora_l2_of_match[] = {
502 {.compatible = "marvell,aurora-system-cache",},
505 MODULE_DEVICE_TABLE(of, aurora_l2_of_match);
507 static int aurora_l2_probe(struct platform_device *pdev)
509 struct aurora_l2_drvdata *drvdata;
510 struct edac_device_ctl_info *dci;
511 const struct of_device_id *id;
512 uint32_t l2x0_aux_ctrl;
516 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
518 dev_err(&pdev->dev, "Unable to get mem resource\n");
522 base = devm_ioremap_resource(&pdev->dev, r);
524 dev_err(&pdev->dev, "Unable to map regs\n");
525 return PTR_ERR(base);
528 l2x0_aux_ctrl = readl(base + L2X0_AUX_CTRL);
529 if (!(l2x0_aux_ctrl & AURORA_ACR_PARITY_EN))
530 dev_warn(&pdev->dev, "tag parity is not enabled");
531 if (!(l2x0_aux_ctrl & AURORA_ACR_ECC_EN))
532 dev_warn(&pdev->dev, "data ECC is not enabled");
534 dci = edac_device_alloc_ctl_info(sizeof(*drvdata),
535 "cpu", 1, "L", 1, 2, NULL, 0, 0);
539 drvdata = dci->pvt_info;
540 drvdata->base = base;
541 dci->dev = &pdev->dev;
542 platform_set_drvdata(pdev, dci);
544 id = of_match_device(aurora_l2_of_match, &pdev->dev);
545 dci->edac_check = aurora_l2_poll;
546 dci->mod_name = pdev->dev.driver->name;
547 dci->ctl_name = id ? id->compatible : "unknown";
548 dci->dev_name = dev_name(&pdev->dev);
550 /* clear registers */
551 writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG);
552 writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG);
554 if (edac_device_add_device(dci)) {
555 edac_device_free_ctl_info(dci);
559 #ifdef CONFIG_EDAC_DEBUG
560 drvdata->debugfs = edac_debugfs_create_dir(dev_name(&pdev->dev));
561 if (drvdata->debugfs) {
562 edac_debugfs_create_x32("inject_addr", 0644,
564 &drvdata->inject_addr);
565 edac_debugfs_create_x32("inject_mask", 0644,
567 &drvdata->inject_mask);
568 edac_debugfs_create_x8("inject_ctl", 0644,
569 drvdata->debugfs, &drvdata->inject_ctl);
576 static int aurora_l2_remove(struct platform_device *pdev)
578 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
579 #ifdef CONFIG_EDAC_DEBUG
580 struct aurora_l2_drvdata *drvdata = dci->pvt_info;
582 edac_debugfs_remove_recursive(drvdata->debugfs);
584 edac_device_del_device(&pdev->dev);
585 edac_device_free_ctl_info(dci);
586 platform_set_drvdata(pdev, NULL);
591 static struct platform_driver aurora_l2_driver = {
592 .probe = aurora_l2_probe,
593 .remove = aurora_l2_remove,
595 .name = "aurora_l2_edac",
596 .of_match_table = of_match_ptr(aurora_l2_of_match),
600 /************************ Driver registration ******************************/
602 static struct platform_driver * const drivers[] = {
607 static int __init armada_xp_edac_init(void)
611 /* only polling is supported */
612 edac_op_state = EDAC_OPSTATE_POLL;
614 res = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
616 pr_warn("Aramda XP EDAC drivers fail to register\n");
620 module_init(armada_xp_edac_init);
622 static void __exit armada_xp_edac_exit(void)
624 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
626 module_exit(armada_xp_edac_exit);
628 MODULE_LICENSE("GPL v2");
629 MODULE_AUTHOR("Pengutronix");
630 MODULE_DESCRIPTION("EDAC Drivers for Marvell Armada XP SDRAM and L2 Cache Controller");