1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
8 #include <asm/cacheflush.h>
9 #include <linux/ctype.h>
10 #include <linux/delay.h>
11 #include <linux/edac.h>
12 #include <linux/firmware/intel/stratix10-smc.h>
13 #include <linux/genalloc.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/altera-sysmgr.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/notifier.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/panic_notifier.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/types.h>
27 #include <linux/uaccess.h>
29 #include "altera_edac.h"
30 #include "edac_module.h"
32 #define EDAC_MOD_STR "altera_edac"
33 #define EDAC_DEVICE "Altera"
35 #ifdef CONFIG_EDAC_ALTERA_SDRAM
36 static const struct altr_sdram_prv_data c5_data = {
37 .ecc_ctrl_offset = CV_CTLCFG_OFST,
38 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
39 .ecc_stat_offset = CV_DRAMSTS_OFST,
40 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
41 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
42 .ecc_saddr_offset = CV_ERRADDR_OFST,
43 .ecc_daddr_offset = CV_ERRADDR_OFST,
44 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
45 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
46 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
47 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
48 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
49 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
50 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
51 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
52 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
53 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
54 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
57 static const struct altr_sdram_prv_data a10_data = {
58 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
59 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
60 .ecc_stat_offset = A10_INTSTAT_OFST,
61 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
62 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
63 .ecc_saddr_offset = A10_SERRADDR_OFST,
64 .ecc_daddr_offset = A10_DERRADDR_OFST,
65 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
66 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
67 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
68 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
69 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
70 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
71 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
72 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
73 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
76 /*********************** EDAC Memory Controller Functions ****************/
78 /* The SDRAM controller uses the EDAC Memory Controller framework. */
80 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
82 struct mem_ctl_info *mci = dev_id;
83 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
84 const struct altr_sdram_prv_data *priv = drvdata->data;
85 u32 status, err_count = 1, err_addr;
87 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
89 if (status & priv->ecc_stat_ue_mask) {
90 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
92 if (priv->ecc_uecnt_offset)
93 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
95 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
98 if (status & priv->ecc_stat_ce_mask) {
99 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
101 if (priv->ecc_uecnt_offset)
102 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
104 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
105 err_addr >> PAGE_SHIFT,
106 err_addr & ~PAGE_MASK, 0,
107 0, 0, -1, mci->ctl_name, "");
108 /* Clear IRQ to resume */
109 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
110 priv->ecc_irq_clr_mask);
117 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
118 const char __user *data,
119 size_t count, loff_t *ppos)
121 struct mem_ctl_info *mci = file->private_data;
122 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
123 const struct altr_sdram_prv_data *priv = drvdata->data;
125 dma_addr_t dma_handle;
128 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
130 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
131 edac_printk(KERN_ERR, EDAC_MC,
132 "Inject: Buffer Allocation error\n");
136 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
138 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
140 /* Error are injected by writing a word while the SBE or DBE
141 * bit in the CTLCFG register is set. Reading the word will
142 * trigger the SBE or DBE error and the corresponding IRQ.
145 edac_printk(KERN_ALERT, EDAC_MC,
146 "Inject Double bit error\n");
148 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
149 (read_reg | priv->ue_set_mask));
152 edac_printk(KERN_ALERT, EDAC_MC,
153 "Inject Single bit error\n");
155 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
156 (read_reg | priv->ce_set_mask));
160 ptemp[0] = 0x5A5A5A5A;
161 ptemp[1] = 0xA5A5A5A5;
163 /* Clear the error injection bits */
164 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
165 /* Ensure it has been written out */
169 * To trigger the error, we need to read the data back
170 * (the data was written with errors above).
171 * The READ_ONCE macros and printk are used to prevent the
172 * the compiler optimizing these reads out.
174 reg = READ_ONCE(ptemp[0]);
175 read_reg = READ_ONCE(ptemp[1]);
179 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
182 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
187 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
189 .write = altr_sdr_mc_err_inject_write,
190 .llseek = generic_file_llseek,
193 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
195 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
201 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
202 &altr_sdr_mc_debug_inject_fops);
205 /* Get total memory size from Open Firmware DTB */
206 static unsigned long get_total_mem(void)
208 struct device_node *np = NULL;
211 unsigned long total_mem = 0;
213 for_each_node_by_type(np, "memory") {
214 ret = of_address_to_resource(np, 0, &res);
218 total_mem += resource_size(&res);
220 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
224 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
225 { .compatible = "altr,sdram-edac", .data = &c5_data},
226 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
229 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
231 static int a10_init(struct regmap *mc_vbase)
233 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
234 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
235 edac_printk(KERN_ERR, EDAC_MC,
236 "Error setting SB IRQ mode\n");
240 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
241 edac_printk(KERN_ERR, EDAC_MC,
242 "Error setting trigger count\n");
249 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
251 void __iomem *sm_base;
254 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
255 dev_name(&pdev->dev))) {
256 edac_printk(KERN_ERR, EDAC_MC,
257 "Unable to request mem region\n");
261 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
263 edac_printk(KERN_ERR, EDAC_MC,
264 "Unable to ioremap device\n");
270 iowrite32(mask, sm_base);
275 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
280 static int altr_sdram_probe(struct platform_device *pdev)
282 const struct of_device_id *id;
283 struct edac_mc_layer layers[2];
284 struct mem_ctl_info *mci;
285 struct altr_sdram_mc_data *drvdata;
286 const struct altr_sdram_prv_data *priv;
287 struct regmap *mc_vbase;
288 struct dimm_info *dimm;
290 int irq, irq2, res = 0;
291 unsigned long mem_size, irqflags = 0;
293 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
297 /* Grab the register range from the sdr controller in device tree */
298 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
300 if (IS_ERR(mc_vbase)) {
301 edac_printk(KERN_ERR, EDAC_MC,
302 "regmap for altr,sdr-syscon lookup failed.\n");
306 /* Check specific dependencies for the module */
307 priv = of_match_node(altr_sdram_ctrl_of_match,
308 pdev->dev.of_node)->data;
310 /* Validate the SDRAM controller has ECC enabled */
311 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
312 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
313 edac_printk(KERN_ERR, EDAC_MC,
314 "No ECC/ECC disabled [0x%08X]\n", read_reg);
318 /* Grab memory size from device tree. */
319 mem_size = get_total_mem();
321 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
325 /* Ensure the SDRAM Interrupt is disabled */
326 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
327 priv->ecc_irq_en_mask, 0)) {
328 edac_printk(KERN_ERR, EDAC_MC,
329 "Error disabling SDRAM ECC IRQ\n");
333 /* Toggle to clear the SDRAM Error count */
334 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
335 priv->ecc_cnt_rst_mask,
336 priv->ecc_cnt_rst_mask)) {
337 edac_printk(KERN_ERR, EDAC_MC,
338 "Error clearing SDRAM ECC count\n");
342 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
343 priv->ecc_cnt_rst_mask, 0)) {
344 edac_printk(KERN_ERR, EDAC_MC,
345 "Error clearing SDRAM ECC count\n");
349 irq = platform_get_irq(pdev, 0);
351 edac_printk(KERN_ERR, EDAC_MC,
352 "No irq %d in DT\n", irq);
356 /* Arria10 has a 2nd IRQ */
357 irq2 = platform_get_irq(pdev, 1);
359 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
361 layers[0].is_virt_csrow = true;
362 layers[1].type = EDAC_MC_LAYER_CHANNEL;
364 layers[1].is_virt_csrow = false;
365 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
366 sizeof(struct altr_sdram_mc_data));
370 mci->pdev = &pdev->dev;
371 drvdata = mci->pvt_info;
372 drvdata->mc_vbase = mc_vbase;
373 drvdata->data = priv;
374 platform_set_drvdata(pdev, mci);
376 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
377 edac_printk(KERN_ERR, EDAC_MC,
378 "Unable to get managed device resource\n");
383 mci->mtype_cap = MEM_FLAG_DDR3;
384 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
385 mci->edac_cap = EDAC_FLAG_SECDED;
386 mci->mod_name = EDAC_MOD_STR;
387 mci->ctl_name = dev_name(&pdev->dev);
388 mci->scrub_mode = SCRUB_SW_SRC;
389 mci->dev_name = dev_name(&pdev->dev);
392 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
394 dimm->dtype = DEV_X8;
395 dimm->mtype = MEM_DDR3;
396 dimm->edac_mode = EDAC_SECDED;
398 res = edac_mc_add_mc(mci);
402 /* Only the Arria10 has separate IRQs */
403 if (of_machine_is_compatible("altr,socfpga-arria10")) {
404 /* Arria10 specific initialization */
405 res = a10_init(mc_vbase);
409 res = devm_request_irq(&pdev->dev, irq2,
410 altr_sdram_mc_err_handler,
411 IRQF_SHARED, dev_name(&pdev->dev), mci);
413 edac_mc_printk(mci, KERN_ERR,
414 "Unable to request irq %d\n", irq2);
419 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
423 irqflags = IRQF_SHARED;
426 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
427 irqflags, dev_name(&pdev->dev), mci);
429 edac_mc_printk(mci, KERN_ERR,
430 "Unable to request irq %d\n", irq);
435 /* Infrastructure ready - enable the IRQ */
436 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
437 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
438 edac_mc_printk(mci, KERN_ERR,
439 "Error enabling SDRAM ECC IRQ\n");
444 altr_sdr_mc_create_debugfs_nodes(mci);
446 devres_close_group(&pdev->dev, NULL);
451 edac_mc_del_mc(&pdev->dev);
453 devres_release_group(&pdev->dev, NULL);
456 edac_printk(KERN_ERR, EDAC_MC,
457 "EDAC Probe Failed; Error %d\n", res);
462 static int altr_sdram_remove(struct platform_device *pdev)
464 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
466 edac_mc_del_mc(&pdev->dev);
468 platform_set_drvdata(pdev, NULL);
474 * If you want to suspend, need to disable EDAC by removing it
475 * from the device tree or defconfig.
478 static int altr_sdram_prepare(struct device *dev)
480 pr_err("Suspend not allowed when EDAC is enabled.\n");
485 static const struct dev_pm_ops altr_sdram_pm_ops = {
486 .prepare = altr_sdram_prepare,
490 static struct platform_driver altr_sdram_edac_driver = {
491 .probe = altr_sdram_probe,
492 .remove = altr_sdram_remove,
494 .name = "altr_sdram_edac",
496 .pm = &altr_sdram_pm_ops,
498 .of_match_table = altr_sdram_ctrl_of_match,
502 module_platform_driver(altr_sdram_edac_driver);
504 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
506 /************************* EDAC Parent Probe *************************/
508 static const struct of_device_id altr_edac_device_of_match[];
510 static const struct of_device_id altr_edac_of_match[] = {
511 { .compatible = "altr,socfpga-ecc-manager" },
514 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
516 static int altr_edac_probe(struct platform_device *pdev)
518 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
523 static struct platform_driver altr_edac_driver = {
524 .probe = altr_edac_probe,
526 .name = "socfpga_ecc_manager",
527 .of_match_table = altr_edac_of_match,
530 module_platform_driver(altr_edac_driver);
532 /************************* EDAC Device Functions *************************/
535 * EDAC Device Functions (shared between various IPs).
536 * The discrete memories use the EDAC Device framework. The probe
537 * and error handling functions are very similar between memories
538 * so they are shared. The memory allocation and freeing for EDAC
539 * trigger testing are different for each memory.
542 static const struct edac_device_prv_data ocramecc_data;
543 static const struct edac_device_prv_data l2ecc_data;
544 static const struct edac_device_prv_data a10_ocramecc_data;
545 static const struct edac_device_prv_data a10_l2ecc_data;
547 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
549 irqreturn_t ret_value = IRQ_NONE;
550 struct edac_device_ctl_info *dci = dev_id;
551 struct altr_edac_device_dev *drvdata = dci->pvt_info;
552 const struct edac_device_prv_data *priv = drvdata->data;
554 if (irq == drvdata->sb_irq) {
555 if (priv->ce_clear_mask)
556 writel(priv->ce_clear_mask, drvdata->base);
557 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
558 ret_value = IRQ_HANDLED;
559 } else if (irq == drvdata->db_irq) {
560 if (priv->ue_clear_mask)
561 writel(priv->ue_clear_mask, drvdata->base);
562 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
563 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
564 ret_value = IRQ_HANDLED;
572 static ssize_t altr_edac_device_trig(struct file *file,
573 const char __user *user_buf,
574 size_t count, loff_t *ppos)
577 u32 *ptemp, i, error_mask;
581 struct edac_device_ctl_info *edac_dci = file->private_data;
582 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
583 const struct edac_device_prv_data *priv = drvdata->data;
584 void *generic_ptr = edac_dci->dev;
586 if (!user_buf || get_user(trig_type, user_buf))
589 if (!priv->alloc_mem)
593 * Note that generic_ptr is initialized to the device * but in
594 * some alloc_functions, this is overridden and returns data.
596 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
598 edac_printk(KERN_ERR, EDAC_DEVICE,
599 "Inject: Buffer Allocation error\n");
603 if (trig_type == ALTR_UE_TRIGGER_CHAR)
604 error_mask = priv->ue_set_mask;
606 error_mask = priv->ce_set_mask;
608 edac_printk(KERN_ALERT, EDAC_DEVICE,
609 "Trigger Error Mask (0x%X)\n", error_mask);
611 local_irq_save(flags);
612 /* write ECC corrupted data out. */
613 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
614 /* Read data so we're in the correct state */
616 if (READ_ONCE(ptemp[i]))
618 /* Toggle Error bit (it is latched), leave ECC enabled */
619 writel(error_mask, (drvdata->base + priv->set_err_ofst));
620 writel(priv->ecc_enable_mask, (drvdata->base +
621 priv->set_err_ofst));
624 /* Ensure it has been written out */
626 local_irq_restore(flags);
629 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
631 /* Read out written data. ECC error caused here */
632 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
633 if (READ_ONCE(ptemp[i]) != i)
634 edac_printk(KERN_ERR, EDAC_DEVICE,
635 "Read doesn't match written data\n");
638 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
643 static const struct file_operations altr_edac_device_inject_fops = {
645 .write = altr_edac_device_trig,
646 .llseek = generic_file_llseek,
649 static ssize_t altr_edac_a10_device_trig(struct file *file,
650 const char __user *user_buf,
651 size_t count, loff_t *ppos);
653 static const struct file_operations altr_edac_a10_device_inject_fops = {
655 .write = altr_edac_a10_device_trig,
656 .llseek = generic_file_llseek,
659 static ssize_t altr_edac_a10_device_trig2(struct file *file,
660 const char __user *user_buf,
661 size_t count, loff_t *ppos);
663 static const struct file_operations altr_edac_a10_device_inject2_fops = {
665 .write = altr_edac_a10_device_trig2,
666 .llseek = generic_file_llseek,
669 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
670 const struct edac_device_prv_data *priv)
672 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
674 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
677 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
678 if (!drvdata->debugfs_dir)
681 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
682 drvdata->debugfs_dir, edac_dci,
684 debugfs_remove_recursive(drvdata->debugfs_dir);
687 static const struct of_device_id altr_edac_device_of_match[] = {
688 #ifdef CONFIG_EDAC_ALTERA_L2C
689 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
691 #ifdef CONFIG_EDAC_ALTERA_OCRAM
692 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
696 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
699 * altr_edac_device_probe()
700 * This is a generic EDAC device driver that will support
701 * various Altera memory devices such as the L2 cache ECC and
702 * OCRAM ECC as well as the memories for other peripherals.
703 * Module specific initialization is done by passing the
704 * function index in the device tree.
706 static int altr_edac_device_probe(struct platform_device *pdev)
708 struct edac_device_ctl_info *dci;
709 struct altr_edac_device_dev *drvdata;
712 struct device_node *np = pdev->dev.of_node;
713 char *ecc_name = (char *)np->name;
714 static int dev_instance;
716 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
717 edac_printk(KERN_ERR, EDAC_DEVICE,
718 "Unable to open devm\n");
722 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
724 edac_printk(KERN_ERR, EDAC_DEVICE,
725 "Unable to get mem resource\n");
730 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
731 dev_name(&pdev->dev))) {
732 edac_printk(KERN_ERR, EDAC_DEVICE,
733 "%s:Error requesting mem region\n", ecc_name);
738 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
739 1, ecc_name, 1, 0, NULL, 0,
743 edac_printk(KERN_ERR, EDAC_DEVICE,
744 "%s: Unable to allocate EDAC device\n", ecc_name);
749 drvdata = dci->pvt_info;
750 dci->dev = &pdev->dev;
751 platform_set_drvdata(pdev, dci);
752 drvdata->edac_dev_name = ecc_name;
754 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
755 if (!drvdata->base) {
760 /* Get driver specific data for this EDAC device */
761 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
763 /* Check specific dependencies for the module */
764 if (drvdata->data->setup) {
765 res = drvdata->data->setup(drvdata);
770 drvdata->sb_irq = platform_get_irq(pdev, 0);
771 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
772 altr_edac_device_handler,
773 0, dev_name(&pdev->dev), dci);
777 drvdata->db_irq = platform_get_irq(pdev, 1);
778 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
779 altr_edac_device_handler,
780 0, dev_name(&pdev->dev), dci);
784 dci->mod_name = "Altera ECC Manager";
785 dci->dev_name = drvdata->edac_dev_name;
787 res = edac_device_add_device(dci);
791 altr_create_edacdev_dbgfs(dci, drvdata->data);
793 devres_close_group(&pdev->dev, NULL);
798 edac_device_free_ctl_info(dci);
800 devres_release_group(&pdev->dev, NULL);
801 edac_printk(KERN_ERR, EDAC_DEVICE,
802 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
807 static int altr_edac_device_remove(struct platform_device *pdev)
809 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
810 struct altr_edac_device_dev *drvdata = dci->pvt_info;
812 debugfs_remove_recursive(drvdata->debugfs_dir);
813 edac_device_del_device(&pdev->dev);
814 edac_device_free_ctl_info(dci);
819 static struct platform_driver altr_edac_device_driver = {
820 .probe = altr_edac_device_probe,
821 .remove = altr_edac_device_remove,
823 .name = "altr_edac_device",
824 .of_match_table = altr_edac_device_of_match,
827 module_platform_driver(altr_edac_device_driver);
829 /******************* Arria10 Device ECC Shared Functions *****************/
832 * Test for memory's ECC dependencies upon entry because platform specific
833 * startup should have initialized the memory and enabled the ECC.
834 * Can't turn on ECC here because accessing un-initialized memory will
835 * cause CE/UE errors possibly causing an ABORT.
837 static int __maybe_unused
838 altr_check_ecc_deps(struct altr_edac_device_dev *device)
840 void __iomem *base = device->base;
841 const struct edac_device_prv_data *prv = device->data;
843 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
846 edac_printk(KERN_ERR, EDAC_DEVICE,
847 "%s: No ECC present or ECC disabled.\n",
848 device->edac_dev_name);
852 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
854 struct altr_edac_device_dev *dci = dev_id;
855 void __iomem *base = dci->base;
857 if (irq == dci->sb_irq) {
858 writel(ALTR_A10_ECC_SERRPENA,
859 base + ALTR_A10_ECC_INTSTAT_OFST);
860 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
863 } else if (irq == dci->db_irq) {
864 writel(ALTR_A10_ECC_DERRPENA,
865 base + ALTR_A10_ECC_INTSTAT_OFST);
866 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
867 if (dci->data->panic)
868 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
878 /******************* Arria10 Memory Buffer Functions *********************/
880 static inline int a10_get_irq_mask(struct device_node *np)
883 const u32 *handle = of_get_property(np, "interrupts", NULL);
887 irq = be32_to_cpup(handle);
891 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
893 u32 value = readl(ioaddr);
896 writel(value, ioaddr);
899 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
901 u32 value = readl(ioaddr);
904 writel(value, ioaddr);
907 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
909 u32 value = readl(ioaddr);
911 return (value & bit_mask) ? 1 : 0;
915 * This function uses the memory initialization block in the Arria10 ECC
916 * controller to initialize/clear the entire memory data and ECC data.
918 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
920 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
921 u32 init_mask, stat_mask, clear_mask;
925 init_mask = ALTR_A10_ECC_INITB;
926 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
927 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
929 init_mask = ALTR_A10_ECC_INITA;
930 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
931 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
934 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
936 if (ecc_test_bits(stat_mask,
937 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
944 /* Clear any pending ECC interrupts */
945 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
950 static __init int __maybe_unused
951 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
952 u32 ecc_ctrl_en_mask, bool dual_port)
955 void __iomem *ecc_block_base;
956 struct regmap *ecc_mgr_map;
958 struct device_node *np_eccmgr;
960 ecc_name = (char *)np->name;
962 /* Get the ECC Manager - parent of the device EDACs */
963 np_eccmgr = of_get_parent(np);
966 altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr,
967 "altr,sysmgr-syscon");
969 of_node_put(np_eccmgr);
970 if (IS_ERR(ecc_mgr_map)) {
971 edac_printk(KERN_ERR, EDAC_DEVICE,
972 "Unable to get syscon altr,sysmgr-syscon\n");
976 /* Map the ECC Block */
977 ecc_block_base = of_iomap(np, 0);
978 if (!ecc_block_base) {
979 edac_printk(KERN_ERR, EDAC_DEVICE,
980 "Unable to map %s ECC block\n", ecc_name);
985 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
986 writel(ALTR_A10_ECC_SERRINTEN,
987 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
988 ecc_clear_bits(ecc_ctrl_en_mask,
989 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
990 /* Ensure all writes complete */
992 /* Use HW initialization block to initialize memory for ECC */
993 ret = altr_init_memory_port(ecc_block_base, 0);
995 edac_printk(KERN_ERR, EDAC_DEVICE,
996 "ECC: cannot init %s PORTA memory\n", ecc_name);
1001 ret = altr_init_memory_port(ecc_block_base, 1);
1003 edac_printk(KERN_ERR, EDAC_DEVICE,
1004 "ECC: cannot init %s PORTB memory\n",
1010 /* Interrupt mode set to every SBERR */
1011 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1012 ALTR_A10_ECC_INTMODE);
1014 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1015 ALTR_A10_ECC_CTRL_OFST));
1016 writel(ALTR_A10_ECC_SERRINTEN,
1017 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1018 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1019 /* Ensure all writes complete */
1022 iounmap(ecc_block_base);
1026 static int validate_parent_available(struct device_node *np);
1027 static const struct of_device_id altr_edac_a10_device_of_match[];
1028 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1031 struct device_node *child, *np;
1033 np = of_find_compatible_node(NULL, NULL,
1034 "altr,socfpga-a10-ecc-manager");
1036 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1040 for_each_child_of_node(np, child) {
1041 const struct of_device_id *pdev_id;
1042 const struct edac_device_prv_data *prv;
1044 if (!of_device_is_available(child))
1046 if (!of_device_is_compatible(child, compat))
1049 if (validate_parent_available(child))
1052 irq = a10_get_irq_mask(child);
1056 /* Get matching node and check for valid result */
1057 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1058 if (IS_ERR_OR_NULL(pdev_id))
1061 /* Validate private data pointer before dereferencing */
1062 prv = pdev_id->data;
1066 altr_init_a10_ecc_block(child, BIT(irq),
1067 prv->ecc_enable_mask, 0);
1074 /*********************** SDRAM EDAC Device Functions *********************/
1076 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1078 static const struct edac_device_prv_data s10_sdramecc_data = {
1079 .setup = altr_check_ecc_deps,
1080 .ce_clear_mask = ALTR_S10_ECC_SERRPENA,
1081 .ue_clear_mask = ALTR_S10_ECC_DERRPENA,
1082 .ecc_enable_mask = ALTR_S10_ECC_EN,
1083 .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
1084 .ce_set_mask = ALTR_S10_ECC_TSERRA,
1085 .ue_set_mask = ALTR_S10_ECC_TDERRA,
1086 .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
1087 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1088 .inject_fops = &altr_edac_a10_device_inject_fops,
1090 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
1092 /*********************** OCRAM EDAC Device Functions *********************/
1094 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1096 static void *ocram_alloc_mem(size_t size, void **other)
1098 struct device_node *np;
1099 struct gen_pool *gp;
1102 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1106 gp = of_gen_pool_get(np, "iram", 0);
1111 sram_addr = (void *)gen_pool_alloc(gp, size);
1115 memset(sram_addr, 0, size);
1116 /* Ensure data is written out */
1119 /* Remember this handle for freeing later */
1125 static void ocram_free_mem(void *p, size_t size, void *other)
1127 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1130 static const struct edac_device_prv_data ocramecc_data = {
1131 .setup = altr_check_ecc_deps,
1132 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1133 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1134 .alloc_mem = ocram_alloc_mem,
1135 .free_mem = ocram_free_mem,
1136 .ecc_enable_mask = ALTR_OCR_ECC_EN,
1137 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1138 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1139 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1140 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1141 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1142 .inject_fops = &altr_edac_device_inject_fops,
1145 static int __maybe_unused
1146 altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
1148 void __iomem *base = device->base;
1151 ret = altr_check_ecc_deps(device);
1155 /* Verify OCRAM has been initialized */
1156 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
1157 (base + ALTR_A10_ECC_INITSTAT_OFST)))
1160 /* Enable IRQ on Single Bit Error */
1161 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
1162 /* Ensure all writes complete */
1168 static const struct edac_device_prv_data a10_ocramecc_data = {
1169 .setup = altr_check_ocram_deps_init,
1170 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1171 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1172 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1173 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1174 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1175 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1176 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1177 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1178 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1179 .inject_fops = &altr_edac_a10_device_inject2_fops,
1181 * OCRAM panic on uncorrectable error because sleep/resume
1182 * functions and FPGA contents are stored in OCRAM. Prefer
1183 * a kernel panic over executing/loading corrupted data.
1188 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1190 /********************* L2 Cache EDAC Device Functions ********************/
1192 #ifdef CONFIG_EDAC_ALTERA_L2C
1194 static void *l2_alloc_mem(size_t size, void **other)
1196 struct device *dev = *other;
1197 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1202 /* Make sure everything is written out */
1206 * Clean all cache levels up to LoC (includes L2)
1207 * This ensures the corrupted data is written into
1208 * L2 cache for readback test (which causes ECC error).
1215 static void l2_free_mem(void *p, size_t size, void *other)
1217 struct device *dev = other;
1224 * altr_l2_check_deps()
1225 * Test for L2 cache ECC dependencies upon entry because
1226 * platform specific startup should have initialized the L2
1227 * memory and enabled the ECC.
1228 * Bail if ECC is not enabled.
1229 * Note that L2 Cache Enable is forced at build time.
1231 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1233 void __iomem *base = device->base;
1234 const struct edac_device_prv_data *prv = device->data;
1236 if ((readl(base) & prv->ecc_enable_mask) ==
1237 prv->ecc_enable_mask)
1240 edac_printk(KERN_ERR, EDAC_DEVICE,
1241 "L2: No ECC present, or ECC disabled\n");
1245 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1247 struct altr_edac_device_dev *dci = dev_id;
1249 if (irq == dci->sb_irq) {
1250 regmap_write(dci->edac->ecc_mgr_map,
1251 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1252 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1253 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1256 } else if (irq == dci->db_irq) {
1257 regmap_write(dci->edac->ecc_mgr_map,
1258 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1259 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1260 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1261 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1271 static const struct edac_device_prv_data l2ecc_data = {
1272 .setup = altr_l2_check_deps,
1275 .alloc_mem = l2_alloc_mem,
1276 .free_mem = l2_free_mem,
1277 .ecc_enable_mask = ALTR_L2_ECC_EN,
1278 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1279 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1280 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1281 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1282 .inject_fops = &altr_edac_device_inject_fops,
1285 static const struct edac_device_prv_data a10_l2ecc_data = {
1286 .setup = altr_l2_check_deps,
1287 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1288 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1289 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1290 .alloc_mem = l2_alloc_mem,
1291 .free_mem = l2_free_mem,
1292 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1293 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1294 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1295 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1296 .ecc_irq_handler = altr_edac_a10_l2_irq,
1297 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1298 .inject_fops = &altr_edac_device_inject_fops,
1301 #endif /* CONFIG_EDAC_ALTERA_L2C */
1303 /********************* Ethernet Device Functions ********************/
1305 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1307 static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
1311 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1315 return altr_check_ecc_deps(dev);
1318 static const struct edac_device_prv_data a10_enetecc_data = {
1319 .setup = socfpga_init_ethernet_ecc,
1320 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1321 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1322 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1323 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1324 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1325 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1326 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1327 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1328 .inject_fops = &altr_edac_a10_device_inject2_fops,
1331 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1333 /********************** NAND Device Functions **********************/
1335 #ifdef CONFIG_EDAC_ALTERA_NAND
1337 static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
1341 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1345 return altr_check_ecc_deps(device);
1348 static const struct edac_device_prv_data a10_nandecc_data = {
1349 .setup = socfpga_init_nand_ecc,
1350 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1351 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1352 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1353 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1354 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1355 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1356 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1357 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1358 .inject_fops = &altr_edac_a10_device_inject_fops,
1361 #endif /* CONFIG_EDAC_ALTERA_NAND */
1363 /********************** DMA Device Functions **********************/
1365 #ifdef CONFIG_EDAC_ALTERA_DMA
1367 static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
1371 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1375 return altr_check_ecc_deps(device);
1378 static const struct edac_device_prv_data a10_dmaecc_data = {
1379 .setup = socfpga_init_dma_ecc,
1380 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1381 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1382 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1383 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1384 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1385 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1386 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1387 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1388 .inject_fops = &altr_edac_a10_device_inject_fops,
1391 #endif /* CONFIG_EDAC_ALTERA_DMA */
1393 /********************** USB Device Functions **********************/
1395 #ifdef CONFIG_EDAC_ALTERA_USB
1397 static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
1401 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1405 return altr_check_ecc_deps(device);
1408 static const struct edac_device_prv_data a10_usbecc_data = {
1409 .setup = socfpga_init_usb_ecc,
1410 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1411 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1412 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1413 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1414 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1415 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1416 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1417 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1418 .inject_fops = &altr_edac_a10_device_inject2_fops,
1421 #endif /* CONFIG_EDAC_ALTERA_USB */
1423 /********************** QSPI Device Functions **********************/
1425 #ifdef CONFIG_EDAC_ALTERA_QSPI
1427 static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
1431 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1435 return altr_check_ecc_deps(device);
1438 static const struct edac_device_prv_data a10_qspiecc_data = {
1439 .setup = socfpga_init_qspi_ecc,
1440 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1441 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1442 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1443 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1444 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1445 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1446 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1447 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1448 .inject_fops = &altr_edac_a10_device_inject_fops,
1451 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1453 /********************* SDMMC Device Functions **********************/
1455 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1457 static const struct edac_device_prv_data a10_sdmmceccb_data;
1458 static int altr_portb_setup(struct altr_edac_device_dev *device)
1460 struct edac_device_ctl_info *dci;
1461 struct altr_edac_device_dev *altdev;
1462 char *ecc_name = "sdmmcb-ecc";
1464 struct device_node *np;
1465 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1467 rc = altr_check_ecc_deps(device);
1471 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1473 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1477 /* Create the PortB EDAC device */
1478 edac_idx = edac_device_alloc_index();
1479 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1480 ecc_name, 1, 0, NULL, 0, edac_idx);
1482 edac_printk(KERN_ERR, EDAC_DEVICE,
1483 "%s: Unable to allocate PortB EDAC device\n",
1488 /* Initialize the PortB EDAC device structure from PortA structure */
1489 altdev = dci->pvt_info;
1492 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1495 /* Update PortB specific values */
1496 altdev->edac_dev_name = ecc_name;
1497 altdev->edac_idx = edac_idx;
1498 altdev->edac_dev = dci;
1500 dci->dev = &altdev->ddev;
1501 dci->ctl_name = "Altera ECC Manager";
1502 dci->mod_name = ecc_name;
1503 dci->dev_name = ecc_name;
1506 * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly
1508 * FIXME: Instead of ifdefs with different architectures the driver
1509 * should properly use compatibles.
1512 altdev->sb_irq = irq_of_parse_and_map(np, 1);
1514 altdev->sb_irq = irq_of_parse_and_map(np, 2);
1516 if (!altdev->sb_irq) {
1517 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1519 goto err_release_group_1;
1521 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1522 prv->ecc_irq_handler,
1523 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1526 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1527 goto err_release_group_1;
1531 /* Use IRQ to determine SError origin instead of assigning IRQ */
1532 rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
1534 edac_printk(KERN_ERR, EDAC_DEVICE,
1535 "Error PortB DBIRQ alloc\n");
1536 goto err_release_group_1;
1539 altdev->db_irq = irq_of_parse_and_map(np, 3);
1540 if (!altdev->db_irq) {
1541 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1543 goto err_release_group_1;
1545 rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1546 prv->ecc_irq_handler,
1547 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1550 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1551 goto err_release_group_1;
1555 rc = edac_device_add_device(dci);
1557 edac_printk(KERN_ERR, EDAC_DEVICE,
1558 "edac_device_add_device portB failed\n");
1560 goto err_release_group_1;
1562 altr_create_edacdev_dbgfs(dci, prv);
1564 list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1566 devres_remove_group(&altdev->ddev, altr_portb_setup);
1570 err_release_group_1:
1571 edac_device_free_ctl_info(dci);
1572 devres_release_group(&altdev->ddev, altr_portb_setup);
1573 edac_printk(KERN_ERR, EDAC_DEVICE,
1574 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1578 static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
1581 struct device_node *child;
1583 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1587 if (!of_device_is_available(child))
1590 if (validate_parent_available(child))
1594 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1595 a10_sdmmceccb_data.ecc_enable_mask, 1);
1600 return altr_portb_setup(device);
1607 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1609 struct altr_edac_device_dev *ad = dev_id;
1610 void __iomem *base = ad->base;
1611 const struct edac_device_prv_data *priv = ad->data;
1613 if (irq == ad->sb_irq) {
1614 writel(priv->ce_clear_mask,
1615 base + ALTR_A10_ECC_INTSTAT_OFST);
1616 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1618 } else if (irq == ad->db_irq) {
1619 writel(priv->ue_clear_mask,
1620 base + ALTR_A10_ECC_INTSTAT_OFST);
1621 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1625 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1630 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1631 .setup = socfpga_init_sdmmc_ecc,
1632 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1633 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1634 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1635 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1636 .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1637 .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1638 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1639 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1640 .inject_fops = &altr_edac_a10_device_inject_fops,
1643 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1644 .setup = socfpga_init_sdmmc_ecc,
1645 .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1646 .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1647 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1648 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1649 .ce_set_mask = ALTR_A10_ECC_TSERRB,
1650 .ue_set_mask = ALTR_A10_ECC_TDERRB,
1651 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1652 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1653 .inject_fops = &altr_edac_a10_device_inject_fops,
1656 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1658 /********************* Arria10 EDAC Device Functions *************************/
1659 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1660 #ifdef CONFIG_EDAC_ALTERA_L2C
1661 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1663 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1664 { .compatible = "altr,socfpga-a10-ocram-ecc",
1665 .data = &a10_ocramecc_data },
1667 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1668 { .compatible = "altr,socfpga-eth-mac-ecc",
1669 .data = &a10_enetecc_data },
1671 #ifdef CONFIG_EDAC_ALTERA_NAND
1672 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1674 #ifdef CONFIG_EDAC_ALTERA_DMA
1675 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1677 #ifdef CONFIG_EDAC_ALTERA_USB
1678 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1680 #ifdef CONFIG_EDAC_ALTERA_QSPI
1681 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1683 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1684 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1686 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1687 { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
1691 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1694 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1695 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1696 * manager manages the IRQs and the children.
1697 * Based on xgene_edac.c peripheral code.
1700 static ssize_t altr_edac_a10_device_trig(struct file *file,
1701 const char __user *user_buf,
1702 size_t count, loff_t *ppos)
1704 struct edac_device_ctl_info *edac_dci = file->private_data;
1705 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1706 const struct edac_device_prv_data *priv = drvdata->data;
1707 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1708 unsigned long flags;
1711 if (!user_buf || get_user(trig_type, user_buf))
1714 local_irq_save(flags);
1715 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1716 writel(priv->ue_set_mask, set_addr);
1718 writel(priv->ce_set_mask, set_addr);
1720 /* Ensure the interrupt test bits are set */
1722 local_irq_restore(flags);
1728 * The Stratix10 EDAC Error Injection Functions differ from Arria10
1729 * slightly. A few Arria10 peripherals can use this injection function.
1730 * Inject the error into the memory and then readback to trigger the IRQ.
1732 static ssize_t altr_edac_a10_device_trig2(struct file *file,
1733 const char __user *user_buf,
1734 size_t count, loff_t *ppos)
1736 struct edac_device_ctl_info *edac_dci = file->private_data;
1737 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1738 const struct edac_device_prv_data *priv = drvdata->data;
1739 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1740 unsigned long flags;
1743 if (!user_buf || get_user(trig_type, user_buf))
1746 local_irq_save(flags);
1747 if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1748 writel(priv->ue_set_mask, set_addr);
1750 /* Setup read/write of 4 bytes */
1751 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1752 /* Setup Address to 0 */
1753 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1754 /* Setup accctrl to read & ecc & data override */
1755 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1757 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1758 /* Setup write for single bit change */
1759 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
1760 drvdata->base + ECC_BLK_WDATA0_OFST);
1761 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
1762 drvdata->base + ECC_BLK_WDATA1_OFST);
1763 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
1764 drvdata->base + ECC_BLK_WDATA2_OFST);
1765 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
1766 drvdata->base + ECC_BLK_WDATA3_OFST);
1768 /* Copy Read ECC to Write ECC */
1769 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1770 drvdata->base + ECC_BLK_WECC0_OFST);
1771 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1772 drvdata->base + ECC_BLK_WECC1_OFST);
1773 /* Setup accctrl to write & ecc override & data override */
1774 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1776 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1777 /* Setup accctrl to read & ecc overwrite & data overwrite */
1778 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1780 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1783 /* Ensure the interrupt test bits are set */
1785 local_irq_restore(flags);
1790 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1792 int dberr, bit, sm_offset, irq_status;
1793 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1794 struct irq_chip *chip = irq_desc_get_chip(desc);
1795 int irq = irq_desc_get_irq(desc);
1798 dberr = (irq == edac->db_irq) ? 1 : 0;
1799 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1800 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1802 chained_irq_enter(chip, desc);
1804 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1807 for_each_set_bit(bit, &bits, 32) {
1808 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1810 generic_handle_irq(irq);
1813 chained_irq_exit(chip, desc);
1816 static int validate_parent_available(struct device_node *np)
1818 struct device_node *parent;
1821 /* SDRAM must be present for Linux (implied parent) */
1822 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1825 /* Ensure parent device is enabled if parent node exists */
1826 parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1827 if (parent && !of_device_is_available(parent))
1830 of_node_put(parent);
1834 static int get_s10_sdram_edac_resource(struct device_node *np,
1835 struct resource *res)
1837 struct device_node *parent;
1840 parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
1844 ret = of_address_to_resource(parent, 0, res);
1845 of_node_put(parent);
1850 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1851 struct device_node *np)
1853 struct edac_device_ctl_info *dci;
1854 struct altr_edac_device_dev *altdev;
1855 char *ecc_name = (char *)np->name;
1856 struct resource res;
1859 const struct edac_device_prv_data *prv;
1860 /* Get matching node and check for valid result */
1861 const struct of_device_id *pdev_id =
1862 of_match_node(altr_edac_a10_device_of_match, np);
1863 if (IS_ERR_OR_NULL(pdev_id))
1866 /* Get driver specific data for this EDAC device */
1867 prv = pdev_id->data;
1868 if (IS_ERR_OR_NULL(prv))
1871 if (validate_parent_available(np))
1874 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1877 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1878 rc = get_s10_sdram_edac_resource(np, &res);
1880 rc = of_address_to_resource(np, 0, &res);
1883 edac_printk(KERN_ERR, EDAC_DEVICE,
1884 "%s: no resource address\n", ecc_name);
1885 goto err_release_group;
1888 edac_idx = edac_device_alloc_index();
1889 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1890 1, ecc_name, 1, 0, NULL, 0,
1894 edac_printk(KERN_ERR, EDAC_DEVICE,
1895 "%s: Unable to allocate EDAC device\n", ecc_name);
1897 goto err_release_group;
1900 altdev = dci->pvt_info;
1901 dci->dev = edac->dev;
1902 altdev->edac_dev_name = ecc_name;
1903 altdev->edac_idx = edac_idx;
1904 altdev->edac = edac;
1905 altdev->edac_dev = dci;
1907 altdev->ddev = *edac->dev;
1908 dci->dev = &altdev->ddev;
1909 dci->ctl_name = "Altera ECC Manager";
1910 dci->mod_name = ecc_name;
1911 dci->dev_name = ecc_name;
1913 altdev->base = devm_ioremap_resource(edac->dev, &res);
1914 if (IS_ERR(altdev->base)) {
1915 rc = PTR_ERR(altdev->base);
1916 goto err_release_group1;
1919 /* Check specific dependencies for the module */
1920 if (altdev->data->setup) {
1921 rc = altdev->data->setup(altdev);
1923 goto err_release_group1;
1926 altdev->sb_irq = irq_of_parse_and_map(np, 0);
1927 if (!altdev->sb_irq) {
1928 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1930 goto err_release_group1;
1932 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1933 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1936 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1937 goto err_release_group1;
1941 /* Use IRQ to determine SError origin instead of assigning IRQ */
1942 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
1944 edac_printk(KERN_ERR, EDAC_DEVICE,
1945 "Unable to parse DB IRQ index\n");
1946 goto err_release_group1;
1949 altdev->db_irq = irq_of_parse_and_map(np, 1);
1950 if (!altdev->db_irq) {
1951 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1953 goto err_release_group1;
1955 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1956 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1959 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1960 goto err_release_group1;
1964 rc = edac_device_add_device(dci);
1966 dev_err(edac->dev, "edac_device_add_device failed\n");
1968 goto err_release_group1;
1971 altr_create_edacdev_dbgfs(dci, prv);
1973 list_add(&altdev->next, &edac->a10_ecc_devices);
1975 devres_remove_group(edac->dev, altr_edac_a10_device_add);
1980 edac_device_free_ctl_info(dci);
1982 devres_release_group(edac->dev, NULL);
1983 edac_printk(KERN_ERR, EDAC_DEVICE,
1984 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1989 static void a10_eccmgr_irq_mask(struct irq_data *d)
1991 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1993 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
1997 static void a10_eccmgr_irq_unmask(struct irq_data *d)
1999 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2001 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2005 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2006 irq_hw_number_t hwirq)
2008 struct altr_arria10_edac *edac = d->host_data;
2010 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2011 irq_set_chip_data(irq, edac);
2012 irq_set_noprobe(irq);
2017 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2018 .map = a10_eccmgr_irqdomain_map,
2019 .xlate = irq_domain_xlate_twocell,
2022 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2023 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2026 /* panic routine issues reboot on non-zero panic_timeout */
2027 extern int panic_timeout;
2030 * The double bit error is handled through SError which is fatal. This is
2031 * called as a panic notifier to printout ECC error info as part of the panic.
2033 static int s10_edac_dberr_handler(struct notifier_block *this,
2034 unsigned long event, void *ptr)
2036 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2037 int err_addr, dberror;
2039 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2041 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2042 if (dberror & S10_DBE_IRQ_MASK) {
2043 struct list_head *position;
2044 struct altr_edac_device_dev *ed;
2045 struct arm_smccc_res result;
2047 /* Find the matching DBE in the list of devices */
2048 list_for_each(position, &edac->a10_ecc_devices) {
2049 ed = list_entry(position, struct altr_edac_device_dev,
2051 if (!(BIT(ed->db_irq) & dberror))
2054 writel(ALTR_A10_ECC_DERRPENA,
2055 ed->base + ALTR_A10_ECC_INTSTAT_OFST);
2056 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
2057 regmap_write(edac->ecc_mgr_map,
2058 S10_SYSMGR_UE_ADDR_OFST, err_addr);
2059 edac_printk(KERN_ERR, EDAC_DEVICE,
2060 "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2061 ed->edac_dev_name, err_addr);
2064 /* Notify the System through SMC. Reboot delay = 1 second */
2066 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
2074 /****************** Arria 10 EDAC Probe Function *********************/
2075 static int altr_edac_a10_probe(struct platform_device *pdev)
2077 struct altr_arria10_edac *edac;
2078 struct device_node *child;
2080 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2084 edac->dev = &pdev->dev;
2085 platform_set_drvdata(pdev, edac);
2086 INIT_LIST_HEAD(&edac->a10_ecc_devices);
2089 altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node,
2090 "altr,sysmgr-syscon");
2092 if (IS_ERR(edac->ecc_mgr_map)) {
2093 edac_printk(KERN_ERR, EDAC_DEVICE,
2094 "Unable to get syscon altr,sysmgr-syscon\n");
2095 return PTR_ERR(edac->ecc_mgr_map);
2098 edac->irq_chip.name = pdev->dev.of_node->name;
2099 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2100 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2101 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2102 &a10_eccmgr_ic_ops, edac);
2103 if (!edac->domain) {
2104 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2108 edac->sb_irq = platform_get_irq(pdev, 0);
2109 if (edac->sb_irq < 0) {
2110 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2111 return edac->sb_irq;
2114 irq_set_chained_handler_and_data(edac->sb_irq,
2115 altr_edac_a10_irq_handler,
2120 int dberror, err_addr;
2122 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2123 atomic_notifier_chain_register(&panic_notifier_list,
2124 &edac->panic_notifier);
2126 /* Printout a message if uncorrectable error previously. */
2127 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2130 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2132 edac_printk(KERN_ERR, EDAC_DEVICE,
2133 "Previous Boot UE detected[0x%X] @ 0x%X\n",
2135 /* Reset the sticky registers */
2136 regmap_write(edac->ecc_mgr_map,
2137 S10_SYSMGR_UE_VAL_OFST, 0);
2138 regmap_write(edac->ecc_mgr_map,
2139 S10_SYSMGR_UE_ADDR_OFST, 0);
2143 edac->db_irq = platform_get_irq(pdev, 1);
2144 if (edac->db_irq < 0) {
2145 dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2146 return edac->db_irq;
2148 irq_set_chained_handler_and_data(edac->db_irq,
2149 altr_edac_a10_irq_handler, edac);
2152 for_each_child_of_node(pdev->dev.of_node, child) {
2153 if (!of_device_is_available(child))
2156 if (of_match_node(altr_edac_a10_device_of_match, child))
2157 altr_edac_a10_device_add(edac, child);
2159 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2160 else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2161 of_platform_populate(pdev->dev.of_node,
2162 altr_sdram_ctrl_of_match,
2170 static const struct of_device_id altr_edac_a10_of_match[] = {
2171 { .compatible = "altr,socfpga-a10-ecc-manager" },
2172 { .compatible = "altr,socfpga-s10-ecc-manager" },
2175 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2177 static struct platform_driver altr_edac_a10_driver = {
2178 .probe = altr_edac_a10_probe,
2180 .name = "socfpga_a10_ecc_manager",
2181 .of_match_table = altr_edac_a10_of_match,
2184 module_platform_driver(altr_edac_a10_driver);
2186 MODULE_LICENSE("GPL v2");
2187 MODULE_AUTHOR("Thor Thayer");
2188 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");