1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx Video DMA Engine
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
7 * Based on the Freescale DMA driver.
10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
13 * two dimensional DMA operations with independent asynchronous read (S2MM)
14 * and write (MM2S) channel operation. It can be configured to have either
15 * one channel or two channels. If configured as two channels, one is to
16 * transmit to the video device (MM2S) and another is to receive from the
17 * video device (S2MM). Initialization, status, interrupt and management
18 * registers are accessed through an AXI4-Lite slave interface.
20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
23 * transmit channel, both of them optional at synthesis time.
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
26 * Access (DMA) between a memory-mapped source address and a memory-mapped
27 * destination address.
30 #include <linux/bitops.h>
31 #include <linux/dmapool.h>
32 #include <linux/dma/xilinx_dma.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
36 #include <linux/iopoll.h>
37 #include <linux/module.h>
38 #include <linux/of_address.h>
39 #include <linux/of_dma.h>
40 #include <linux/of_platform.h>
41 #include <linux/of_irq.h>
42 #include <linux/slab.h>
43 #include <linux/clk.h>
44 #include <linux/io-64-nonatomic-lo-hi.h>
46 #include "../dmaengine.h"
48 /* Register/Descriptor Offsets */
49 #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000
50 #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030
51 #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050
52 #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0
54 /* Control Registers */
55 #define XILINX_DMA_REG_DMACR 0x0000
56 #define XILINX_DMA_DMACR_DELAY_MAX 0xff
57 #define XILINX_DMA_DMACR_DELAY_SHIFT 24
58 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff
59 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16
60 #define XILINX_DMA_DMACR_ERR_IRQ BIT(14)
61 #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13)
62 #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12)
63 #define XILINX_DMA_DMACR_MASTER_SHIFT 8
64 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
65 #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4)
66 #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3)
67 #define XILINX_DMA_DMACR_RESET BIT(2)
68 #define XILINX_DMA_DMACR_CIRC_EN BIT(1)
69 #define XILINX_DMA_DMACR_RUNSTOP BIT(0)
70 #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
72 #define XILINX_DMA_REG_DMASR 0x0004
73 #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
74 #define XILINX_DMA_DMASR_ERR_IRQ BIT(14)
75 #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13)
76 #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12)
77 #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11)
78 #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10)
79 #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9)
80 #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8)
81 #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7)
82 #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6)
83 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5)
84 #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4)
85 #define XILINX_DMA_DMASR_SG_MASK BIT(3)
86 #define XILINX_DMA_DMASR_IDLE BIT(1)
87 #define XILINX_DMA_DMASR_HALTED BIT(0)
88 #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24)
89 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16)
91 #define XILINX_DMA_REG_CURDESC 0x0008
92 #define XILINX_DMA_REG_TAILDESC 0x0010
93 #define XILINX_DMA_REG_REG_INDEX 0x0014
94 #define XILINX_DMA_REG_FRMSTORE 0x0018
95 #define XILINX_DMA_REG_THRESHOLD 0x001c
96 #define XILINX_DMA_REG_FRMPTR_STS 0x0024
97 #define XILINX_DMA_REG_PARK_PTR 0x0028
98 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8
99 #define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8)
100 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0
101 #define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0)
102 #define XILINX_DMA_REG_VDMA_VERSION 0x002c
104 /* Register Direct Mode Registers */
105 #define XILINX_DMA_REG_VSIZE 0x0000
106 #define XILINX_DMA_REG_HSIZE 0x0004
108 #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008
109 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24
110 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0
112 #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n))
113 #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n))
115 #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec
116 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0)
118 /* HW specific definitions */
119 #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x20
121 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \
122 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \
123 XILINX_DMA_DMASR_DLY_CNT_IRQ | \
124 XILINX_DMA_DMASR_ERR_IRQ)
126 #define XILINX_DMA_DMASR_ALL_ERR_MASK \
127 (XILINX_DMA_DMASR_EOL_LATE_ERR | \
128 XILINX_DMA_DMASR_SOF_LATE_ERR | \
129 XILINX_DMA_DMASR_SG_DEC_ERR | \
130 XILINX_DMA_DMASR_SG_SLV_ERR | \
131 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
132 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
133 XILINX_DMA_DMASR_DMA_DEC_ERR | \
134 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
135 XILINX_DMA_DMASR_DMA_INT_ERR)
138 * Recoverable errors are DMA Internal error, SOF Early, EOF Early
139 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
140 * is enabled in the h/w system.
142 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \
143 (XILINX_DMA_DMASR_SOF_LATE_ERR | \
144 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
145 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
146 XILINX_DMA_DMASR_DMA_INT_ERR)
148 /* Axi VDMA Flush on Fsync bits */
149 #define XILINX_DMA_FLUSH_S2MM 3
150 #define XILINX_DMA_FLUSH_MM2S 2
151 #define XILINX_DMA_FLUSH_BOTH 1
153 /* Delay loop counter to prevent hardware failure */
154 #define XILINX_DMA_LOOP_COUNT 1000000
156 /* AXI DMA Specific Registers/Offsets */
157 #define XILINX_DMA_REG_SRCDSTADDR 0x18
158 #define XILINX_DMA_REG_BTT 0x28
160 /* AXI DMA Specific Masks/Bit fields */
161 #define XILINX_DMA_MAX_TRANS_LEN_MIN 8
162 #define XILINX_DMA_MAX_TRANS_LEN_MAX 23
163 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26
164 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16)
165 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)
166 #define XILINX_DMA_CR_COALESCE_SHIFT 16
167 #define XILINX_DMA_BD_SOP BIT(27)
168 #define XILINX_DMA_BD_EOP BIT(26)
169 #define XILINX_DMA_COALESCE_MAX 255
170 #define XILINX_DMA_NUM_DESCS 255
171 #define XILINX_DMA_NUM_APP_WORDS 5
173 /* Multi-Channel DMA Descriptor offsets*/
174 #define XILINX_DMA_MCRX_CDESC(x) (0x40 + (x-1) * 0x20)
175 #define XILINX_DMA_MCRX_TDESC(x) (0x48 + (x-1) * 0x20)
177 /* Multi-Channel DMA Masks/Shifts */
178 #define XILINX_DMA_BD_HSIZE_MASK GENMASK(15, 0)
179 #define XILINX_DMA_BD_STRIDE_MASK GENMASK(15, 0)
180 #define XILINX_DMA_BD_VSIZE_MASK GENMASK(31, 19)
181 #define XILINX_DMA_BD_TDEST_MASK GENMASK(4, 0)
182 #define XILINX_DMA_BD_STRIDE_SHIFT 0
183 #define XILINX_DMA_BD_VSIZE_SHIFT 19
185 /* AXI CDMA Specific Registers/Offsets */
186 #define XILINX_CDMA_REG_SRCADDR 0x18
187 #define XILINX_CDMA_REG_DSTADDR 0x20
189 /* AXI CDMA Specific Masks */
190 #define XILINX_CDMA_CR_SGMODE BIT(3)
192 #define xilinx_prep_dma_addr_t(addr) \
193 ((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
195 * struct xilinx_vdma_desc_hw - Hardware Descriptor
196 * @next_desc: Next Descriptor Pointer @0x00
197 * @pad1: Reserved @0x04
198 * @buf_addr: Buffer address @0x08
199 * @buf_addr_msb: MSB of Buffer address @0x0C
200 * @vsize: Vertical Size @0x10
201 * @hsize: Horizontal Size @0x14
202 * @stride: Number of bytes between the first
203 * pixels of each horizontal line @0x18
205 struct xilinx_vdma_desc_hw {
216 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
217 * @next_desc: Next Descriptor Pointer @0x00
218 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
219 * @buf_addr: Buffer address @0x08
220 * @buf_addr_msb: MSB of Buffer address @0x0C
221 * @mcdma_control: Control field for mcdma @0x10
222 * @vsize_stride: Vsize and Stride field for mcdma @0x14
223 * @control: Control field @0x18
224 * @status: Status field @0x1C
225 * @app: APP Fields @0x20 - 0x30
227 struct xilinx_axidma_desc_hw {
236 u32 app[XILINX_DMA_NUM_APP_WORDS];
240 * struct xilinx_cdma_desc_hw - Hardware Descriptor
241 * @next_desc: Next Descriptor Pointer @0x00
242 * @next_desc_msb: Next Descriptor Pointer MSB @0x04
243 * @src_addr: Source address @0x08
244 * @src_addr_msb: Source address MSB @0x0C
245 * @dest_addr: Destination address @0x10
246 * @dest_addr_msb: Destination address MSB @0x14
247 * @control: Control field @0x18
248 * @status: Status field @0x1C
250 struct xilinx_cdma_desc_hw {
262 * struct xilinx_vdma_tx_segment - Descriptor segment
263 * @hw: Hardware descriptor
264 * @node: Node in the descriptor segments list
265 * @phys: Physical address of segment
267 struct xilinx_vdma_tx_segment {
268 struct xilinx_vdma_desc_hw hw;
269 struct list_head node;
274 * struct xilinx_axidma_tx_segment - Descriptor segment
275 * @hw: Hardware descriptor
276 * @node: Node in the descriptor segments list
277 * @phys: Physical address of segment
279 struct xilinx_axidma_tx_segment {
280 struct xilinx_axidma_desc_hw hw;
281 struct list_head node;
286 * struct xilinx_cdma_tx_segment - Descriptor segment
287 * @hw: Hardware descriptor
288 * @node: Node in the descriptor segments list
289 * @phys: Physical address of segment
291 struct xilinx_cdma_tx_segment {
292 struct xilinx_cdma_desc_hw hw;
293 struct list_head node;
298 * struct xilinx_dma_tx_descriptor - Per Transaction structure
299 * @async_tx: Async transaction descriptor
300 * @segments: TX segments list
301 * @node: Node in the channel descriptors list
302 * @cyclic: Check for cyclic transfers.
304 struct xilinx_dma_tx_descriptor {
305 struct dma_async_tx_descriptor async_tx;
306 struct list_head segments;
307 struct list_head node;
312 * struct xilinx_dma_chan - Driver specific DMA channel structure
313 * @xdev: Driver specific device structure
314 * @ctrl_offset: Control registers offset
315 * @desc_offset: TX descriptor registers offset
316 * @lock: Descriptor operation lock
317 * @pending_list: Descriptors waiting
318 * @active_list: Descriptors ready to submit
319 * @done_list: Complete descriptors
320 * @free_seg_list: Free descriptors
321 * @common: DMA common channel
322 * @desc_pool: Descriptors pool
323 * @dev: The dma device
326 * @direction: Transfer direction
327 * @num_frms: Number of frames
328 * @has_sg: Support scatter transfers
329 * @cyclic: Check for cyclic transfers.
330 * @genlock: Support genlock mode
331 * @err: Channel has errors
332 * @idle: Check for channel idle
333 * @tasklet: Cleanup work after irq
334 * @config: Device configuration info
335 * @flush_on_fsync: Flush on Frame sync
336 * @desc_pendingcount: Descriptor pending count
337 * @ext_addr: Indicates 64 bit addressing is supported by dma channel
338 * @desc_submitcount: Descriptor h/w submitted count
339 * @residue: Residue for AXI DMA
340 * @seg_v: Statically allocated segments base
341 * @seg_p: Physical allocated segments base
342 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
343 * @cyclic_seg_p: Physical allocated segments base for cyclic dma
344 * @start_transfer: Differentiate b/w DMA IP's transfer
345 * @stop_transfer: Differentiate b/w DMA IP's quiesce
346 * @tdest: TDEST value for mcdma
347 * @has_vflip: S2MM vertical flip
349 struct xilinx_dma_chan {
350 struct xilinx_dma_device *xdev;
354 struct list_head pending_list;
355 struct list_head active_list;
356 struct list_head done_list;
357 struct list_head free_seg_list;
358 struct dma_chan common;
359 struct dma_pool *desc_pool;
363 enum dma_transfer_direction direction;
370 struct tasklet_struct tasklet;
371 struct xilinx_vdma_config config;
373 u32 desc_pendingcount;
375 u32 desc_submitcount;
377 struct xilinx_axidma_tx_segment *seg_v;
379 struct xilinx_axidma_tx_segment *cyclic_seg_v;
380 dma_addr_t cyclic_seg_p;
381 void (*start_transfer)(struct xilinx_dma_chan *chan);
382 int (*stop_transfer)(struct xilinx_dma_chan *chan);
388 * enum xdma_ip_type - DMA IP type.
390 * @XDMA_TYPE_AXIDMA: Axi dma ip.
391 * @XDMA_TYPE_CDMA: Axi cdma ip.
392 * @XDMA_TYPE_VDMA: Axi vdma ip.
396 XDMA_TYPE_AXIDMA = 0,
401 struct xilinx_dma_config {
402 enum xdma_ip_type dmatype;
403 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
404 struct clk **tx_clk, struct clk **txs_clk,
405 struct clk **rx_clk, struct clk **rxs_clk);
409 * struct xilinx_dma_device - DMA device structure
410 * @regs: I/O mapped base address
411 * @dev: Device Structure
412 * @common: DMA device structure
413 * @chan: Driver specific DMA channel
414 * @mcdma: Specifies whether Multi-Channel is present or not
415 * @flush_on_fsync: Flush on frame sync
416 * @ext_addr: Indicates 64 bit addressing is supported by dma device
417 * @pdev: Platform device structure pointer
418 * @dma_config: DMA config structure
419 * @axi_clk: DMA Axi4-lite interace clock
420 * @tx_clk: DMA mm2s clock
421 * @txs_clk: DMA mm2s stream clock
422 * @rx_clk: DMA s2mm clock
423 * @rxs_clk: DMA s2mm stream clock
424 * @nr_channels: Number of channels DMA device supports
425 * @chan_id: DMA channel identifier
426 * @max_buffer_len: Max buffer length
428 struct xilinx_dma_device {
431 struct dma_device common;
432 struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE];
436 struct platform_device *pdev;
437 const struct xilinx_dma_config *dma_config;
449 #define to_xilinx_chan(chan) \
450 container_of(chan, struct xilinx_dma_chan, common)
451 #define to_dma_tx_descriptor(tx) \
452 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
453 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
454 readl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \
455 cond, delay_us, timeout_us)
458 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
460 return ioread32(chan->xdev->regs + reg);
463 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
465 iowrite32(value, chan->xdev->regs + reg);
468 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
471 dma_write(chan, chan->desc_offset + reg, value);
474 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
476 return dma_read(chan, chan->ctrl_offset + reg);
479 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
482 dma_write(chan, chan->ctrl_offset + reg, value);
485 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
488 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
491 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
494 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
498 * vdma_desc_write_64 - 64-bit descriptor write
499 * @chan: Driver specific VDMA channel
500 * @reg: Register to write
501 * @value_lsb: lower address of the descriptor.
502 * @value_msb: upper address of the descriptor.
504 * Since vdma driver is trying to write to a register offset which is not a
505 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
506 * instead of a single 64 bit register write.
508 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
509 u32 value_lsb, u32 value_msb)
511 /* Write the lsb 32 bits*/
512 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
514 /* Write the msb 32 bits */
515 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
518 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
520 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
523 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
527 dma_writeq(chan, reg, addr);
529 dma_ctrl_write(chan, reg, addr);
532 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
533 struct xilinx_axidma_desc_hw *hw,
534 dma_addr_t buf_addr, size_t sg_used,
537 if (chan->ext_addr) {
538 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);
539 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +
542 hw->buf_addr = buf_addr + sg_used + period_len;
546 /* -----------------------------------------------------------------------------
547 * Descriptors and segments alloc and free
551 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
552 * @chan: Driver specific DMA channel
554 * Return: The allocated segment on success and NULL on failure.
556 static struct xilinx_vdma_tx_segment *
557 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
559 struct xilinx_vdma_tx_segment *segment;
562 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
566 segment->phys = phys;
572 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
573 * @chan: Driver specific DMA channel
575 * Return: The allocated segment on success and NULL on failure.
577 static struct xilinx_cdma_tx_segment *
578 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
580 struct xilinx_cdma_tx_segment *segment;
583 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
587 segment->phys = phys;
593 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
594 * @chan: Driver specific DMA channel
596 * Return: The allocated segment on success and NULL on failure.
598 static struct xilinx_axidma_tx_segment *
599 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
601 struct xilinx_axidma_tx_segment *segment = NULL;
604 spin_lock_irqsave(&chan->lock, flags);
605 if (!list_empty(&chan->free_seg_list)) {
606 segment = list_first_entry(&chan->free_seg_list,
607 struct xilinx_axidma_tx_segment,
609 list_del(&segment->node);
611 spin_unlock_irqrestore(&chan->lock, flags);
616 static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)
618 u32 next_desc = hw->next_desc;
619 u32 next_desc_msb = hw->next_desc_msb;
621 memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));
623 hw->next_desc = next_desc;
624 hw->next_desc_msb = next_desc_msb;
628 * xilinx_dma_free_tx_segment - Free transaction segment
629 * @chan: Driver specific DMA channel
630 * @segment: DMA transaction segment
632 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
633 struct xilinx_axidma_tx_segment *segment)
635 xilinx_dma_clean_hw_desc(&segment->hw);
637 list_add_tail(&segment->node, &chan->free_seg_list);
641 * xilinx_cdma_free_tx_segment - Free transaction segment
642 * @chan: Driver specific DMA channel
643 * @segment: DMA transaction segment
645 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
646 struct xilinx_cdma_tx_segment *segment)
648 dma_pool_free(chan->desc_pool, segment, segment->phys);
652 * xilinx_vdma_free_tx_segment - Free transaction segment
653 * @chan: Driver specific DMA channel
654 * @segment: DMA transaction segment
656 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
657 struct xilinx_vdma_tx_segment *segment)
659 dma_pool_free(chan->desc_pool, segment, segment->phys);
663 * xilinx_dma_tx_descriptor - Allocate transaction descriptor
664 * @chan: Driver specific DMA channel
666 * Return: The allocated descriptor on success and NULL on failure.
668 static struct xilinx_dma_tx_descriptor *
669 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
671 struct xilinx_dma_tx_descriptor *desc;
673 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
677 INIT_LIST_HEAD(&desc->segments);
683 * xilinx_dma_free_tx_descriptor - Free transaction descriptor
684 * @chan: Driver specific DMA channel
685 * @desc: DMA transaction descriptor
688 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
689 struct xilinx_dma_tx_descriptor *desc)
691 struct xilinx_vdma_tx_segment *segment, *next;
692 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;
693 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;
698 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
699 list_for_each_entry_safe(segment, next, &desc->segments, node) {
700 list_del(&segment->node);
701 xilinx_vdma_free_tx_segment(chan, segment);
703 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
704 list_for_each_entry_safe(cdma_segment, cdma_next,
705 &desc->segments, node) {
706 list_del(&cdma_segment->node);
707 xilinx_cdma_free_tx_segment(chan, cdma_segment);
710 list_for_each_entry_safe(axidma_segment, axidma_next,
711 &desc->segments, node) {
712 list_del(&axidma_segment->node);
713 xilinx_dma_free_tx_segment(chan, axidma_segment);
720 /* Required functions */
723 * xilinx_dma_free_desc_list - Free descriptors list
724 * @chan: Driver specific DMA channel
725 * @list: List to parse and delete the descriptor
727 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
728 struct list_head *list)
730 struct xilinx_dma_tx_descriptor *desc, *next;
732 list_for_each_entry_safe(desc, next, list, node) {
733 list_del(&desc->node);
734 xilinx_dma_free_tx_descriptor(chan, desc);
739 * xilinx_dma_free_descriptors - Free channel descriptors
740 * @chan: Driver specific DMA channel
742 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
746 spin_lock_irqsave(&chan->lock, flags);
748 xilinx_dma_free_desc_list(chan, &chan->pending_list);
749 xilinx_dma_free_desc_list(chan, &chan->done_list);
750 xilinx_dma_free_desc_list(chan, &chan->active_list);
752 spin_unlock_irqrestore(&chan->lock, flags);
756 * xilinx_dma_free_chan_resources - Free channel resources
757 * @dchan: DMA channel
759 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
761 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
764 dev_dbg(chan->dev, "Free all channel resources.\n");
766 xilinx_dma_free_descriptors(chan);
768 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
769 spin_lock_irqsave(&chan->lock, flags);
770 INIT_LIST_HEAD(&chan->free_seg_list);
771 spin_unlock_irqrestore(&chan->lock, flags);
773 /* Free memory that is allocated for BD */
774 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
775 XILINX_DMA_NUM_DESCS, chan->seg_v,
778 /* Free Memory that is allocated for cyclic DMA Mode */
779 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),
780 chan->cyclic_seg_v, chan->cyclic_seg_p);
783 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) {
784 dma_pool_destroy(chan->desc_pool);
785 chan->desc_pool = NULL;
790 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
791 * @chan: Driver specific dma channel
792 * @desc: dma transaction descriptor
793 * @flags: flags for spin lock
795 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
796 struct xilinx_dma_tx_descriptor *desc,
797 unsigned long *flags)
799 dma_async_tx_callback callback;
800 void *callback_param;
802 callback = desc->async_tx.callback;
803 callback_param = desc->async_tx.callback_param;
805 spin_unlock_irqrestore(&chan->lock, *flags);
806 callback(callback_param);
807 spin_lock_irqsave(&chan->lock, *flags);
812 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
813 * @chan: Driver specific DMA channel
815 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
817 struct xilinx_dma_tx_descriptor *desc, *next;
820 spin_lock_irqsave(&chan->lock, flags);
822 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
823 struct dmaengine_desc_callback cb;
826 xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
830 /* Remove from the list of running transactions */
831 list_del(&desc->node);
833 /* Run the link descriptor callback function */
834 dmaengine_desc_get_callback(&desc->async_tx, &cb);
835 if (dmaengine_desc_callback_valid(&cb)) {
836 spin_unlock_irqrestore(&chan->lock, flags);
837 dmaengine_desc_callback_invoke(&cb, NULL);
838 spin_lock_irqsave(&chan->lock, flags);
841 /* Run any dependencies, then free the descriptor */
842 dma_run_dependencies(&desc->async_tx);
843 xilinx_dma_free_tx_descriptor(chan, desc);
846 spin_unlock_irqrestore(&chan->lock, flags);
850 * xilinx_dma_do_tasklet - Schedule completion tasklet
851 * @data: Pointer to the Xilinx DMA channel structure
853 static void xilinx_dma_do_tasklet(unsigned long data)
855 struct xilinx_dma_chan *chan = (struct xilinx_dma_chan *)data;
857 xilinx_dma_chan_desc_cleanup(chan);
861 * xilinx_dma_alloc_chan_resources - Allocate channel resources
862 * @dchan: DMA channel
864 * Return: '0' on success and failure value on error
866 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
868 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
871 /* Has this channel already been allocated? */
876 * We need the descriptor to be aligned to 64bytes
877 * for meeting Xilinx VDMA specification requirement.
879 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
880 /* Allocate the buffer descriptors. */
881 chan->seg_v = dma_alloc_coherent(chan->dev,
882 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS,
883 &chan->seg_p, GFP_KERNEL);
886 "unable to allocate channel %d descriptors\n",
891 * For cyclic DMA mode we need to program the tail Descriptor
892 * register with a value which is not a part of the BD chain
893 * so allocating a desc segment during channel allocation for
894 * programming tail descriptor.
896 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev,
897 sizeof(*chan->cyclic_seg_v),
900 if (!chan->cyclic_seg_v) {
902 "unable to allocate desc segment for cyclic DMA\n");
903 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
904 XILINX_DMA_NUM_DESCS, chan->seg_v,
908 chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
910 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
911 chan->seg_v[i].hw.next_desc =
912 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
913 ((i + 1) % XILINX_DMA_NUM_DESCS));
914 chan->seg_v[i].hw.next_desc_msb =
915 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
916 ((i + 1) % XILINX_DMA_NUM_DESCS));
917 chan->seg_v[i].phys = chan->seg_p +
918 sizeof(*chan->seg_v) * i;
919 list_add_tail(&chan->seg_v[i].node,
920 &chan->free_seg_list);
922 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
923 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
925 sizeof(struct xilinx_cdma_tx_segment),
926 __alignof__(struct xilinx_cdma_tx_segment),
929 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
931 sizeof(struct xilinx_vdma_tx_segment),
932 __alignof__(struct xilinx_vdma_tx_segment),
936 if (!chan->desc_pool &&
937 (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA)) {
939 "unable to allocate channel %d descriptor pool\n",
944 dma_cookie_init(dchan);
946 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
947 /* For AXI DMA resetting once channel will reset the
948 * other channel as well so enable the interrupts here.
950 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
951 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
954 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
955 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
956 XILINX_CDMA_CR_SGMODE);
962 * xilinx_dma_calc_copysize - Calculate the amount of data to copy
963 * @chan: Driver specific DMA channel
964 * @size: Total data that needs to be copied
965 * @done: Amount of data that has been already copied
967 * Return: Amount of data that has to be copied
969 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
974 copy = min_t(size_t, size - done,
975 chan->xdev->max_buffer_len);
977 if ((copy + done < size) &&
978 chan->xdev->common.copy_align) {
980 * If this is not the last descriptor, make sure
981 * the next one will be properly aligned
983 copy = rounddown(copy,
984 (1 << chan->xdev->common.copy_align));
990 * xilinx_dma_tx_status - Get DMA transaction status
991 * @dchan: DMA channel
992 * @cookie: Transaction identifier
993 * @txstate: Transaction state
995 * Return: DMA transaction status
997 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
999 struct dma_tx_state *txstate)
1001 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1002 struct xilinx_dma_tx_descriptor *desc;
1003 struct xilinx_axidma_tx_segment *segment;
1004 struct xilinx_axidma_desc_hw *hw;
1005 enum dma_status ret;
1006 unsigned long flags;
1009 ret = dma_cookie_status(dchan, cookie, txstate);
1010 if (ret == DMA_COMPLETE || !txstate)
1013 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1014 spin_lock_irqsave(&chan->lock, flags);
1016 desc = list_last_entry(&chan->active_list,
1017 struct xilinx_dma_tx_descriptor, node);
1019 list_for_each_entry(segment, &desc->segments, node) {
1021 residue += (hw->control - hw->status) &
1022 chan->xdev->max_buffer_len;
1025 spin_unlock_irqrestore(&chan->lock, flags);
1027 chan->residue = residue;
1028 dma_set_residue(txstate, chan->residue);
1035 * xilinx_dma_stop_transfer - Halt DMA channel
1036 * @chan: Driver specific DMA channel
1038 * Return: '0' on success and failure value on error
1040 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
1044 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1046 /* Wait for the hardware to halt */
1047 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1048 val & XILINX_DMA_DMASR_HALTED, 0,
1049 XILINX_DMA_LOOP_COUNT);
1053 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete
1054 * @chan: Driver specific DMA channel
1056 * Return: '0' on success and failure value on error
1058 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
1062 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1063 val & XILINX_DMA_DMASR_IDLE, 0,
1064 XILINX_DMA_LOOP_COUNT);
1068 * xilinx_dma_start - Start DMA channel
1069 * @chan: Driver specific DMA channel
1071 static void xilinx_dma_start(struct xilinx_dma_chan *chan)
1076 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1078 /* Wait for the hardware to start */
1079 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1080 !(val & XILINX_DMA_DMASR_HALTED), 0,
1081 XILINX_DMA_LOOP_COUNT);
1084 dev_err(chan->dev, "Cannot start channel %p: %x\n",
1085 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1092 * xilinx_vdma_start_transfer - Starts VDMA transfer
1093 * @chan: Driver specific channel struct pointer
1095 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
1097 struct xilinx_vdma_config *config = &chan->config;
1098 struct xilinx_dma_tx_descriptor *desc, *tail_desc;
1100 struct xilinx_vdma_tx_segment *segment, *last = NULL;
1103 /* This function was invoked with lock held */
1110 if (list_empty(&chan->pending_list))
1113 desc = list_first_entry(&chan->pending_list,
1114 struct xilinx_dma_tx_descriptor, node);
1115 tail_desc = list_last_entry(&chan->pending_list,
1116 struct xilinx_dma_tx_descriptor, node);
1118 /* Configure the hardware using info in the config structure */
1119 if (chan->has_vflip) {
1120 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);
1121 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP;
1122 reg |= config->vflip_en;
1123 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP,
1127 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1129 if (config->frm_cnt_en)
1130 reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
1132 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
1134 /* If not parking, enable circular mode */
1136 reg &= ~XILINX_DMA_DMACR_CIRC_EN;
1138 reg |= XILINX_DMA_DMACR_CIRC_EN;
1140 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1142 j = chan->desc_submitcount;
1143 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR);
1144 if (chan->direction == DMA_MEM_TO_DEV) {
1145 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK;
1146 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT;
1148 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK;
1149 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT;
1151 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg);
1153 /* Start the hardware */
1154 xilinx_dma_start(chan);
1159 /* Start the transfer */
1160 if (chan->desc_submitcount < chan->num_frms)
1161 i = chan->desc_submitcount;
1163 list_for_each_entry(segment, &desc->segments, node) {
1165 vdma_desc_write_64(chan,
1166 XILINX_VDMA_REG_START_ADDRESS_64(i++),
1167 segment->hw.buf_addr,
1168 segment->hw.buf_addr_msb);
1170 vdma_desc_write(chan,
1171 XILINX_VDMA_REG_START_ADDRESS(i++),
1172 segment->hw.buf_addr);
1180 /* HW expects these parameters to be same for one transaction */
1181 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
1182 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
1184 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
1186 chan->desc_submitcount++;
1187 chan->desc_pendingcount--;
1188 list_del(&desc->node);
1189 list_add_tail(&desc->node, &chan->active_list);
1190 if (chan->desc_submitcount == chan->num_frms)
1191 chan->desc_submitcount = 0;
1197 * xilinx_cdma_start_transfer - Starts cdma transfer
1198 * @chan: Driver specific channel struct pointer
1200 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
1202 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1203 struct xilinx_cdma_tx_segment *tail_segment;
1204 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
1212 if (list_empty(&chan->pending_list))
1215 head_desc = list_first_entry(&chan->pending_list,
1216 struct xilinx_dma_tx_descriptor, node);
1217 tail_desc = list_last_entry(&chan->pending_list,
1218 struct xilinx_dma_tx_descriptor, node);
1219 tail_segment = list_last_entry(&tail_desc->segments,
1220 struct xilinx_cdma_tx_segment, node);
1222 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1223 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1224 ctrl_reg |= chan->desc_pendingcount <<
1225 XILINX_DMA_CR_COALESCE_SHIFT;
1226 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
1230 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
1231 XILINX_CDMA_CR_SGMODE);
1233 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1234 XILINX_CDMA_CR_SGMODE);
1236 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1237 head_desc->async_tx.phys);
1239 /* Update tail ptr register which will start the transfer */
1240 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1241 tail_segment->phys);
1243 /* In simple mode */
1244 struct xilinx_cdma_tx_segment *segment;
1245 struct xilinx_cdma_desc_hw *hw;
1247 segment = list_first_entry(&head_desc->segments,
1248 struct xilinx_cdma_tx_segment,
1253 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
1254 xilinx_prep_dma_addr_t(hw->src_addr));
1255 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
1256 xilinx_prep_dma_addr_t(hw->dest_addr));
1258 /* Start the transfer */
1259 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1260 hw->control & chan->xdev->max_buffer_len);
1263 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1264 chan->desc_pendingcount = 0;
1269 * xilinx_dma_start_transfer - Starts DMA transfer
1270 * @chan: Driver specific channel struct pointer
1272 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
1274 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1275 struct xilinx_axidma_tx_segment *tail_segment;
1281 if (list_empty(&chan->pending_list))
1287 head_desc = list_first_entry(&chan->pending_list,
1288 struct xilinx_dma_tx_descriptor, node);
1289 tail_desc = list_last_entry(&chan->pending_list,
1290 struct xilinx_dma_tx_descriptor, node);
1291 tail_segment = list_last_entry(&tail_desc->segments,
1292 struct xilinx_axidma_tx_segment, node);
1294 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1296 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1297 reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1298 reg |= chan->desc_pendingcount <<
1299 XILINX_DMA_CR_COALESCE_SHIFT;
1300 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1303 if (chan->has_sg && !chan->xdev->mcdma)
1304 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1305 head_desc->async_tx.phys);
1307 if (chan->has_sg && chan->xdev->mcdma) {
1308 if (chan->direction == DMA_MEM_TO_DEV) {
1309 dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1310 head_desc->async_tx.phys);
1313 dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1314 head_desc->async_tx.phys);
1316 dma_ctrl_write(chan,
1317 XILINX_DMA_MCRX_CDESC(chan->tdest),
1318 head_desc->async_tx.phys);
1323 xilinx_dma_start(chan);
1328 /* Start the transfer */
1329 if (chan->has_sg && !chan->xdev->mcdma) {
1331 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1332 chan->cyclic_seg_v->phys);
1334 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1335 tail_segment->phys);
1336 } else if (chan->has_sg && chan->xdev->mcdma) {
1337 if (chan->direction == DMA_MEM_TO_DEV) {
1338 dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1339 tail_segment->phys);
1342 dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1343 tail_segment->phys);
1345 dma_ctrl_write(chan,
1346 XILINX_DMA_MCRX_TDESC(chan->tdest),
1347 tail_segment->phys);
1351 struct xilinx_axidma_tx_segment *segment;
1352 struct xilinx_axidma_desc_hw *hw;
1354 segment = list_first_entry(&head_desc->segments,
1355 struct xilinx_axidma_tx_segment,
1359 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);
1361 /* Start the transfer */
1362 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1363 hw->control & chan->xdev->max_buffer_len);
1366 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1367 chan->desc_pendingcount = 0;
1372 * xilinx_dma_issue_pending - Issue pending transactions
1373 * @dchan: DMA channel
1375 static void xilinx_dma_issue_pending(struct dma_chan *dchan)
1377 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1378 unsigned long flags;
1380 spin_lock_irqsave(&chan->lock, flags);
1381 chan->start_transfer(chan);
1382 spin_unlock_irqrestore(&chan->lock, flags);
1386 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1387 * @chan : xilinx DMA channel
1391 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
1393 struct xilinx_dma_tx_descriptor *desc, *next;
1395 /* This function was invoked with lock held */
1396 if (list_empty(&chan->active_list))
1399 list_for_each_entry_safe(desc, next, &chan->active_list, node) {
1400 list_del(&desc->node);
1402 dma_cookie_complete(&desc->async_tx);
1403 list_add_tail(&desc->node, &chan->done_list);
1408 * xilinx_dma_reset - Reset DMA channel
1409 * @chan: Driver specific DMA channel
1411 * Return: '0' on success and failure value on error
1413 static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
1418 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
1420 /* Wait for the hardware to finish reset */
1421 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
1422 !(tmp & XILINX_DMA_DMACR_RESET), 0,
1423 XILINX_DMA_LOOP_COUNT);
1426 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
1427 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
1428 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1434 chan->desc_submitcount = 0;
1440 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1441 * @chan: Driver specific DMA channel
1443 * Return: '0' on success and failure value on error
1445 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
1450 err = xilinx_dma_reset(chan);
1454 /* Enable interrupts */
1455 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1456 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1462 * xilinx_dma_irq_handler - DMA Interrupt handler
1464 * @data: Pointer to the Xilinx DMA channel structure
1466 * Return: IRQ_HANDLED/IRQ_NONE
1468 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
1470 struct xilinx_dma_chan *chan = data;
1473 /* Read the status and ack the interrupts. */
1474 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
1475 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
1478 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1479 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1481 if (status & XILINX_DMA_DMASR_ERR_IRQ) {
1483 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
1484 * error is recoverable, ignore it. Otherwise flag the error.
1486 * Only recoverable errors can be cleared in the DMASR register,
1487 * make sure not to write to other error bits to 1.
1489 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
1491 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1492 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
1494 if (!chan->flush_on_fsync ||
1495 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
1497 "Channel %p has errors %x, cdr %x tdr %x\n",
1499 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
1500 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
1505 if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
1507 * Device takes too long to do the transfer when user requires
1510 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1513 if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
1514 spin_lock(&chan->lock);
1515 xilinx_dma_complete_descriptor(chan);
1517 chan->start_transfer(chan);
1518 spin_unlock(&chan->lock);
1521 tasklet_schedule(&chan->tasklet);
1526 * append_desc_queue - Queuing descriptor
1527 * @chan: Driver specific dma channel
1528 * @desc: dma transaction descriptor
1530 static void append_desc_queue(struct xilinx_dma_chan *chan,
1531 struct xilinx_dma_tx_descriptor *desc)
1533 struct xilinx_vdma_tx_segment *tail_segment;
1534 struct xilinx_dma_tx_descriptor *tail_desc;
1535 struct xilinx_axidma_tx_segment *axidma_tail_segment;
1536 struct xilinx_cdma_tx_segment *cdma_tail_segment;
1538 if (list_empty(&chan->pending_list))
1542 * Add the hardware descriptor to the chain of hardware descriptors
1543 * that already exists in memory.
1545 tail_desc = list_last_entry(&chan->pending_list,
1546 struct xilinx_dma_tx_descriptor, node);
1547 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
1548 tail_segment = list_last_entry(&tail_desc->segments,
1549 struct xilinx_vdma_tx_segment,
1551 tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1552 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1553 cdma_tail_segment = list_last_entry(&tail_desc->segments,
1554 struct xilinx_cdma_tx_segment,
1556 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1558 axidma_tail_segment = list_last_entry(&tail_desc->segments,
1559 struct xilinx_axidma_tx_segment,
1561 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1565 * Add the software descriptor and all children to the list
1566 * of pending transactions
1569 list_add_tail(&desc->node, &chan->pending_list);
1570 chan->desc_pendingcount++;
1572 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
1573 && unlikely(chan->desc_pendingcount > chan->num_frms)) {
1574 dev_dbg(chan->dev, "desc pendingcount is too high\n");
1575 chan->desc_pendingcount = chan->num_frms;
1580 * xilinx_dma_tx_submit - Submit DMA transaction
1581 * @tx: Async transaction descriptor
1583 * Return: cookie value on success and failure value on error
1585 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
1587 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
1588 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
1589 dma_cookie_t cookie;
1590 unsigned long flags;
1594 xilinx_dma_free_tx_descriptor(chan, desc);
1600 * If reset fails, need to hard reset the system.
1601 * Channel is no longer functional
1603 err = xilinx_dma_chan_reset(chan);
1608 spin_lock_irqsave(&chan->lock, flags);
1610 cookie = dma_cookie_assign(tx);
1612 /* Put this transaction onto the tail of the pending queue */
1613 append_desc_queue(chan, desc);
1616 chan->cyclic = true;
1618 spin_unlock_irqrestore(&chan->lock, flags);
1624 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
1625 * DMA_SLAVE transaction
1626 * @dchan: DMA channel
1627 * @xt: Interleaved template pointer
1628 * @flags: transfer ack flags
1630 * Return: Async transaction descriptor on success and NULL on failure
1632 static struct dma_async_tx_descriptor *
1633 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
1634 struct dma_interleaved_template *xt,
1635 unsigned long flags)
1637 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1638 struct xilinx_dma_tx_descriptor *desc;
1639 struct xilinx_vdma_tx_segment *segment;
1640 struct xilinx_vdma_desc_hw *hw;
1642 if (!is_slave_direction(xt->dir))
1645 if (!xt->numf || !xt->sgl[0].size)
1648 if (xt->frame_size != 1)
1651 /* Allocate a transaction descriptor. */
1652 desc = xilinx_dma_alloc_tx_descriptor(chan);
1656 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1657 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1658 async_tx_ack(&desc->async_tx);
1660 /* Allocate the link descriptor from DMA pool */
1661 segment = xilinx_vdma_alloc_tx_segment(chan);
1665 /* Fill in the hardware descriptor */
1667 hw->vsize = xt->numf;
1668 hw->hsize = xt->sgl[0].size;
1669 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
1670 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
1671 hw->stride |= chan->config.frm_dly <<
1672 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
1674 if (xt->dir != DMA_MEM_TO_DEV) {
1675 if (chan->ext_addr) {
1676 hw->buf_addr = lower_32_bits(xt->dst_start);
1677 hw->buf_addr_msb = upper_32_bits(xt->dst_start);
1679 hw->buf_addr = xt->dst_start;
1682 if (chan->ext_addr) {
1683 hw->buf_addr = lower_32_bits(xt->src_start);
1684 hw->buf_addr_msb = upper_32_bits(xt->src_start);
1686 hw->buf_addr = xt->src_start;
1690 /* Insert the segment into the descriptor segments list. */
1691 list_add_tail(&segment->node, &desc->segments);
1693 /* Link the last hardware descriptor with the first. */
1694 segment = list_first_entry(&desc->segments,
1695 struct xilinx_vdma_tx_segment, node);
1696 desc->async_tx.phys = segment->phys;
1698 return &desc->async_tx;
1701 xilinx_dma_free_tx_descriptor(chan, desc);
1706 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
1707 * @dchan: DMA channel
1708 * @dma_dst: destination address
1709 * @dma_src: source address
1710 * @len: transfer length
1711 * @flags: transfer ack flags
1713 * Return: Async transaction descriptor on success and NULL on failure
1715 static struct dma_async_tx_descriptor *
1716 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
1717 dma_addr_t dma_src, size_t len, unsigned long flags)
1719 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1720 struct xilinx_dma_tx_descriptor *desc;
1721 struct xilinx_cdma_tx_segment *segment;
1722 struct xilinx_cdma_desc_hw *hw;
1724 if (!len || len > chan->xdev->max_buffer_len)
1727 desc = xilinx_dma_alloc_tx_descriptor(chan);
1731 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1732 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1734 /* Allocate the link descriptor from DMA pool */
1735 segment = xilinx_cdma_alloc_tx_segment(chan);
1741 hw->src_addr = dma_src;
1742 hw->dest_addr = dma_dst;
1743 if (chan->ext_addr) {
1744 hw->src_addr_msb = upper_32_bits(dma_src);
1745 hw->dest_addr_msb = upper_32_bits(dma_dst);
1748 /* Insert the segment into the descriptor segments list. */
1749 list_add_tail(&segment->node, &desc->segments);
1751 desc->async_tx.phys = segment->phys;
1752 hw->next_desc = segment->phys;
1754 return &desc->async_tx;
1757 xilinx_dma_free_tx_descriptor(chan, desc);
1762 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
1763 * @dchan: DMA channel
1764 * @sgl: scatterlist to transfer to/from
1765 * @sg_len: number of entries in @scatterlist
1766 * @direction: DMA direction
1767 * @flags: transfer ack flags
1768 * @context: APP words of the descriptor
1770 * Return: Async transaction descriptor on success and NULL on failure
1772 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
1773 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
1774 enum dma_transfer_direction direction, unsigned long flags,
1777 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1778 struct xilinx_dma_tx_descriptor *desc;
1779 struct xilinx_axidma_tx_segment *segment = NULL;
1780 u32 *app_w = (u32 *)context;
1781 struct scatterlist *sg;
1786 if (!is_slave_direction(direction))
1789 /* Allocate a transaction descriptor. */
1790 desc = xilinx_dma_alloc_tx_descriptor(chan);
1794 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1795 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1797 /* Build transactions using information in the scatter gather list */
1798 for_each_sg(sgl, sg, sg_len, i) {
1801 /* Loop until the entire scatterlist entry is used */
1802 while (sg_used < sg_dma_len(sg)) {
1803 struct xilinx_axidma_desc_hw *hw;
1805 /* Get a free segment */
1806 segment = xilinx_axidma_alloc_tx_segment(chan);
1811 * Calculate the maximum number of bytes to transfer,
1812 * making sure it is less than the hw limit
1814 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg),
1818 /* Fill in the descriptor */
1819 xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
1824 if (chan->direction == DMA_MEM_TO_DEV) {
1826 memcpy(hw->app, app_w, sizeof(u32) *
1827 XILINX_DMA_NUM_APP_WORDS);
1833 * Insert the segment into the descriptor segments
1836 list_add_tail(&segment->node, &desc->segments);
1840 segment = list_first_entry(&desc->segments,
1841 struct xilinx_axidma_tx_segment, node);
1842 desc->async_tx.phys = segment->phys;
1844 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
1845 if (chan->direction == DMA_MEM_TO_DEV) {
1846 segment->hw.control |= XILINX_DMA_BD_SOP;
1847 segment = list_last_entry(&desc->segments,
1848 struct xilinx_axidma_tx_segment,
1850 segment->hw.control |= XILINX_DMA_BD_EOP;
1853 return &desc->async_tx;
1856 xilinx_dma_free_tx_descriptor(chan, desc);
1861 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
1862 * @dchan: DMA channel
1863 * @buf_addr: Physical address of the buffer
1864 * @buf_len: Total length of the cyclic buffers
1865 * @period_len: length of individual cyclic buffer
1866 * @direction: DMA direction
1867 * @flags: transfer ack flags
1869 * Return: Async transaction descriptor on success and NULL on failure
1871 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
1872 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
1873 size_t period_len, enum dma_transfer_direction direction,
1874 unsigned long flags)
1876 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1877 struct xilinx_dma_tx_descriptor *desc;
1878 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;
1879 size_t copy, sg_used;
1880 unsigned int num_periods;
1887 num_periods = buf_len / period_len;
1892 if (!is_slave_direction(direction))
1895 /* Allocate a transaction descriptor. */
1896 desc = xilinx_dma_alloc_tx_descriptor(chan);
1900 chan->direction = direction;
1901 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1902 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1904 for (i = 0; i < num_periods; ++i) {
1907 while (sg_used < period_len) {
1908 struct xilinx_axidma_desc_hw *hw;
1910 /* Get a free segment */
1911 segment = xilinx_axidma_alloc_tx_segment(chan);
1916 * Calculate the maximum number of bytes to transfer,
1917 * making sure it is less than the hw limit
1919 copy = xilinx_dma_calc_copysize(chan, period_len,
1922 xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
1927 prev->hw.next_desc = segment->phys;
1933 * Insert the segment into the descriptor segments
1936 list_add_tail(&segment->node, &desc->segments);
1940 head_segment = list_first_entry(&desc->segments,
1941 struct xilinx_axidma_tx_segment, node);
1942 desc->async_tx.phys = head_segment->phys;
1944 desc->cyclic = true;
1945 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1946 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
1947 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1949 segment = list_last_entry(&desc->segments,
1950 struct xilinx_axidma_tx_segment,
1952 segment->hw.next_desc = (u32) head_segment->phys;
1954 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
1955 if (direction == DMA_MEM_TO_DEV) {
1956 head_segment->hw.control |= XILINX_DMA_BD_SOP;
1957 segment->hw.control |= XILINX_DMA_BD_EOP;
1960 return &desc->async_tx;
1963 xilinx_dma_free_tx_descriptor(chan, desc);
1968 * xilinx_dma_prep_interleaved - prepare a descriptor for a
1969 * DMA_SLAVE transaction
1970 * @dchan: DMA channel
1971 * @xt: Interleaved template pointer
1972 * @flags: transfer ack flags
1974 * Return: Async transaction descriptor on success and NULL on failure
1976 static struct dma_async_tx_descriptor *
1977 xilinx_dma_prep_interleaved(struct dma_chan *dchan,
1978 struct dma_interleaved_template *xt,
1979 unsigned long flags)
1981 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1982 struct xilinx_dma_tx_descriptor *desc;
1983 struct xilinx_axidma_tx_segment *segment;
1984 struct xilinx_axidma_desc_hw *hw;
1986 if (!is_slave_direction(xt->dir))
1989 if (!xt->numf || !xt->sgl[0].size)
1992 if (xt->frame_size != 1)
1995 /* Allocate a transaction descriptor. */
1996 desc = xilinx_dma_alloc_tx_descriptor(chan);
2000 chan->direction = xt->dir;
2001 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2002 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2004 /* Get a free segment */
2005 segment = xilinx_axidma_alloc_tx_segment(chan);
2011 /* Fill in the descriptor */
2012 if (xt->dir != DMA_MEM_TO_DEV)
2013 hw->buf_addr = xt->dst_start;
2015 hw->buf_addr = xt->src_start;
2017 hw->mcdma_control = chan->tdest & XILINX_DMA_BD_TDEST_MASK;
2018 hw->vsize_stride = (xt->numf << XILINX_DMA_BD_VSIZE_SHIFT) &
2019 XILINX_DMA_BD_VSIZE_MASK;
2020 hw->vsize_stride |= (xt->sgl[0].icg + xt->sgl[0].size) &
2021 XILINX_DMA_BD_STRIDE_MASK;
2022 hw->control = xt->sgl[0].size & XILINX_DMA_BD_HSIZE_MASK;
2025 * Insert the segment into the descriptor segments
2028 list_add_tail(&segment->node, &desc->segments);
2031 segment = list_first_entry(&desc->segments,
2032 struct xilinx_axidma_tx_segment, node);
2033 desc->async_tx.phys = segment->phys;
2035 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2036 if (xt->dir == DMA_MEM_TO_DEV) {
2037 segment->hw.control |= XILINX_DMA_BD_SOP;
2038 segment = list_last_entry(&desc->segments,
2039 struct xilinx_axidma_tx_segment,
2041 segment->hw.control |= XILINX_DMA_BD_EOP;
2044 return &desc->async_tx;
2047 xilinx_dma_free_tx_descriptor(chan, desc);
2052 * xilinx_dma_terminate_all - Halt the channel and free descriptors
2053 * @dchan: Driver specific DMA Channel pointer
2055 * Return: '0' always.
2057 static int xilinx_dma_terminate_all(struct dma_chan *dchan)
2059 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2064 xilinx_dma_chan_reset(chan);
2066 err = chan->stop_transfer(chan);
2068 dev_err(chan->dev, "Cannot stop channel %p: %x\n",
2069 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
2073 /* Remove and free all of the descriptors in the lists */
2074 xilinx_dma_free_descriptors(chan);
2078 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2079 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2080 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2081 chan->cyclic = false;
2084 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
2085 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2086 XILINX_CDMA_CR_SGMODE);
2092 * xilinx_dma_channel_set_config - Configure VDMA channel
2093 * Run-time configuration for Axi VDMA, supports:
2094 * . halt the channel
2095 * . configure interrupt coalescing and inter-packet delay threshold
2096 * . start/stop parking
2099 * @dchan: DMA channel
2100 * @cfg: VDMA device configuration pointer
2102 * Return: '0' on success and failure value on error
2104 int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
2105 struct xilinx_vdma_config *cfg)
2107 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2111 return xilinx_dma_chan_reset(chan);
2113 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2115 chan->config.frm_dly = cfg->frm_dly;
2116 chan->config.park = cfg->park;
2118 /* genlock settings */
2119 chan->config.gen_lock = cfg->gen_lock;
2120 chan->config.master = cfg->master;
2122 if (cfg->gen_lock && chan->genlock) {
2123 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
2124 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
2127 chan->config.frm_cnt_en = cfg->frm_cnt_en;
2128 chan->config.vflip_en = cfg->vflip_en;
2131 chan->config.park_frm = cfg->park_frm;
2133 chan->config.park_frm = -1;
2135 chan->config.coalesc = cfg->coalesc;
2136 chan->config.delay = cfg->delay;
2138 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
2139 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
2140 chan->config.coalesc = cfg->coalesc;
2143 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
2144 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
2145 chan->config.delay = cfg->delay;
2148 /* FSync Source selection */
2149 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
2150 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
2152 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
2156 EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
2158 /* -----------------------------------------------------------------------------
2163 * xilinx_dma_chan_remove - Per Channel remove function
2164 * @chan: Driver specific DMA channel
2166 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
2168 /* Disable all interrupts */
2169 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2170 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
2173 free_irq(chan->irq, chan);
2175 tasklet_kill(&chan->tasklet);
2177 list_del(&chan->common.device_node);
2180 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2181 struct clk **tx_clk, struct clk **rx_clk,
2182 struct clk **sg_clk, struct clk **tmp_clk)
2188 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2189 if (IS_ERR(*axi_clk)) {
2190 err = PTR_ERR(*axi_clk);
2191 dev_err(&pdev->dev, "failed to get axi_aclk (%d)\n", err);
2195 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2196 if (IS_ERR(*tx_clk))
2199 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2200 if (IS_ERR(*rx_clk))
2203 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk");
2204 if (IS_ERR(*sg_clk))
2207 err = clk_prepare_enable(*axi_clk);
2209 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2213 err = clk_prepare_enable(*tx_clk);
2215 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2216 goto err_disable_axiclk;
2219 err = clk_prepare_enable(*rx_clk);
2221 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2222 goto err_disable_txclk;
2225 err = clk_prepare_enable(*sg_clk);
2227 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err);
2228 goto err_disable_rxclk;
2234 clk_disable_unprepare(*rx_clk);
2236 clk_disable_unprepare(*tx_clk);
2238 clk_disable_unprepare(*axi_clk);
2243 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2244 struct clk **dev_clk, struct clk **tmp_clk,
2245 struct clk **tmp1_clk, struct clk **tmp2_clk)
2253 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2254 if (IS_ERR(*axi_clk)) {
2255 err = PTR_ERR(*axi_clk);
2256 dev_err(&pdev->dev, "failed to get axi_clk (%d)\n", err);
2260 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk");
2261 if (IS_ERR(*dev_clk)) {
2262 err = PTR_ERR(*dev_clk);
2263 dev_err(&pdev->dev, "failed to get dev_clk (%d)\n", err);
2267 err = clk_prepare_enable(*axi_clk);
2269 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2273 err = clk_prepare_enable(*dev_clk);
2275 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err);
2276 goto err_disable_axiclk;
2282 clk_disable_unprepare(*axi_clk);
2287 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2288 struct clk **tx_clk, struct clk **txs_clk,
2289 struct clk **rx_clk, struct clk **rxs_clk)
2293 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2294 if (IS_ERR(*axi_clk)) {
2295 err = PTR_ERR(*axi_clk);
2296 dev_err(&pdev->dev, "failed to get axi_aclk (%d)\n", err);
2300 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2301 if (IS_ERR(*tx_clk))
2304 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk");
2305 if (IS_ERR(*txs_clk))
2308 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2309 if (IS_ERR(*rx_clk))
2312 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk");
2313 if (IS_ERR(*rxs_clk))
2316 err = clk_prepare_enable(*axi_clk);
2318 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2322 err = clk_prepare_enable(*tx_clk);
2324 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2325 goto err_disable_axiclk;
2328 err = clk_prepare_enable(*txs_clk);
2330 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err);
2331 goto err_disable_txclk;
2334 err = clk_prepare_enable(*rx_clk);
2336 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2337 goto err_disable_txsclk;
2340 err = clk_prepare_enable(*rxs_clk);
2342 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err);
2343 goto err_disable_rxclk;
2349 clk_disable_unprepare(*rx_clk);
2351 clk_disable_unprepare(*txs_clk);
2353 clk_disable_unprepare(*tx_clk);
2355 clk_disable_unprepare(*axi_clk);
2360 static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
2362 clk_disable_unprepare(xdev->rxs_clk);
2363 clk_disable_unprepare(xdev->rx_clk);
2364 clk_disable_unprepare(xdev->txs_clk);
2365 clk_disable_unprepare(xdev->tx_clk);
2366 clk_disable_unprepare(xdev->axi_clk);
2370 * xilinx_dma_chan_probe - Per Channel Probing
2371 * It get channel features from the device tree entry and
2372 * initialize special channel handling routines
2374 * @xdev: Driver specific device structure
2375 * @node: Device node
2376 * @chan_id: DMA Channel id
2378 * Return: '0' on success and failure value on error
2380 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
2381 struct device_node *node, int chan_id)
2383 struct xilinx_dma_chan *chan;
2384 bool has_dre = false;
2388 /* Allocate and initialize the channel structure */
2389 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
2393 chan->dev = xdev->dev;
2395 chan->desc_pendingcount = 0x0;
2396 chan->ext_addr = xdev->ext_addr;
2397 /* This variable ensures that descriptors are not
2398 * Submitted when dma engine is in progress. This variable is
2399 * Added to avoid polling for a bit in the status register to
2400 * Know dma state in the driver hot path.
2404 spin_lock_init(&chan->lock);
2405 INIT_LIST_HEAD(&chan->pending_list);
2406 INIT_LIST_HEAD(&chan->done_list);
2407 INIT_LIST_HEAD(&chan->active_list);
2408 INIT_LIST_HEAD(&chan->free_seg_list);
2410 /* Retrieve the channel properties from the device tree */
2411 has_dre = of_property_read_bool(node, "xlnx,include-dre");
2413 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
2415 err = of_property_read_u32(node, "xlnx,datawidth", &value);
2417 dev_err(xdev->dev, "missing xlnx,datawidth property\n");
2420 width = value >> 3; /* Convert bits to bytes */
2422 /* If data width is greater than 8 bytes, DRE is not in hw */
2427 xdev->common.copy_align = fls(width - 1);
2429 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
2430 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
2431 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
2432 chan->direction = DMA_MEM_TO_DEV;
2434 chan->tdest = chan_id;
2436 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
2437 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2438 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
2439 chan->config.park = 1;
2441 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2442 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
2443 chan->flush_on_fsync = true;
2445 } else if (of_device_is_compatible(node,
2446 "xlnx,axi-vdma-s2mm-channel") ||
2447 of_device_is_compatible(node,
2448 "xlnx,axi-dma-s2mm-channel")) {
2449 chan->direction = DMA_DEV_TO_MEM;
2451 chan->tdest = chan_id - xdev->nr_channels;
2452 chan->has_vflip = of_property_read_bool(node,
2453 "xlnx,enable-vert-flip");
2454 if (chan->has_vflip) {
2455 chan->config.vflip_en = dma_read(chan,
2456 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) &
2457 XILINX_VDMA_ENABLE_VERTICAL_FLIP;
2460 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
2461 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2462 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
2463 chan->config.park = 1;
2465 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2466 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
2467 chan->flush_on_fsync = true;
2470 dev_err(xdev->dev, "Invalid channel compatible node\n");
2474 /* Request the interrupt */
2475 chan->irq = irq_of_parse_and_map(node, 0);
2476 err = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED,
2477 "xilinx-dma-controller", chan);
2479 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
2483 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2484 chan->start_transfer = xilinx_dma_start_transfer;
2485 chan->stop_transfer = xilinx_dma_stop_transfer;
2486 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2487 chan->start_transfer = xilinx_cdma_start_transfer;
2488 chan->stop_transfer = xilinx_cdma_stop_transfer;
2490 chan->start_transfer = xilinx_vdma_start_transfer;
2491 chan->stop_transfer = xilinx_dma_stop_transfer;
2494 /* check if SG is enabled (only for AXIDMA and CDMA) */
2495 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) {
2496 if (dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
2497 XILINX_DMA_DMASR_SG_MASK)
2498 chan->has_sg = true;
2499 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id,
2500 chan->has_sg ? "enabled" : "disabled");
2503 /* Initialize the tasklet */
2504 tasklet_init(&chan->tasklet, xilinx_dma_do_tasklet,
2505 (unsigned long)chan);
2508 * Initialize the DMA channel and add it to the DMA engine channels
2511 chan->common.device = &xdev->common;
2513 list_add_tail(&chan->common.device_node, &xdev->common.channels);
2514 xdev->chan[chan->id] = chan;
2516 /* Reset the channel */
2517 err = xilinx_dma_chan_reset(chan);
2519 dev_err(xdev->dev, "Reset channel failed\n");
2527 * xilinx_dma_child_probe - Per child node probe
2528 * It get number of dma-channels per child node from
2529 * device-tree and initializes all the channels.
2531 * @xdev: Driver specific device structure
2532 * @node: Device node
2536 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
2537 struct device_node *node)
2539 int ret, i, nr_channels = 1;
2541 ret = of_property_read_u32(node, "dma-channels", &nr_channels);
2542 if ((ret < 0) && xdev->mcdma)
2543 dev_warn(xdev->dev, "missing dma-channels property\n");
2545 for (i = 0; i < nr_channels; i++)
2546 xilinx_dma_chan_probe(xdev, node, xdev->chan_id++);
2548 xdev->nr_channels += nr_channels;
2554 * of_dma_xilinx_xlate - Translation function
2555 * @dma_spec: Pointer to DMA specifier as found in the device tree
2556 * @ofdma: Pointer to DMA controller data
2558 * Return: DMA channel pointer on success and NULL on error
2560 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
2561 struct of_dma *ofdma)
2563 struct xilinx_dma_device *xdev = ofdma->of_dma_data;
2564 int chan_id = dma_spec->args[0];
2566 if (chan_id >= xdev->nr_channels || !xdev->chan[chan_id])
2569 return dma_get_slave_channel(&xdev->chan[chan_id]->common);
2572 static const struct xilinx_dma_config axidma_config = {
2573 .dmatype = XDMA_TYPE_AXIDMA,
2574 .clk_init = axidma_clk_init,
2577 static const struct xilinx_dma_config axicdma_config = {
2578 .dmatype = XDMA_TYPE_CDMA,
2579 .clk_init = axicdma_clk_init,
2582 static const struct xilinx_dma_config axivdma_config = {
2583 .dmatype = XDMA_TYPE_VDMA,
2584 .clk_init = axivdma_clk_init,
2587 static const struct of_device_id xilinx_dma_of_ids[] = {
2588 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
2589 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
2590 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
2593 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
2596 * xilinx_dma_probe - Driver probe function
2597 * @pdev: Pointer to the platform_device structure
2599 * Return: '0' on success and failure value on error
2601 static int xilinx_dma_probe(struct platform_device *pdev)
2603 int (*clk_init)(struct platform_device *, struct clk **, struct clk **,
2604 struct clk **, struct clk **, struct clk **)
2606 struct device_node *node = pdev->dev.of_node;
2607 struct xilinx_dma_device *xdev;
2608 struct device_node *child, *np = pdev->dev.of_node;
2609 struct resource *io;
2610 u32 num_frames, addr_width, len_width;
2613 /* Allocate and initialize the DMA engine structure */
2614 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
2618 xdev->dev = &pdev->dev;
2620 const struct of_device_id *match;
2622 match = of_match_node(xilinx_dma_of_ids, np);
2623 if (match && match->data) {
2624 xdev->dma_config = match->data;
2625 clk_init = xdev->dma_config->clk_init;
2629 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,
2630 &xdev->rx_clk, &xdev->rxs_clk);
2634 /* Request and map I/O memory */
2635 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2636 xdev->regs = devm_ioremap_resource(&pdev->dev, io);
2637 if (IS_ERR(xdev->regs))
2638 return PTR_ERR(xdev->regs);
2640 /* Retrieve the DMA engine properties from the device tree */
2641 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
2643 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2644 xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma");
2645 if (!of_property_read_u32(node, "xlnx,sg-length-width",
2647 if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
2648 len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {
2650 "invalid xlnx,sg-length-width property value. Using default width\n");
2652 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)
2653 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n");
2654 xdev->max_buffer_len =
2655 GENMASK(len_width - 1, 0);
2660 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2661 err = of_property_read_u32(node, "xlnx,num-fstores",
2665 "missing xlnx,num-fstores property\n");
2669 err = of_property_read_u32(node, "xlnx,flush-fsync",
2670 &xdev->flush_on_fsync);
2673 "missing xlnx,flush-fsync property\n");
2676 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
2678 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n");
2680 if (addr_width > 32)
2681 xdev->ext_addr = true;
2683 xdev->ext_addr = false;
2685 /* Set the dma mask bits */
2686 dma_set_mask(xdev->dev, DMA_BIT_MASK(addr_width));
2688 /* Initialize the DMA engine */
2689 xdev->common.dev = &pdev->dev;
2691 INIT_LIST_HEAD(&xdev->common.channels);
2692 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
2693 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
2694 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
2697 xdev->common.device_alloc_chan_resources =
2698 xilinx_dma_alloc_chan_resources;
2699 xdev->common.device_free_chan_resources =
2700 xilinx_dma_free_chan_resources;
2701 xdev->common.device_terminate_all = xilinx_dma_terminate_all;
2702 xdev->common.device_tx_status = xilinx_dma_tx_status;
2703 xdev->common.device_issue_pending = xilinx_dma_issue_pending;
2704 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2705 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
2706 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
2707 xdev->common.device_prep_dma_cyclic =
2708 xilinx_dma_prep_dma_cyclic;
2709 xdev->common.device_prep_interleaved_dma =
2710 xilinx_dma_prep_interleaved;
2711 /* Residue calculation is supported by only AXI DMA */
2712 xdev->common.residue_granularity =
2713 DMA_RESIDUE_GRANULARITY_SEGMENT;
2714 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2715 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
2716 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
2718 xdev->common.device_prep_interleaved_dma =
2719 xilinx_vdma_dma_prep_interleaved;
2722 platform_set_drvdata(pdev, xdev);
2724 /* Initialize the channels */
2725 for_each_child_of_node(node, child) {
2726 err = xilinx_dma_child_probe(xdev, child);
2731 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2732 for (i = 0; i < xdev->nr_channels; i++)
2734 xdev->chan[i]->num_frms = num_frames;
2737 /* Register the DMA engine with the core */
2738 dma_async_device_register(&xdev->common);
2740 err = of_dma_controller_register(node, of_dma_xilinx_xlate,
2743 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
2744 dma_async_device_unregister(&xdev->common);
2748 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
2749 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n");
2750 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)
2751 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n");
2753 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");
2758 xdma_disable_allclks(xdev);
2760 for (i = 0; i < xdev->nr_channels; i++)
2762 xilinx_dma_chan_remove(xdev->chan[i]);
2768 * xilinx_dma_remove - Driver remove function
2769 * @pdev: Pointer to the platform_device structure
2771 * Return: Always '0'
2773 static int xilinx_dma_remove(struct platform_device *pdev)
2775 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
2778 of_dma_controller_free(pdev->dev.of_node);
2780 dma_async_device_unregister(&xdev->common);
2782 for (i = 0; i < xdev->nr_channels; i++)
2784 xilinx_dma_chan_remove(xdev->chan[i]);
2786 xdma_disable_allclks(xdev);
2791 static struct platform_driver xilinx_vdma_driver = {
2793 .name = "xilinx-vdma",
2794 .of_match_table = xilinx_dma_of_ids,
2796 .probe = xilinx_dma_probe,
2797 .remove = xilinx_dma_remove,
2800 module_platform_driver(xilinx_vdma_driver);
2802 MODULE_AUTHOR("Xilinx, Inc.");
2803 MODULE_DESCRIPTION("Xilinx VDMA driver");
2804 MODULE_LICENSE("GPL v2");