drivers/dma/sun6i-dma.c

   1 /*
   2  * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd
   3  * Author: Sugar <shuge@allwinnertech.com>
   4  *
   5  * Copyright (C) 2014 Maxime Ripard
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/of_dma.h>
  21 #include <linux/of_device.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/reset.h>
  24 #include <linux/slab.h>
  25 #include <linux/types.h>
  26
  27 #include "virt-dma.h"
  28
  29 /*
  30  * Common registers
  31  */
  32 #define DMA_IRQ_EN(x)           ((x) * 0x04)
  33 #define DMA_IRQ_HALF                    BIT(0)
  34 #define DMA_IRQ_PKG                     BIT(1)
  35 #define DMA_IRQ_QUEUE                   BIT(2)
  36
  37 #define DMA_IRQ_CHAN_NR                 8
  38 #define DMA_IRQ_CHAN_WIDTH              4
  39
  40
  41 #define DMA_IRQ_STAT(x)         ((x) * 0x04 + 0x10)
  42
  43 #define DMA_STAT                0x30
  44
  45 /*
  46  * sun8i specific registers
  47  */
  48 #define SUN8I_DMA_GATE          0x20
  49 #define SUN8I_DMA_GATE_ENABLE   0x4
  50
  51 #define SUNXI_H3_SECURE_REG             0x20
  52 #define SUNXI_H3_DMA_GATE               0x28
  53 #define SUNXI_H3_DMA_GATE_ENABLE        0x4
  54 /*
  55  * Channels specific registers
  56  */
  57 #define DMA_CHAN_ENABLE         0x00
  58 #define DMA_CHAN_ENABLE_START           BIT(0)
  59 #define DMA_CHAN_ENABLE_STOP            0
  60
  61 #define DMA_CHAN_PAUSE          0x04
  62 #define DMA_CHAN_PAUSE_PAUSE            BIT(1)
  63 #define DMA_CHAN_PAUSE_RESUME           0
  64
  65 #define DMA_CHAN_LLI_ADDR       0x08
  66
  67 #define DMA_CHAN_CUR_CFG        0x0c
  68 #define DMA_CHAN_CFG_SRC_DRQ(x)         ((x) & 0x1f)
  69 #define DMA_CHAN_CFG_SRC_IO_MODE        BIT(5)
  70 #define DMA_CHAN_CFG_SRC_LINEAR_MODE    (0 << 5)
  71 #define DMA_CHAN_CFG_SRC_BURST_A31(x)   (((x) & 0x3) << 7)
  72 #define DMA_CHAN_CFG_SRC_BURST_H3(x)    (((x) & 0x3) << 6)
  73 #define DMA_CHAN_CFG_SRC_WIDTH(x)       (((x) & 0x3) << 9)
  74
  75 #define DMA_CHAN_CFG_DST_DRQ(x)         (DMA_CHAN_CFG_SRC_DRQ(x) << 16)
  76 #define DMA_CHAN_CFG_DST_IO_MODE        (DMA_CHAN_CFG_SRC_IO_MODE << 16)
  77 #define DMA_CHAN_CFG_DST_LINEAR_MODE    (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)
  78 #define DMA_CHAN_CFG_DST_BURST_A31(x)   (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
  79 #define DMA_CHAN_CFG_DST_BURST_H3(x)    (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
  80 #define DMA_CHAN_CFG_DST_WIDTH(x)       (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
  81
  82 #define DMA_CHAN_CUR_SRC        0x10
  83
  84 #define DMA_CHAN_CUR_DST        0x14
  85
  86 #define DMA_CHAN_CUR_CNT        0x18
  87
  88 #define DMA_CHAN_CUR_PARA       0x1c
  89
  90
  91 /*
  92  * Various hardware related defines
  93  */
  94 #define LLI_LAST_ITEM   0xfffff800
  95 #define NORMAL_WAIT     8
  96 #define DRQ_SDRAM       1
  97
  98 /* forward declaration */
  99 struct sun6i_dma_dev;
 100
 101 /*
 102  * Hardware channels / ports representation
 103  *
 104  * The hardware is used in several SoCs, with differing numbers
 105  * of channels and endpoints. This structure ties those numbers
 106  * to a certain compatible string.
 107  */
 108 struct sun6i_dma_config {
 109         u32 nr_max_channels;
 110         u32 nr_max_requests;
 111         u32 nr_max_vchans;
 112         /*
 113          * In the datasheets/user manuals of newer Allwinner SoCs, a special
 114          * bit (bit 2 at register 0x20) is present.
 115          * It's named "DMA MCLK interface circuit auto gating bit" in the
 116          * documents, and the footnote of this register says that this bit
 117          * should be set up when initializing the DMA controller.
 118          * Allwinner A23/A33 user manuals do not have this bit documented,
 119          * however these SoCs really have and need this bit, as seen in the
 120          * BSP kernel source code.
 121          */
 122         void (*clock_autogate_enable)(struct sun6i_dma_dev *);
 123         void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst);
 124 };
 125
 126 /*
 127  * Hardware representation of the LLI
 128  *
 129  * The hardware will be fed the physical address of this structure,
 130  * and read its content in order to start the transfer.
 131  */
 132 struct sun6i_dma_lli {
 133         u32                     cfg;
 134         u32                     src;
 135         u32                     dst;
 136         u32                     len;
 137         u32                     para;
 138         u32                     p_lli_next;
 139
 140         /*
 141          * This field is not used by the DMA controller, but will be
 142          * used by the CPU to go through the list (mostly for dumping
 143          * or freeing it).
 144          */
 145         struct sun6i_dma_lli    *v_lli_next;
 146 };
 147
 148
 149 struct sun6i_desc {
 150         struct virt_dma_desc    vd;
 151         dma_addr_t              p_lli;
 152         struct sun6i_dma_lli    *v_lli;
 153 };
 154
 155 struct sun6i_pchan {
 156         u32                     idx;
 157         void __iomem            *base;
 158         struct sun6i_vchan      *vchan;
 159         struct sun6i_desc       *desc;
 160         struct sun6i_desc       *done;
 161 };
 162
 163 struct sun6i_vchan {
 164         struct virt_dma_chan    vc;
 165         struct list_head        node;
 166         struct dma_slave_config cfg;
 167         struct sun6i_pchan      *phy;
 168         u8                      port;
 169         u8                      irq_type;
 170         bool                    cyclic;
 171 };
 172
 173 struct sun6i_dma_dev {
 174         struct dma_device       slave;
 175         void __iomem            *base;
 176         struct clk              *clk;
 177         int                     irq;
 178         spinlock_t              lock;
 179         struct reset_control    *rstc;
 180         struct tasklet_struct   task;
 181         atomic_t                tasklet_shutdown;
 182         struct list_head        pending;
 183         struct dma_pool         *pool;
 184         struct sun6i_pchan      *pchans;
 185         struct sun6i_vchan      *vchans;
 186         const struct sun6i_dma_config *cfg;
 187 };
 188
 189 static struct device *chan2dev(struct dma_chan *chan)
 190 {
 191         return &chan->dev->device;
 192 }
 193
 194 static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d)
 195 {
 196         return container_of(d, struct sun6i_dma_dev, slave);
 197 }
 198
 199 static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan)
 200 {
 201         return container_of(chan, struct sun6i_vchan, vc.chan);
 202 }
 203
 204 static inline struct sun6i_desc *
 205 to_sun6i_desc(struct dma_async_tx_descriptor *tx)
 206 {
 207         return container_of(tx, struct sun6i_desc, vd.tx);
 208 }
 209
 210 static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev)
 211 {
 212         dev_dbg(sdev->slave.dev, "Common register:\n"
 213                 "\tmask0(%04x): 0x%08x\n"
 214                 "\tmask1(%04x): 0x%08x\n"
 215                 "\tpend0(%04x): 0x%08x\n"
 216                 "\tpend1(%04x): 0x%08x\n"
 217                 "\tstats(%04x): 0x%08x\n",
 218                 DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)),
 219                 DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)),
 220                 DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)),
 221                 DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)),
 222                 DMA_STAT, readl(sdev->base + DMA_STAT));
 223 }
 224
 225 static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev,
 226                                             struct sun6i_pchan *pchan)
 227 {
 228         phys_addr_t reg = virt_to_phys(pchan->base);
 229
 230         dev_dbg(sdev->slave.dev, "Chan %d reg: %pa\n"
 231                 "\t___en(%04x): \t0x%08x\n"
 232                 "\tpause(%04x): \t0x%08x\n"
 233                 "\tstart(%04x): \t0x%08x\n"
 234                 "\t__cfg(%04x): \t0x%08x\n"
 235                 "\t__src(%04x): \t0x%08x\n"
 236                 "\t__dst(%04x): \t0x%08x\n"
 237                 "\tcount(%04x): \t0x%08x\n"
 238                 "\t_para(%04x): \t0x%08x\n\n",
 239                 pchan->idx, &reg,
 240                 DMA_CHAN_ENABLE,
 241                 readl(pchan->base + DMA_CHAN_ENABLE),
 242                 DMA_CHAN_PAUSE,
 243                 readl(pchan->base + DMA_CHAN_PAUSE),
 244                 DMA_CHAN_LLI_ADDR,
 245                 readl(pchan->base + DMA_CHAN_LLI_ADDR),
 246                 DMA_CHAN_CUR_CFG,
 247                 readl(pchan->base + DMA_CHAN_CUR_CFG),
 248                 DMA_CHAN_CUR_SRC,
 249                 readl(pchan->base + DMA_CHAN_CUR_SRC),
 250                 DMA_CHAN_CUR_DST,
 251                 readl(pchan->base + DMA_CHAN_CUR_DST),
 252                 DMA_CHAN_CUR_CNT,
 253                 readl(pchan->base + DMA_CHAN_CUR_CNT),
 254                 DMA_CHAN_CUR_PARA,
 255                 readl(pchan->base + DMA_CHAN_CUR_PARA));
 256 }
 257
 258 static inline s8 convert_burst(u32 maxburst)
 259 {
 260         switch (maxburst) {
 261         case 1:
 262                 return 0;
 263         case 8:
 264                 return 2;
 265         default:
 266                 return -EINVAL;
 267         }
 268 }
 269
 270 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
 271 {
 272         if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
 273             (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
 274                 return -EINVAL;
 275
 276         return addr_width >> 1;
 277 }
 278
 279 static void sun6i_enable_clock_autogate_a23(struct sun6i_dma_dev *sdev)
 280 {
 281         writel(SUN8I_DMA_GATE_ENABLE, sdev->base + SUN8I_DMA_GATE);
 282 }
 283
 284 static void sun6i_enable_clock_autogate_h3(struct sun6i_dma_dev *sdev)
 285 {
 286         writel(SUNXI_H3_DMA_GATE_ENABLE, sdev->base + SUNXI_H3_DMA_GATE);
 287 }
 288
 289 static void sun6i_set_burst_length_a31(u32 *p_cfg, s8 src_burst, s8 dst_burst)
 290 {
 291         *p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) |
 292                   DMA_CHAN_CFG_DST_BURST_A31(dst_burst);
 293 }
 294
 295 static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst)
 296 {
 297         *p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) |
 298                   DMA_CHAN_CFG_DST_BURST_H3(dst_burst);
 299 }
 300
 301 static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
 302 {
 303         struct sun6i_desc *txd = pchan->desc;
 304         struct sun6i_dma_lli *lli;
 305         size_t bytes;
 306         dma_addr_t pos;
 307
 308         pos = readl(pchan->base + DMA_CHAN_LLI_ADDR);
 309         bytes = readl(pchan->base + DMA_CHAN_CUR_CNT);
 310
 311         if (pos == LLI_LAST_ITEM)
 312                 return bytes;
 313
 314         for (lli = txd->v_lli; lli; lli = lli->v_lli_next) {
 315                 if (lli->p_lli_next == pos) {
 316                         for (lli = lli->v_lli_next; lli; lli = lli->v_lli_next)
 317                                 bytes += lli->len;
 318                         break;
 319                 }
 320         }
 321
 322         return bytes;
 323 }
 324
 325 static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
 326                                struct sun6i_dma_lli *next,
 327                                dma_addr_t next_phy,
 328                                struct sun6i_desc *txd)
 329 {
 330         if ((!prev && !txd) || !next)
 331                 return NULL;
 332
 333         if (!prev) {
 334                 txd->p_lli = next_phy;
 335                 txd->v_lli = next;
 336         } else {
 337                 prev->p_lli_next = next_phy;
 338                 prev->v_lli_next = next;
 339         }
 340
 341         next->p_lli_next = LLI_LAST_ITEM;
 342         next->v_lli_next = NULL;
 343
 344         return next;
 345 }
 346
 347 static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan,
 348                                       struct sun6i_dma_lli *lli)
 349 {
 350         phys_addr_t p_lli = virt_to_phys(lli);
 351
 352         dev_dbg(chan2dev(&vchan->vc.chan),
 353                 "\n\tdesc:   p - %pa v - 0x%p\n"
 354                 "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n"
 355                 "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n",
 356                 &p_lli, lli,
 357                 lli->cfg, lli->src, lli->dst,
 358                 lli->len, lli->para, lli->p_lli_next);
 359 }
 360
 361 static void sun6i_dma_free_desc(struct virt_dma_desc *vd)
 362 {
 363         struct sun6i_desc *txd = to_sun6i_desc(&vd->tx);
 364         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device);
 365         struct sun6i_dma_lli *v_lli, *v_next;
 366         dma_addr_t p_lli, p_next;
 367
 368         if (unlikely(!txd))
 369                 return;
 370
 371         p_lli = txd->p_lli;
 372         v_lli = txd->v_lli;
 373
 374         while (v_lli) {
 375                 v_next = v_lli->v_lli_next;
 376                 p_next = v_lli->p_lli_next;
 377
 378                 dma_pool_free(sdev->pool, v_lli, p_lli);
 379
 380                 v_lli = v_next;
 381                 p_lli = p_next;
 382         }
 383
 384         kfree(txd);
 385 }
 386
 387 static int sun6i_dma_start_desc(struct sun6i_vchan *vchan)
 388 {
 389         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device);
 390         struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc);
 391         struct sun6i_pchan *pchan = vchan->phy;
 392         u32 irq_val, irq_reg, irq_offset;
 393
 394         if (!pchan)
 395                 return -EAGAIN;
 396
 397         if (!desc) {
 398                 pchan->desc = NULL;
 399                 pchan->done = NULL;
 400                 return -EAGAIN;
 401         }
 402
 403         list_del(&desc->node);
 404
 405         pchan->desc = to_sun6i_desc(&desc->tx);
 406         pchan->done = NULL;
 407
 408         sun6i_dma_dump_lli(vchan, pchan->desc->v_lli);
 409
 410         irq_reg = pchan->idx / DMA_IRQ_CHAN_NR;
 411         irq_offset = pchan->idx % DMA_IRQ_CHAN_NR;
 412
 413         vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE;
 414
 415         irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg));
 416         irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) <<
 417                         (irq_offset * DMA_IRQ_CHAN_WIDTH));
 418         irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH);
 419         writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg));
 420
 421         writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
 422         writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);
 423
 424         sun6i_dma_dump_com_regs(sdev);
 425         sun6i_dma_dump_chan_regs(sdev, pchan);
 426
 427         return 0;
 428 }
 429
 430 static void sun6i_dma_tasklet(unsigned long data)
 431 {
 432         struct sun6i_dma_dev *sdev = (struct sun6i_dma_dev *)data;
 433         const struct sun6i_dma_config *cfg = sdev->cfg;
 434         struct sun6i_vchan *vchan;
 435         struct sun6i_pchan *pchan;
 436         unsigned int pchan_alloc = 0;
 437         unsigned int pchan_idx;
 438
 439         list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) {
 440                 spin_lock_irq(&vchan->vc.lock);
 441
 442                 pchan = vchan->phy;
 443
 444                 if (pchan && pchan->done) {
 445                         if (sun6i_dma_start_desc(vchan)) {
 446                                 /*
 447                                  * No current txd associated with this channel
 448                                  */
 449                                 dev_dbg(sdev->slave.dev, "pchan %u: free\n",
 450                                         pchan->idx);
 451
 452                                 /* Mark this channel free */
 453                                 vchan->phy = NULL;
 454                                 pchan->vchan = NULL;
 455                         }
 456                 }
 457                 spin_unlock_irq(&vchan->vc.lock);
 458         }
 459
 460         spin_lock_irq(&sdev->lock);
 461         for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) {
 462                 pchan = &sdev->pchans[pchan_idx];
 463
 464                 if (pchan->vchan || list_empty(&sdev->pending))
 465                         continue;
 466
 467                 vchan = list_first_entry(&sdev->pending,
 468                                          struct sun6i_vchan, node);
 469
 470                 /* Remove from pending channels */
 471                 list_del_init(&vchan->node);
 472                 pchan_alloc |= BIT(pchan_idx);
 473
 474                 /* Mark this channel allocated */
 475                 pchan->vchan = vchan;
 476                 vchan->phy = pchan;
 477                 dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n",
 478                         pchan->idx, &vchan->vc);
 479         }
 480         spin_unlock_irq(&sdev->lock);
 481
 482         for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) {
 483                 if (!(pchan_alloc & BIT(pchan_idx)))
 484                         continue;
 485
 486                 pchan = sdev->pchans + pchan_idx;
 487                 vchan = pchan->vchan;
 488                 if (vchan) {
 489                         spin_lock_irq(&vchan->vc.lock);
 490                         sun6i_dma_start_desc(vchan);
 491                         spin_unlock_irq(&vchan->vc.lock);
 492                 }
 493         }
 494 }
 495
 496 static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
 497 {
 498         struct sun6i_dma_dev *sdev = dev_id;
 499         struct sun6i_vchan *vchan;
 500         struct sun6i_pchan *pchan;
 501         int i, j, ret = IRQ_NONE;
 502         u32 status;
 503
 504         for (i = 0; i < sdev->cfg->nr_max_channels / DMA_IRQ_CHAN_NR; i++) {
 505                 status = readl(sdev->base + DMA_IRQ_STAT(i));
 506                 if (!status)
 507                         continue;
 508
 509                 dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n",
 510                         i ? "high" : "low", status);
 511
 512                 writel(status, sdev->base + DMA_IRQ_STAT(i));
 513
 514                 for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) {
 515                         pchan = sdev->pchans + j;
 516                         vchan = pchan->vchan;
 517                         if (vchan && (status & vchan->irq_type)) {
 518                                 if (vchan->cyclic) {
 519                                         vchan_cyclic_callback(&pchan->desc->vd);
 520                                 } else {
 521                                         spin_lock(&vchan->vc.lock);
 522                                         vchan_cookie_complete(&pchan->desc->vd);
 523                                         pchan->done = pchan->desc;
 524                                         spin_unlock(&vchan->vc.lock);
 525                                 }
 526                         }
 527
 528                         status = status >> DMA_IRQ_CHAN_WIDTH;
 529                 }
 530
 531                 if (!atomic_read(&sdev->tasklet_shutdown))
 532                         tasklet_schedule(&sdev->task);
 533                 ret = IRQ_HANDLED;
 534         }
 535
 536         return ret;
 537 }
 538
 539 static int set_config(struct sun6i_dma_dev *sdev,
 540                         struct dma_slave_config *sconfig,
 541                         enum dma_transfer_direction direction,
 542                         u32 *p_cfg)
 543 {
 544         s8 src_width, dst_width, src_burst, dst_burst;
 545
 546         switch (direction) {
 547         case DMA_MEM_TO_DEV:
 548                 src_burst = convert_burst(sconfig->src_maxburst ?
 549                                         sconfig->src_maxburst : 8);
 550                 src_width = convert_buswidth(sconfig->src_addr_width !=
 551                                                 DMA_SLAVE_BUSWIDTH_UNDEFINED ?
 552                                 sconfig->src_addr_width :
 553                                 DMA_SLAVE_BUSWIDTH_4_BYTES);
 554                 dst_burst = convert_burst(sconfig->dst_maxburst);
 555                 dst_width = convert_buswidth(sconfig->dst_addr_width);
 556                 break;
 557         case DMA_DEV_TO_MEM:
 558                 src_burst = convert_burst(sconfig->src_maxburst);
 559                 src_width = convert_buswidth(sconfig->src_addr_width);
 560                 dst_burst = convert_burst(sconfig->dst_maxburst ?
 561                                         sconfig->dst_maxburst : 8);
 562                 dst_width = convert_buswidth(sconfig->dst_addr_width !=
 563                                                 DMA_SLAVE_BUSWIDTH_UNDEFINED ?
 564                                 sconfig->dst_addr_width :
 565                                 DMA_SLAVE_BUSWIDTH_4_BYTES);
 566                 break;
 567         default:
 568                 return -EINVAL;
 569         }
 570
 571         if (src_burst < 0)
 572                 return src_burst;
 573         if (src_width < 0)
 574                 return src_width;
 575         if (dst_burst < 0)
 576                 return dst_burst;
 577         if (dst_width < 0)
 578                 return dst_width;
 579
 580         *p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) |
 581                 DMA_CHAN_CFG_DST_WIDTH(dst_width);
 582
 583         sdev->cfg->set_burst_length(p_cfg, src_burst, dst_burst);
 584
 585         return 0;
 586 }
 587
 588 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
 589                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 590                 size_t len, unsigned long flags)
 591 {
 592         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 593         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 594         struct sun6i_dma_lli *v_lli;
 595         struct sun6i_desc *txd;
 596         dma_addr_t p_lli;
 597         s8 burst, width;
 598
 599         dev_dbg(chan2dev(chan),
 600                 "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n",
 601                 __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags);
 602
 603         if (!len)
 604                 return NULL;
 605
 606         txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
 607         if (!txd)
 608                 return NULL;
 609
 610         v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
 611         if (!v_lli) {
 612                 dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
 613                 goto err_txd_free;
 614         }
 615
 616         v_lli->src = src;
 617         v_lli->dst = dest;
 618         v_lli->len = len;
 619         v_lli->para = NORMAL_WAIT;
 620
 621         burst = convert_burst(8);
 622         width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
 623         v_lli->cfg = DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
 624                 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
 625                 DMA_CHAN_CFG_DST_LINEAR_MODE |
 626                 DMA_CHAN_CFG_SRC_LINEAR_MODE |
 627                 DMA_CHAN_CFG_SRC_WIDTH(width) |
 628                 DMA_CHAN_CFG_DST_WIDTH(width);
 629
 630         sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst);
 631
 632         sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
 633
 634         sun6i_dma_dump_lli(vchan, v_lli);
 635
 636         return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
 637
 638 err_txd_free:
 639         kfree(txd);
 640         return NULL;
 641 }
 642
 643 static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
 644                 struct dma_chan *chan, struct scatterlist *sgl,
 645                 unsigned int sg_len, enum dma_transfer_direction dir,
 646                 unsigned long flags, void *context)
 647 {
 648         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 649         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 650         struct dma_slave_config *sconfig = &vchan->cfg;
 651         struct sun6i_dma_lli *v_lli, *prev = NULL;
 652         struct sun6i_desc *txd;
 653         struct scatterlist *sg;
 654         dma_addr_t p_lli;
 655         u32 lli_cfg;
 656         int i, ret;
 657
 658         if (!sgl)
 659                 return NULL;
 660
 661         ret = set_config(sdev, sconfig, dir, &lli_cfg);
 662         if (ret) {
 663                 dev_err(chan2dev(chan), "Invalid DMA configuration\n");
 664                 return NULL;
 665         }
 666
 667         txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
 668         if (!txd)
 669                 return NULL;
 670
 671         for_each_sg(sgl, sg, sg_len, i) {
 672                 v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
 673                 if (!v_lli)
 674                         goto err_lli_free;
 675
 676                 v_lli->len = sg_dma_len(sg);
 677                 v_lli->para = NORMAL_WAIT;
 678
 679                 if (dir == DMA_MEM_TO_DEV) {
 680                         v_lli->src = sg_dma_address(sg);
 681                         v_lli->dst = sconfig->dst_addr;
 682                         v_lli->cfg = lli_cfg |
 683                                 DMA_CHAN_CFG_DST_IO_MODE |
 684                                 DMA_CHAN_CFG_SRC_LINEAR_MODE |
 685                                 DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
 686                                 DMA_CHAN_CFG_DST_DRQ(vchan->port);
 687
 688                         dev_dbg(chan2dev(chan),
 689                                 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
 690                                 __func__, vchan->vc.chan.chan_id,
 691                                 &sconfig->dst_addr, &sg_dma_address(sg),
 692                                 sg_dma_len(sg), flags);
 693
 694                 } else {
 695                         v_lli->src = sconfig->src_addr;
 696                         v_lli->dst = sg_dma_address(sg);
 697                         v_lli->cfg = lli_cfg |
 698                                 DMA_CHAN_CFG_DST_LINEAR_MODE |
 699                                 DMA_CHAN_CFG_SRC_IO_MODE |
 700                                 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
 701                                 DMA_CHAN_CFG_SRC_DRQ(vchan->port);
 702
 703                         dev_dbg(chan2dev(chan),
 704                                 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
 705                                 __func__, vchan->vc.chan.chan_id,
 706                                 &sg_dma_address(sg), &sconfig->src_addr,
 707                                 sg_dma_len(sg), flags);
 708                 }
 709
 710                 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
 711         }
 712
 713         dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli);
 714         for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
 715                 sun6i_dma_dump_lli(vchan, prev);
 716
 717         return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
 718
 719 err_lli_free:
 720         for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
 721                 dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
 722         kfree(txd);
 723         return NULL;
 724 }
 725
 726 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic(
 727                                         struct dma_chan *chan,
 728                                         dma_addr_t buf_addr,
 729                                         size_t buf_len,
 730                                         size_t period_len,
 731                                         enum dma_transfer_direction dir,
 732                                         unsigned long flags)
 733 {
 734         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 735         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 736         struct dma_slave_config *sconfig = &vchan->cfg;
 737         struct sun6i_dma_lli *v_lli, *prev = NULL;
 738         struct sun6i_desc *txd;
 739         dma_addr_t p_lli;
 740         u32 lli_cfg;
 741         unsigned int i, periods = buf_len / period_len;
 742         int ret;
 743
 744         ret = set_config(sdev, sconfig, dir, &lli_cfg);
 745         if (ret) {
 746                 dev_err(chan2dev(chan), "Invalid DMA configuration\n");
 747                 return NULL;
 748         }
 749
 750         txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
 751         if (!txd)
 752                 return NULL;
 753
 754         for (i = 0; i < periods; i++) {
 755                 v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
 756                 if (!v_lli) {
 757                         dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
 758                         goto err_lli_free;
 759                 }
 760
 761                 v_lli->len = period_len;
 762                 v_lli->para = NORMAL_WAIT;
 763
 764                 if (dir == DMA_MEM_TO_DEV) {
 765                         v_lli->src = buf_addr + period_len * i;
 766                         v_lli->dst = sconfig->dst_addr;
 767                         v_lli->cfg = lli_cfg |
 768                                 DMA_CHAN_CFG_DST_IO_MODE |
 769                                 DMA_CHAN_CFG_SRC_LINEAR_MODE |
 770                                 DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
 771                                 DMA_CHAN_CFG_DST_DRQ(vchan->port);
 772                 } else {
 773                         v_lli->src = sconfig->src_addr;
 774                         v_lli->dst = buf_addr + period_len * i;
 775                         v_lli->cfg = lli_cfg |
 776                                 DMA_CHAN_CFG_DST_LINEAR_MODE |
 777                                 DMA_CHAN_CFG_SRC_IO_MODE |
 778                                 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
 779                                 DMA_CHAN_CFG_SRC_DRQ(vchan->port);
 780                 }
 781
 782                 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
 783         }
 784
 785         prev->p_lli_next = txd->p_lli;          /* cyclic list */
 786
 787         vchan->cyclic = true;
 788
 789         return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
 790
 791 err_lli_free:
 792         for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
 793                 dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
 794         kfree(txd);
 795         return NULL;
 796 }
 797
 798 static int sun6i_dma_config(struct dma_chan *chan,
 799                             struct dma_slave_config *config)
 800 {
 801         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 802
 803         memcpy(&vchan->cfg, config, sizeof(*config));
 804
 805         return 0;
 806 }
 807
 808 static int sun6i_dma_pause(struct dma_chan *chan)
 809 {
 810         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 811         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 812         struct sun6i_pchan *pchan = vchan->phy;
 813
 814         dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc);
 815
 816         if (pchan) {
 817                 writel(DMA_CHAN_PAUSE_PAUSE,
 818                        pchan->base + DMA_CHAN_PAUSE);
 819         } else {
 820                 spin_lock(&sdev->lock);
 821                 list_del_init(&vchan->node);
 822                 spin_unlock(&sdev->lock);
 823         }
 824
 825         return 0;
 826 }
 827
 828 static int sun6i_dma_resume(struct dma_chan *chan)
 829 {
 830         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 831         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 832         struct sun6i_pchan *pchan = vchan->phy;
 833         unsigned long flags;
 834
 835         dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc);
 836
 837         spin_lock_irqsave(&vchan->vc.lock, flags);
 838
 839         if (pchan) {
 840                 writel(DMA_CHAN_PAUSE_RESUME,
 841                        pchan->base + DMA_CHAN_PAUSE);
 842         } else if (!list_empty(&vchan->vc.desc_issued)) {
 843                 spin_lock(&sdev->lock);
 844                 list_add_tail(&vchan->node, &sdev->pending);
 845                 spin_unlock(&sdev->lock);
 846         }
 847
 848         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 849
 850         return 0;
 851 }
 852
 853 static int sun6i_dma_terminate_all(struct dma_chan *chan)
 854 {
 855         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 856         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 857         struct sun6i_pchan *pchan = vchan->phy;
 858         unsigned long flags;
 859         LIST_HEAD(head);
 860
 861         spin_lock(&sdev->lock);
 862         list_del_init(&vchan->node);
 863         spin_unlock(&sdev->lock);
 864
 865         spin_lock_irqsave(&vchan->vc.lock, flags);
 866
 867         if (vchan->cyclic) {
 868                 vchan->cyclic = false;
 869                 if (pchan && pchan->desc) {
 870                         struct virt_dma_desc *vd = &pchan->desc->vd;
 871                         struct virt_dma_chan *vc = &vchan->vc;
 872
 873                         list_add_tail(&vd->node, &vc->desc_completed);
 874                 }
 875         }
 876
 877         vchan_get_all_descriptors(&vchan->vc, &head);
 878
 879         if (pchan) {
 880                 writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE);
 881                 writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE);
 882
 883                 vchan->phy = NULL;
 884                 pchan->vchan = NULL;
 885                 pchan->desc = NULL;
 886                 pchan->done = NULL;
 887         }
 888
 889         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 890
 891         vchan_dma_desc_free_list(&vchan->vc, &head);
 892
 893         return 0;
 894 }
 895
 896 static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan,
 897                                            dma_cookie_t cookie,
 898                                            struct dma_tx_state *state)
 899 {
 900         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 901         struct sun6i_pchan *pchan = vchan->phy;
 902         struct sun6i_dma_lli *lli;
 903         struct virt_dma_desc *vd;
 904         struct sun6i_desc *txd;
 905         enum dma_status ret;
 906         unsigned long flags;
 907         size_t bytes = 0;
 908
 909         ret = dma_cookie_status(chan, cookie, state);
 910         if (ret == DMA_COMPLETE || !state)
 911                 return ret;
 912
 913         spin_lock_irqsave(&vchan->vc.lock, flags);
 914
 915         vd = vchan_find_desc(&vchan->vc, cookie);
 916         txd = to_sun6i_desc(&vd->tx);
 917
 918         if (vd) {
 919                 for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next)
 920                         bytes += lli->len;
 921         } else if (!pchan || !pchan->desc) {
 922                 bytes = 0;
 923         } else {
 924                 bytes = sun6i_get_chan_size(pchan);
 925         }
 926
 927         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 928
 929         dma_set_residue(state, bytes);
 930
 931         return ret;
 932 }
 933
 934 static void sun6i_dma_issue_pending(struct dma_chan *chan)
 935 {
 936         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 937         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 938         unsigned long flags;
 939
 940         spin_lock_irqsave(&vchan->vc.lock, flags);
 941
 942         if (vchan_issue_pending(&vchan->vc)) {
 943                 spin_lock(&sdev->lock);
 944
 945                 if (!vchan->phy && list_empty(&vchan->node)) {
 946                         list_add_tail(&vchan->node, &sdev->pending);
 947                         tasklet_schedule(&sdev->task);
 948                         dev_dbg(chan2dev(chan), "vchan %p: issued\n",
 949                                 &vchan->vc);
 950                 }
 951
 952                 spin_unlock(&sdev->lock);
 953         } else {
 954                 dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n",
 955                         &vchan->vc);
 956         }
 957
 958         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 959 }
 960
 961 static void sun6i_dma_free_chan_resources(struct dma_chan *chan)
 962 {
 963         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 964         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 965         unsigned long flags;
 966
 967         spin_lock_irqsave(&sdev->lock, flags);
 968         list_del_init(&vchan->node);
 969         spin_unlock_irqrestore(&sdev->lock, flags);
 970
 971         vchan_free_chan_resources(&vchan->vc);
 972 }
 973
 974 static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec,
 975                                            struct of_dma *ofdma)
 976 {
 977         struct sun6i_dma_dev *sdev = ofdma->of_dma_data;
 978         struct sun6i_vchan *vchan;
 979         struct dma_chan *chan;
 980         u8 port = dma_spec->args[0];
 981
 982         if (port > sdev->cfg->nr_max_requests)
 983                 return NULL;
 984
 985         chan = dma_get_any_slave_channel(&sdev->slave);
 986         if (!chan)
 987                 return NULL;
 988
 989         vchan = to_sun6i_vchan(chan);
 990         vchan->port = port;
 991
 992         return chan;
 993 }
 994
 995 static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev)
 996 {
 997         /* Disable all interrupts from DMA */
 998         writel(0, sdev->base + DMA_IRQ_EN(0));
 999         writel(0, sdev->base + DMA_IRQ_EN(1));
1000
1001         /* Prevent spurious interrupts from scheduling the tasklet */
1002         atomic_inc(&sdev->tasklet_shutdown);
1003
1004         /* Make sure we won't have any further interrupts */
1005         devm_free_irq(sdev->slave.dev, sdev->irq, sdev);
1006
1007         /* Actually prevent the tasklet from being scheduled */
1008         tasklet_kill(&sdev->task);
1009 }
1010
1011 static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev)
1012 {
1013         int i;
1014
1015         for (i = 0; i < sdev->cfg->nr_max_vchans; i++) {
1016                 struct sun6i_vchan *vchan = &sdev->vchans[i];
1017
1018                 list_del(&vchan->vc.chan.device_node);
1019                 tasklet_kill(&vchan->vc.task);
1020         }
1021 }
1022
1023 /*
1024  * For A31:
1025  *
1026  * There's 16 physical channels that can work in parallel.
1027  *
1028  * However we have 30 different endpoints for our requests.
1029  *
1030  * Since the channels are able to handle only an unidirectional
1031  * transfer, we need to allocate more virtual channels so that
1032  * everyone can grab one channel.
1033  *
1034  * Some devices can't work in both direction (mostly because it
1035  * wouldn't make sense), so we have a bit fewer virtual channels than
1036  * 2 channels per endpoints.
1037  */
1038
1039 static struct sun6i_dma_config sun6i_a31_dma_cfg = {
1040         .nr_max_channels = 16,
1041         .nr_max_requests = 30,
1042         .nr_max_vchans   = 53,
1043         .set_burst_length = sun6i_set_burst_length_a31,
1044 };
1045
1046 /*
1047  * The A23 only has 8 physical channels, a maximum DRQ port id of 24,
1048  * and a total of 37 usable source and destination endpoints.
1049  */
1050
1051 static struct sun6i_dma_config sun8i_a23_dma_cfg = {
1052         .nr_max_channels = 8,
1053         .nr_max_requests = 24,
1054         .nr_max_vchans   = 37,
1055         .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
1056         .set_burst_length = sun6i_set_burst_length_a31,
1057 };
1058
1059 static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
1060         .nr_max_channels = 8,
1061         .nr_max_requests = 28,
1062         .nr_max_vchans   = 39,
1063         .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
1064         .set_burst_length = sun6i_set_burst_length_a31,
1065 };
1066
1067 /*
1068  * The H3 has 12 physical channels, a maximum DRQ port id of 27,
1069  * and a total of 34 usable source and destination endpoints.
1070  */
1071
1072 static struct sun6i_dma_config sun8i_h3_dma_cfg = {
1073         .nr_max_channels = 12,
1074         .nr_max_requests = 27,
1075         .nr_max_vchans   = 34,
1076         .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
1077         .set_burst_length = sun6i_set_burst_length_h3,
1078 };
1079
1080 /*
1081  * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
1082  * and a total of 24 usable source and destination endpoints.
1083  */
1084
1085 static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
1086         .nr_max_channels = 8,
1087         .nr_max_requests = 23,
1088         .nr_max_vchans   = 24,
1089         .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
1090         .set_burst_length = sun6i_set_burst_length_a31,
1091 };
1092
1093 static const struct of_device_id sun6i_dma_match[] = {
1094         { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
1095         { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
1096         { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
1097         { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
1098         { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
1099         { /* sentinel */ }
1100 };
1101 MODULE_DEVICE_TABLE(of, sun6i_dma_match);
1102
1103 static int sun6i_dma_probe(struct platform_device *pdev)
1104 {
1105         struct sun6i_dma_dev *sdc;
1106         struct resource *res;
1107         int ret, i;
1108
1109         sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
1110         if (!sdc)
1111                 return -ENOMEM;
1112
1113         sdc->cfg = of_device_get_match_data(&pdev->dev);
1114         if (!sdc->cfg)
1115                 return -ENODEV;
1116
1117         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1118         sdc->base = devm_ioremap_resource(&pdev->dev, res);
1119         if (IS_ERR(sdc->base))
1120                 return PTR_ERR(sdc->base);
1121
1122         sdc->irq = platform_get_irq(pdev, 0);
1123         if (sdc->irq < 0) {
1124                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
1125                 return sdc->irq;
1126         }
1127
1128         sdc->clk = devm_clk_get(&pdev->dev, NULL);
1129         if (IS_ERR(sdc->clk)) {
1130                 dev_err(&pdev->dev, "No clock specified\n");
1131                 return PTR_ERR(sdc->clk);
1132         }
1133
1134         sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);
1135         if (IS_ERR(sdc->rstc)) {
1136                 dev_err(&pdev->dev, "No reset controller specified\n");
1137                 return PTR_ERR(sdc->rstc);
1138         }
1139
1140         sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1141                                      sizeof(struct sun6i_dma_lli), 4, 0);
1142         if (!sdc->pool) {
1143                 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1144                 return -ENOMEM;
1145         }
1146
1147         platform_set_drvdata(pdev, sdc);
1148         INIT_LIST_HEAD(&sdc->pending);
1149         spin_lock_init(&sdc->lock);
1150
1151         dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask);
1152         dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask);
1153         dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask);
1154         dma_cap_set(DMA_CYCLIC, sdc->slave.cap_mask);
1155
1156         INIT_LIST_HEAD(&sdc->slave.channels);
1157         sdc->slave.device_free_chan_resources   = sun6i_dma_free_chan_resources;
1158         sdc->slave.device_tx_status             = sun6i_dma_tx_status;
1159         sdc->slave.device_issue_pending         = sun6i_dma_issue_pending;
1160         sdc->slave.device_prep_slave_sg         = sun6i_dma_prep_slave_sg;
1161         sdc->slave.device_prep_dma_memcpy       = sun6i_dma_prep_dma_memcpy;
1162         sdc->slave.device_prep_dma_cyclic       = sun6i_dma_prep_dma_cyclic;
1163         sdc->slave.copy_align                   = DMAENGINE_ALIGN_4_BYTES;
1164         sdc->slave.device_config                = sun6i_dma_config;
1165         sdc->slave.device_pause                 = sun6i_dma_pause;
1166         sdc->slave.device_resume                = sun6i_dma_resume;
1167         sdc->slave.device_terminate_all         = sun6i_dma_terminate_all;
1168         sdc->slave.src_addr_widths              = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1169                                                   BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1170                                                   BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1171         sdc->slave.dst_addr_widths              = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1172                                                   BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1173                                                   BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1174         sdc->slave.directions                   = BIT(DMA_DEV_TO_MEM) |
1175                                                   BIT(DMA_MEM_TO_DEV);
1176         sdc->slave.residue_granularity          = DMA_RESIDUE_GRANULARITY_BURST;
1177         sdc->slave.dev = &pdev->dev;
1178
1179         sdc->pchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_channels,
1180                                    sizeof(struct sun6i_pchan), GFP_KERNEL);
1181         if (!sdc->pchans)
1182                 return -ENOMEM;
1183
1184         sdc->vchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_vchans,
1185                                    sizeof(struct sun6i_vchan), GFP_KERNEL);
1186         if (!sdc->vchans)
1187                 return -ENOMEM;
1188
1189         tasklet_init(&sdc->task, sun6i_dma_tasklet, (unsigned long)sdc);
1190
1191         for (i = 0; i < sdc->cfg->nr_max_channels; i++) {
1192                 struct sun6i_pchan *pchan = &sdc->pchans[i];
1193
1194                 pchan->idx = i;
1195                 pchan->base = sdc->base + 0x100 + i * 0x40;
1196         }
1197
1198         for (i = 0; i < sdc->cfg->nr_max_vchans; i++) {
1199                 struct sun6i_vchan *vchan = &sdc->vchans[i];
1200
1201                 INIT_LIST_HEAD(&vchan->node);
1202                 vchan->vc.desc_free = sun6i_dma_free_desc;
1203                 vchan_init(&vchan->vc, &sdc->slave);
1204         }
1205
1206         ret = reset_control_deassert(sdc->rstc);
1207         if (ret) {
1208                 dev_err(&pdev->dev, "Couldn't deassert the device from reset\n");
1209                 goto err_chan_free;
1210         }
1211
1212         ret = clk_prepare_enable(sdc->clk);
1213         if (ret) {
1214                 dev_err(&pdev->dev, "Couldn't enable the clock\n");
1215                 goto err_reset_assert;
1216         }
1217
1218         ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0,
1219                                dev_name(&pdev->dev), sdc);
1220         if (ret) {
1221                 dev_err(&pdev->dev, "Cannot request IRQ\n");
1222                 goto err_clk_disable;
1223         }
1224
1225         ret = dma_async_device_register(&sdc->slave);
1226         if (ret) {
1227                 dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
1228                 goto err_irq_disable;
1229         }
1230
1231         ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate,
1232                                          sdc);
1233         if (ret) {
1234                 dev_err(&pdev->dev, "of_dma_controller_register failed\n");
1235                 goto err_dma_unregister;
1236         }
1237
1238         if (sdc->cfg->clock_autogate_enable)
1239                 sdc->cfg->clock_autogate_enable(sdc);
1240
1241         return 0;
1242
1243 err_dma_unregister:
1244         dma_async_device_unregister(&sdc->slave);
1245 err_irq_disable:
1246         sun6i_kill_tasklet(sdc);
1247 err_clk_disable:
1248         clk_disable_unprepare(sdc->clk);
1249 err_reset_assert:
1250         reset_control_assert(sdc->rstc);
1251 err_chan_free:
1252         sun6i_dma_free(sdc);
1253         return ret;
1254 }
1255
1256 static int sun6i_dma_remove(struct platform_device *pdev)
1257 {
1258         struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev);
1259
1260         of_dma_controller_free(pdev->dev.of_node);
1261         dma_async_device_unregister(&sdc->slave);
1262
1263         sun6i_kill_tasklet(sdc);
1264
1265         clk_disable_unprepare(sdc->clk);
1266         reset_control_assert(sdc->rstc);
1267
1268         sun6i_dma_free(sdc);
1269
1270         return 0;
1271 }
1272
1273 static struct platform_driver sun6i_dma_driver = {
1274         .probe          = sun6i_dma_probe,
1275         .remove         = sun6i_dma_remove,
1276         .driver = {
1277                 .name           = "sun6i-dma",
1278                 .of_match_table = sun6i_dma_match,
1279         },
1280 };
1281 module_platform_driver(sun6i_dma_driver);
1282
1283 MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver");
1284 MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>");
1285 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1286 MODULE_LICENSE("GPL");