2 * DMA driver for STMicroelectronics STi FDMA controller
4 * Copyright (C) 2014 STMicroelectronics
6 * Author: Ludovic Barre <Ludovic.barre@st.com>
7 * Peter Griffin <peter.griffin@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/of_dma.h>
19 #include <linux/platform_device.h>
20 #include <linux/interrupt.h>
21 #include <linux/remoteproc.h>
25 static inline struct st_fdma_chan *to_st_fdma_chan(struct dma_chan *c)
27 return container_of(c, struct st_fdma_chan, vchan.chan);
30 static struct st_fdma_desc *to_st_fdma_desc(struct virt_dma_desc *vd)
32 return container_of(vd, struct st_fdma_desc, vdesc);
35 static int st_fdma_dreq_get(struct st_fdma_chan *fchan)
37 struct st_fdma_dev *fdev = fchan->fdev;
38 u32 req_line_cfg = fchan->cfg.req_line;
43 * dreq_mask is shared for n channels of fdma, so all accesses must be
44 * atomic. if the dreq_mask is changed between ffz and set_bit,
48 if (fdev->dreq_mask == ~0L) {
49 dev_err(fdev->dev, "No req lines available\n");
53 if (try || req_line_cfg >= ST_FDMA_NR_DREQS) {
54 dev_err(fdev->dev, "Invalid or used req line\n");
57 dreq_line = req_line_cfg;
61 } while (test_and_set_bit(dreq_line, &fdev->dreq_mask));
63 dev_dbg(fdev->dev, "get dreq_line:%d mask:%#lx\n",
64 dreq_line, fdev->dreq_mask);
69 static void st_fdma_dreq_put(struct st_fdma_chan *fchan)
71 struct st_fdma_dev *fdev = fchan->fdev;
73 dev_dbg(fdev->dev, "put dreq_line:%#x\n", fchan->dreq_line);
74 clear_bit(fchan->dreq_line, &fdev->dreq_mask);
77 static void st_fdma_xfer_desc(struct st_fdma_chan *fchan)
79 struct virt_dma_desc *vdesc;
80 unsigned long nbytes, ch_cmd, cmd;
82 vdesc = vchan_next_desc(&fchan->vchan);
86 fchan->fdesc = to_st_fdma_desc(vdesc);
87 nbytes = fchan->fdesc->node[0].desc->nbytes;
88 cmd = FDMA_CMD_START(fchan->vchan.chan.chan_id);
89 ch_cmd = fchan->fdesc->node[0].pdesc | FDMA_CH_CMD_STA_START;
91 /* start the channel for the descriptor */
92 fnode_write(fchan, nbytes, FDMA_CNTN_OFST);
93 fchan_write(fchan, ch_cmd, FDMA_CH_CMD_OFST);
95 fchan->fdev->slim_rproc->peri + FDMA_CMD_SET_OFST);
97 dev_dbg(fchan->fdev->dev, "start chan:%d\n", fchan->vchan.chan.chan_id);
100 static void st_fdma_ch_sta_update(struct st_fdma_chan *fchan,
101 unsigned long int_sta)
103 unsigned long ch_sta, ch_err;
104 int ch_id = fchan->vchan.chan.chan_id;
105 struct st_fdma_dev *fdev = fchan->fdev;
107 ch_sta = fchan_read(fchan, FDMA_CH_CMD_OFST);
108 ch_err = ch_sta & FDMA_CH_CMD_ERR_MASK;
109 ch_sta &= FDMA_CH_CMD_STA_MASK;
111 if (int_sta & FDMA_INT_STA_ERR) {
112 dev_warn(fdev->dev, "chan:%d, error:%ld\n", ch_id, ch_err);
113 fchan->status = DMA_ERROR;
118 case FDMA_CH_CMD_STA_PAUSED:
119 fchan->status = DMA_PAUSED;
122 case FDMA_CH_CMD_STA_RUNNING:
123 fchan->status = DMA_IN_PROGRESS;
128 static irqreturn_t st_fdma_irq_handler(int irq, void *dev_id)
130 struct st_fdma_dev *fdev = dev_id;
131 irqreturn_t ret = IRQ_NONE;
132 struct st_fdma_chan *fchan = &fdev->chans[0];
133 unsigned long int_sta, clr;
135 int_sta = fdma_read(fdev, FDMA_INT_STA_OFST);
138 for (; int_sta != 0 ; int_sta >>= 2, fchan++) {
139 if (!(int_sta & (FDMA_INT_STA_CH | FDMA_INT_STA_ERR)))
142 spin_lock(&fchan->vchan.lock);
143 st_fdma_ch_sta_update(fchan, int_sta);
146 if (!fchan->fdesc->iscyclic) {
147 list_del(&fchan->fdesc->vdesc.node);
148 vchan_cookie_complete(&fchan->fdesc->vdesc);
150 fchan->status = DMA_COMPLETE;
152 vchan_cyclic_callback(&fchan->fdesc->vdesc);
155 /* Start the next descriptor (if available) */
157 st_fdma_xfer_desc(fchan);
160 spin_unlock(&fchan->vchan.lock);
164 fdma_write(fdev, clr, FDMA_INT_CLR_OFST);
169 static struct dma_chan *st_fdma_of_xlate(struct of_phandle_args *dma_spec,
170 struct of_dma *ofdma)
172 struct st_fdma_dev *fdev = ofdma->of_dma_data;
173 struct dma_chan *chan;
174 struct st_fdma_chan *fchan;
177 if (dma_spec->args_count < 1)
178 return ERR_PTR(-EINVAL);
180 if (fdev->dma_device.dev->of_node != dma_spec->np)
181 return ERR_PTR(-EINVAL);
183 ret = rproc_boot(fdev->slim_rproc->rproc);
185 return ERR_PTR(-EPROBE_DEFER);
189 chan = dma_get_any_slave_channel(&fdev->dma_device);
193 fchan = to_st_fdma_chan(chan);
195 fchan->cfg.of_node = dma_spec->np;
196 fchan->cfg.req_line = dma_spec->args[0];
197 fchan->cfg.req_ctrl = 0;
198 fchan->cfg.type = ST_FDMA_TYPE_FREE_RUN;
200 if (dma_spec->args_count > 1)
201 fchan->cfg.req_ctrl = dma_spec->args[1]
202 & FDMA_REQ_CTRL_CFG_MASK;
204 if (dma_spec->args_count > 2)
205 fchan->cfg.type = dma_spec->args[2];
207 if (fchan->cfg.type == ST_FDMA_TYPE_FREE_RUN) {
208 fchan->dreq_line = 0;
210 fchan->dreq_line = st_fdma_dreq_get(fchan);
211 if (IS_ERR_VALUE(fchan->dreq_line)) {
212 chan = ERR_PTR(fchan->dreq_line);
217 dev_dbg(fdev->dev, "xlate req_line:%d type:%d req_ctrl:%#lx\n",
218 fchan->cfg.req_line, fchan->cfg.type, fchan->cfg.req_ctrl);
223 rproc_shutdown(fdev->slim_rproc->rproc);
228 static void st_fdma_free_desc(struct virt_dma_desc *vdesc)
230 struct st_fdma_desc *fdesc;
233 fdesc = to_st_fdma_desc(vdesc);
234 for (i = 0; i < fdesc->n_nodes; i++)
235 dma_pool_free(fdesc->fchan->node_pool, fdesc->node[i].desc,
236 fdesc->node[i].pdesc);
240 static struct st_fdma_desc *st_fdma_alloc_desc(struct st_fdma_chan *fchan,
243 struct st_fdma_desc *fdesc;
246 fdesc = kzalloc(struct_size(fdesc, node, sg_len), GFP_NOWAIT);
250 fdesc->fchan = fchan;
251 fdesc->n_nodes = sg_len;
252 for (i = 0; i < sg_len; i++) {
253 fdesc->node[i].desc = dma_pool_alloc(fchan->node_pool,
254 GFP_NOWAIT, &fdesc->node[i].pdesc);
255 if (!fdesc->node[i].desc)
262 dma_pool_free(fchan->node_pool, fdesc->node[i].desc,
263 fdesc->node[i].pdesc);
268 static int st_fdma_alloc_chan_res(struct dma_chan *chan)
270 struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
272 /* Create the dma pool for descriptor allocation */
273 fchan->node_pool = dma_pool_create(dev_name(&chan->dev->device),
275 sizeof(struct st_fdma_hw_node),
276 __alignof__(struct st_fdma_hw_node),
279 if (!fchan->node_pool) {
280 dev_err(fchan->fdev->dev, "unable to allocate desc pool\n");
284 dev_dbg(fchan->fdev->dev, "alloc ch_id:%d type:%d\n",
285 fchan->vchan.chan.chan_id, fchan->cfg.type);
290 static void st_fdma_free_chan_res(struct dma_chan *chan)
292 struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
293 struct rproc *rproc = fchan->fdev->slim_rproc->rproc;
296 dev_dbg(fchan->fdev->dev, "%s: freeing chan:%d\n",
297 __func__, fchan->vchan.chan.chan_id);
299 if (fchan->cfg.type != ST_FDMA_TYPE_FREE_RUN)
300 st_fdma_dreq_put(fchan);
302 spin_lock_irqsave(&fchan->vchan.lock, flags);
304 spin_unlock_irqrestore(&fchan->vchan.lock, flags);
306 dma_pool_destroy(fchan->node_pool);
307 fchan->node_pool = NULL;
308 memset(&fchan->cfg, 0, sizeof(struct st_fdma_cfg));
310 rproc_shutdown(rproc);
313 static struct dma_async_tx_descriptor *st_fdma_prep_dma_memcpy(
314 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
315 size_t len, unsigned long flags)
317 struct st_fdma_chan *fchan;
318 struct st_fdma_desc *fdesc;
319 struct st_fdma_hw_node *hw_node;
324 fchan = to_st_fdma_chan(chan);
326 /* We only require a single descriptor */
327 fdesc = st_fdma_alloc_desc(fchan, 1);
329 dev_err(fchan->fdev->dev, "no memory for desc\n");
333 hw_node = fdesc->node[0].desc;
335 hw_node->control = FDMA_NODE_CTRL_REQ_MAP_FREE_RUN;
336 hw_node->control |= FDMA_NODE_CTRL_SRC_INCR;
337 hw_node->control |= FDMA_NODE_CTRL_DST_INCR;
338 hw_node->control |= FDMA_NODE_CTRL_INT_EON;
339 hw_node->nbytes = len;
340 hw_node->saddr = src;
341 hw_node->daddr = dst;
342 hw_node->generic.length = len;
343 hw_node->generic.sstride = 0;
344 hw_node->generic.dstride = 0;
346 return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
349 static int config_reqctrl(struct st_fdma_chan *fchan,
350 enum dma_transfer_direction direction)
352 u32 maxburst = 0, addr = 0;
353 enum dma_slave_buswidth width;
354 int ch_id = fchan->vchan.chan.chan_id;
355 struct st_fdma_dev *fdev = fchan->fdev;
360 fchan->cfg.req_ctrl &= ~FDMA_REQ_CTRL_WNR;
361 maxburst = fchan->scfg.src_maxburst;
362 width = fchan->scfg.src_addr_width;
363 addr = fchan->scfg.src_addr;
367 fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_WNR;
368 maxburst = fchan->scfg.dst_maxburst;
369 width = fchan->scfg.dst_addr_width;
370 addr = fchan->scfg.dst_addr;
377 fchan->cfg.req_ctrl &= ~FDMA_REQ_CTRL_OPCODE_MASK;
381 case DMA_SLAVE_BUSWIDTH_1_BYTE:
382 fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST1;
385 case DMA_SLAVE_BUSWIDTH_2_BYTES:
386 fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST2;
389 case DMA_SLAVE_BUSWIDTH_4_BYTES:
390 fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST4;
393 case DMA_SLAVE_BUSWIDTH_8_BYTES:
394 fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST8;
401 fchan->cfg.req_ctrl &= ~FDMA_REQ_CTRL_NUM_OPS_MASK;
402 fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_NUM_OPS(maxburst-1);
403 dreq_write(fchan, fchan->cfg.req_ctrl, FDMA_REQ_CTRL_OFST);
405 fchan->cfg.dev_addr = addr;
406 fchan->cfg.dir = direction;
408 dev_dbg(fdev->dev, "chan:%d config_reqctrl:%#x req_ctrl:%#lx\n",
409 ch_id, addr, fchan->cfg.req_ctrl);
414 static void fill_hw_node(struct st_fdma_hw_node *hw_node,
415 struct st_fdma_chan *fchan,
416 enum dma_transfer_direction direction)
418 if (direction == DMA_MEM_TO_DEV) {
419 hw_node->control |= FDMA_NODE_CTRL_SRC_INCR;
420 hw_node->control |= FDMA_NODE_CTRL_DST_STATIC;
421 hw_node->daddr = fchan->cfg.dev_addr;
423 hw_node->control |= FDMA_NODE_CTRL_SRC_STATIC;
424 hw_node->control |= FDMA_NODE_CTRL_DST_INCR;
425 hw_node->saddr = fchan->cfg.dev_addr;
428 hw_node->generic.sstride = 0;
429 hw_node->generic.dstride = 0;
432 static inline struct st_fdma_chan *st_fdma_prep_common(struct dma_chan *chan,
433 size_t len, enum dma_transfer_direction direction)
435 struct st_fdma_chan *fchan;
440 fchan = to_st_fdma_chan(chan);
442 if (!is_slave_direction(direction)) {
443 dev_err(fchan->fdev->dev, "bad direction?\n");
450 static struct dma_async_tx_descriptor *st_fdma_prep_dma_cyclic(
451 struct dma_chan *chan, dma_addr_t buf_addr, size_t len,
452 size_t period_len, enum dma_transfer_direction direction,
455 struct st_fdma_chan *fchan;
456 struct st_fdma_desc *fdesc;
459 fchan = st_fdma_prep_common(chan, len, direction);
466 if (config_reqctrl(fchan, direction)) {
467 dev_err(fchan->fdev->dev, "bad width or direction\n");
471 /* the buffer length must be a multiple of period_len */
472 if (len % period_len != 0) {
473 dev_err(fchan->fdev->dev, "len is not multiple of period\n");
477 sg_len = len / period_len;
478 fdesc = st_fdma_alloc_desc(fchan, sg_len);
480 dev_err(fchan->fdev->dev, "no memory for desc\n");
484 fdesc->iscyclic = true;
486 for (i = 0; i < sg_len; i++) {
487 struct st_fdma_hw_node *hw_node = fdesc->node[i].desc;
489 hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc;
492 FDMA_NODE_CTRL_REQ_MAP_DREQ(fchan->dreq_line);
493 hw_node->control |= FDMA_NODE_CTRL_INT_EON;
495 fill_hw_node(hw_node, fchan, direction);
497 if (direction == DMA_MEM_TO_DEV)
498 hw_node->saddr = buf_addr + (i * period_len);
500 hw_node->daddr = buf_addr + (i * period_len);
502 hw_node->nbytes = period_len;
503 hw_node->generic.length = period_len;
506 return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
509 static struct dma_async_tx_descriptor *st_fdma_prep_slave_sg(
510 struct dma_chan *chan, struct scatterlist *sgl,
511 unsigned int sg_len, enum dma_transfer_direction direction,
512 unsigned long flags, void *context)
514 struct st_fdma_chan *fchan;
515 struct st_fdma_desc *fdesc;
516 struct st_fdma_hw_node *hw_node;
517 struct scatterlist *sg;
520 fchan = st_fdma_prep_common(chan, sg_len, direction);
527 fdesc = st_fdma_alloc_desc(fchan, sg_len);
529 dev_err(fchan->fdev->dev, "no memory for desc\n");
533 fdesc->iscyclic = false;
535 for_each_sg(sgl, sg, sg_len, i) {
536 hw_node = fdesc->node[i].desc;
538 hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc;
539 hw_node->control = FDMA_NODE_CTRL_REQ_MAP_DREQ(fchan->dreq_line);
541 fill_hw_node(hw_node, fchan, direction);
543 if (direction == DMA_MEM_TO_DEV)
544 hw_node->saddr = sg_dma_address(sg);
546 hw_node->daddr = sg_dma_address(sg);
548 hw_node->nbytes = sg_dma_len(sg);
549 hw_node->generic.length = sg_dma_len(sg);
552 /* interrupt at end of last node */
553 hw_node->control |= FDMA_NODE_CTRL_INT_EON;
555 return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
558 static size_t st_fdma_desc_residue(struct st_fdma_chan *fchan,
559 struct virt_dma_desc *vdesc,
562 struct st_fdma_desc *fdesc = fchan->fdesc;
564 dma_addr_t cur_addr = 0;
568 cur_addr = fchan_read(fchan, FDMA_CH_CMD_OFST);
569 cur_addr &= FDMA_CH_CMD_DATA_MASK;
572 for (i = fchan->fdesc->n_nodes - 1 ; i >= 0; i--) {
573 if (cur_addr == fdesc->node[i].pdesc) {
574 residue += fnode_read(fchan, FDMA_CNTN_OFST);
577 residue += fdesc->node[i].desc->nbytes;
583 static enum dma_status st_fdma_tx_status(struct dma_chan *chan,
585 struct dma_tx_state *txstate)
587 struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
588 struct virt_dma_desc *vd;
592 ret = dma_cookie_status(chan, cookie, txstate);
593 if (ret == DMA_COMPLETE || !txstate)
596 spin_lock_irqsave(&fchan->vchan.lock, flags);
597 vd = vchan_find_desc(&fchan->vchan, cookie);
598 if (fchan->fdesc && cookie == fchan->fdesc->vdesc.tx.cookie)
599 txstate->residue = st_fdma_desc_residue(fchan, vd, true);
601 txstate->residue = st_fdma_desc_residue(fchan, vd, false);
603 txstate->residue = 0;
605 spin_unlock_irqrestore(&fchan->vchan.lock, flags);
610 static void st_fdma_issue_pending(struct dma_chan *chan)
612 struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
615 spin_lock_irqsave(&fchan->vchan.lock, flags);
617 if (vchan_issue_pending(&fchan->vchan) && !fchan->fdesc)
618 st_fdma_xfer_desc(fchan);
620 spin_unlock_irqrestore(&fchan->vchan.lock, flags);
623 static int st_fdma_pause(struct dma_chan *chan)
626 struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
627 int ch_id = fchan->vchan.chan.chan_id;
628 unsigned long cmd = FDMA_CMD_PAUSE(ch_id);
630 dev_dbg(fchan->fdev->dev, "pause chan:%d\n", ch_id);
632 spin_lock_irqsave(&fchan->vchan.lock, flags);
634 fdma_write(fchan->fdev, cmd, FDMA_CMD_SET_OFST);
635 spin_unlock_irqrestore(&fchan->vchan.lock, flags);
640 static int st_fdma_resume(struct dma_chan *chan)
644 struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
645 int ch_id = fchan->vchan.chan.chan_id;
647 dev_dbg(fchan->fdev->dev, "resume chan:%d\n", ch_id);
649 spin_lock_irqsave(&fchan->vchan.lock, flags);
651 val = fchan_read(fchan, FDMA_CH_CMD_OFST);
652 val &= FDMA_CH_CMD_DATA_MASK;
653 fchan_write(fchan, val, FDMA_CH_CMD_OFST);
655 spin_unlock_irqrestore(&fchan->vchan.lock, flags);
660 static int st_fdma_terminate_all(struct dma_chan *chan)
664 struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
665 int ch_id = fchan->vchan.chan.chan_id;
666 unsigned long cmd = FDMA_CMD_PAUSE(ch_id);
668 dev_dbg(fchan->fdev->dev, "terminate chan:%d\n", ch_id);
670 spin_lock_irqsave(&fchan->vchan.lock, flags);
671 fdma_write(fchan->fdev, cmd, FDMA_CMD_SET_OFST);
673 vchan_get_all_descriptors(&fchan->vchan, &head);
674 spin_unlock_irqrestore(&fchan->vchan.lock, flags);
675 vchan_dma_desc_free_list(&fchan->vchan, &head);
680 static int st_fdma_slave_config(struct dma_chan *chan,
681 struct dma_slave_config *slave_cfg)
683 struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
685 memcpy(&fchan->scfg, slave_cfg, sizeof(fchan->scfg));
689 static const struct st_fdma_driverdata fdma_mpe31_stih407_11 = {
694 static const struct st_fdma_driverdata fdma_mpe31_stih407_12 = {
699 static const struct st_fdma_driverdata fdma_mpe31_stih407_13 = {
704 static const struct of_device_id st_fdma_match[] = {
705 { .compatible = "st,stih407-fdma-mpe31-11"
706 , .data = &fdma_mpe31_stih407_11 },
707 { .compatible = "st,stih407-fdma-mpe31-12"
708 , .data = &fdma_mpe31_stih407_12 },
709 { .compatible = "st,stih407-fdma-mpe31-13"
710 , .data = &fdma_mpe31_stih407_13 },
713 MODULE_DEVICE_TABLE(of, st_fdma_match);
715 static int st_fdma_parse_dt(struct platform_device *pdev,
716 const struct st_fdma_driverdata *drvdata,
717 struct st_fdma_dev *fdev)
719 snprintf(fdev->fw_name, FW_NAME_SIZE, "fdma_%s_%d.elf",
720 drvdata->name, drvdata->id);
722 return of_property_read_u32(pdev->dev.of_node, "dma-channels",
725 #define FDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
726 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
727 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
728 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
730 static void st_fdma_free(struct st_fdma_dev *fdev)
732 struct st_fdma_chan *fchan;
735 for (i = 0; i < fdev->nr_channels; i++) {
736 fchan = &fdev->chans[i];
737 list_del(&fchan->vchan.chan.device_node);
738 tasklet_kill(&fchan->vchan.task);
742 static int st_fdma_probe(struct platform_device *pdev)
744 struct st_fdma_dev *fdev;
745 const struct of_device_id *match;
746 struct device_node *np = pdev->dev.of_node;
747 const struct st_fdma_driverdata *drvdata;
750 match = of_match_device((st_fdma_match), &pdev->dev);
751 if (!match || !match->data) {
752 dev_err(&pdev->dev, "No device match found\n");
756 drvdata = match->data;
758 fdev = devm_kzalloc(&pdev->dev, sizeof(*fdev), GFP_KERNEL);
762 ret = st_fdma_parse_dt(pdev, drvdata, fdev);
764 dev_err(&pdev->dev, "unable to find platform data\n");
768 fdev->chans = devm_kcalloc(&pdev->dev, fdev->nr_channels,
769 sizeof(struct st_fdma_chan), GFP_KERNEL);
773 fdev->dev = &pdev->dev;
774 fdev->drvdata = drvdata;
775 platform_set_drvdata(pdev, fdev);
777 fdev->irq = platform_get_irq(pdev, 0);
779 dev_err(&pdev->dev, "Failed to get irq resource\n");
783 ret = devm_request_irq(&pdev->dev, fdev->irq, st_fdma_irq_handler, 0,
784 dev_name(&pdev->dev), fdev);
786 dev_err(&pdev->dev, "Failed to request irq (%d)\n", ret);
790 fdev->slim_rproc = st_slim_rproc_alloc(pdev, fdev->fw_name);
791 if (IS_ERR(fdev->slim_rproc)) {
792 ret = PTR_ERR(fdev->slim_rproc);
793 dev_err(&pdev->dev, "slim_rproc_alloc failed (%d)\n", ret);
797 /* Initialise list of FDMA channels */
798 INIT_LIST_HEAD(&fdev->dma_device.channels);
799 for (i = 0; i < fdev->nr_channels; i++) {
800 struct st_fdma_chan *fchan = &fdev->chans[i];
803 fchan->vchan.desc_free = st_fdma_free_desc;
804 vchan_init(&fchan->vchan, &fdev->dma_device);
807 /* Initialise the FDMA dreq (reserve 0 & 31 for FDMA use) */
808 fdev->dreq_mask = BIT(0) | BIT(31);
810 dma_cap_set(DMA_SLAVE, fdev->dma_device.cap_mask);
811 dma_cap_set(DMA_CYCLIC, fdev->dma_device.cap_mask);
812 dma_cap_set(DMA_MEMCPY, fdev->dma_device.cap_mask);
814 fdev->dma_device.dev = &pdev->dev;
815 fdev->dma_device.device_alloc_chan_resources = st_fdma_alloc_chan_res;
816 fdev->dma_device.device_free_chan_resources = st_fdma_free_chan_res;
817 fdev->dma_device.device_prep_dma_cyclic = st_fdma_prep_dma_cyclic;
818 fdev->dma_device.device_prep_slave_sg = st_fdma_prep_slave_sg;
819 fdev->dma_device.device_prep_dma_memcpy = st_fdma_prep_dma_memcpy;
820 fdev->dma_device.device_tx_status = st_fdma_tx_status;
821 fdev->dma_device.device_issue_pending = st_fdma_issue_pending;
822 fdev->dma_device.device_terminate_all = st_fdma_terminate_all;
823 fdev->dma_device.device_config = st_fdma_slave_config;
824 fdev->dma_device.device_pause = st_fdma_pause;
825 fdev->dma_device.device_resume = st_fdma_resume;
827 fdev->dma_device.src_addr_widths = FDMA_DMA_BUSWIDTHS;
828 fdev->dma_device.dst_addr_widths = FDMA_DMA_BUSWIDTHS;
829 fdev->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
830 fdev->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
832 ret = dmaenginem_async_device_register(&fdev->dma_device);
835 "Failed to register DMA device (%d)\n", ret);
839 ret = of_dma_controller_register(np, st_fdma_of_xlate, fdev);
842 "Failed to register controller (%d)\n", ret);
846 dev_info(&pdev->dev, "ST FDMA engine driver, irq:%d\n", fdev->irq);
852 st_slim_rproc_put(fdev->slim_rproc);
857 static int st_fdma_remove(struct platform_device *pdev)
859 struct st_fdma_dev *fdev = platform_get_drvdata(pdev);
861 devm_free_irq(&pdev->dev, fdev->irq, fdev);
862 st_slim_rproc_put(fdev->slim_rproc);
863 of_dma_controller_free(pdev->dev.of_node);
868 static struct platform_driver st_fdma_platform_driver = {
871 .of_match_table = st_fdma_match,
873 .probe = st_fdma_probe,
874 .remove = st_fdma_remove,
876 module_platform_driver(st_fdma_platform_driver);
878 MODULE_LICENSE("GPL v2");
879 MODULE_DESCRIPTION("STMicroelectronics FDMA engine driver");
880 MODULE_AUTHOR("Ludovic.barre <Ludovic.barre@st.com>");
881 MODULE_AUTHOR("Peter Griffin <peter.griffin@linaro.org>");
882 MODULE_ALIAS("platform: " DRIVER_NAME);