2 * Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/interrupt.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/dmaengine.h>
17 #include <linux/platform_device.h>
18 #include <linux/device.h>
19 #include <linux/platform_data/mmp_dma.h>
20 #include <linux/dmapool.h>
21 #include <linux/of_device.h>
22 #include <linux/of_dma.h>
24 #include <linux/dma/pxa-dma.h>
26 #include "dmaengine.h"
29 #define DCSR(n) (0x0000 + ((n) << 2))
30 #define DALGN(n) 0x00a0
32 #define DDADR(n) (0x0200 + ((n) << 4))
33 #define DSADR(n) (0x0204 + ((n) << 4))
34 #define DTADR(n) (0x0208 + ((n) << 4))
35 #define DCMD(n) (0x020c + ((n) << 4))
37 #define PXA_DCSR_RUN BIT(31) /* Run Bit (read / write) */
38 #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
39 #define PXA_DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (R/W) */
40 #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
41 #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
42 #define PXA_DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */
43 #define PXA_DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */
44 #define PXA_DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */
46 #define PXA_DCSR_EORIRQEN BIT(28) /* End of Receive IRQ Enable (R/W) */
47 #define PXA_DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */
48 #define PXA_DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */
49 #define PXA_DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */
50 #define PXA_DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */
51 #define PXA_DCSR_CMPST BIT(10) /* The Descriptor Compare Status */
52 #define PXA_DCSR_EORINTR BIT(9) /* The end of Receive */
54 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */
55 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
57 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
58 #define DDADR_STOP BIT(0) /* Stop (read / write) */
60 #define PXA_DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */
61 #define PXA_DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */
62 #define PXA_DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */
63 #define PXA_DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */
64 #define PXA_DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */
65 #define PXA_DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */
66 #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
67 #define PXA_DCMD_BURST8 (1 << 16) /* 8 byte burst */
68 #define PXA_DCMD_BURST16 (2 << 16) /* 16 byte burst */
69 #define PXA_DCMD_BURST32 (3 << 16) /* 32 byte burst */
70 #define PXA_DCMD_WIDTH1 (1 << 14) /* 1 byte width */
71 #define PXA_DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
72 #define PXA_DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
73 #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
75 #define PDMA_ALIGNMENT 3
76 #define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))
79 u32 ddadr; /* Points to the next descriptor + flags */
80 u32 dsadr; /* DSADR value for the current transfer */
81 u32 dtadr; /* DTADR value for the current transfer */
82 u32 dcmd; /* DCMD value for the current transfer */
86 struct virt_dma_desc vd; /* Virtual descriptor */
87 int nb_desc; /* Number of hw. descriptors */
88 size_t len; /* Number of bytes xfered */
89 dma_addr_t first; /* First descriptor's addr */
91 /* At least one descriptor has an src/dst address not multiple of 8 */
94 struct dma_pool *desc_pool; /* Channel's used allocator */
96 struct pxad_desc_hw *hw_desc[]; /* DMA coherent descriptors */
102 struct pxad_chan *vchan;
106 struct virt_dma_chan vc; /* Virtual channel */
107 u32 drcmr; /* Requestor of the channel */
108 enum pxad_chan_prio prio; /* Required priority of phy */
110 * At least one desc_sw in submitted or issued transfers on this channel
111 * has one address such as: addr % 8 != 0. This implies the DALGN
112 * setting on the phy.
115 struct dma_slave_config cfg; /* Runtime config */
117 /* protected by vc->lock */
118 struct pxad_phy *phy;
119 struct dma_pool *desc_pool; /* Descriptors pool */
123 struct dma_device slave;
126 struct pxad_phy *phys;
127 spinlock_t phy_lock; /* Phy association */
128 #ifdef CONFIG_DEBUG_FS
129 struct dentry *dbgfs_root;
130 struct dentry *dbgfs_state;
131 struct dentry **dbgfs_chan;
135 #define tx_to_pxad_desc(tx) \
136 container_of(tx, struct pxad_desc_sw, async_tx)
137 #define to_pxad_chan(dchan) \
138 container_of(dchan, struct pxad_chan, vc.chan)
139 #define to_pxad_dev(dmadev) \
140 container_of(dmadev, struct pxad_device, slave)
141 #define to_pxad_sw_desc(_vd) \
142 container_of((_vd), struct pxad_desc_sw, vd)
144 #define _phy_readl_relaxed(phy, _reg) \
145 readl_relaxed((phy)->base + _reg((phy)->idx))
146 #define phy_readl_relaxed(phy, _reg) \
149 _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \
150 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
151 "%s(): readl(%s): 0x%08x\n", __func__, #_reg, \
155 #define phy_writel(phy, val, _reg) \
157 writel((val), (phy)->base + _reg((phy)->idx)); \
158 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
159 "%s(): writel(0x%08x, %s)\n", \
160 __func__, (u32)(val), #_reg); \
162 #define phy_writel_relaxed(phy, val, _reg) \
164 writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \
165 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
166 "%s(): writel_relaxed(0x%08x, %s)\n", \
167 __func__, (u32)(val), #_reg); \
170 static unsigned int pxad_drcmr(unsigned int line)
173 return 0x100 + line * 4;
174 return 0x1000 + line * 4;
180 #ifdef CONFIG_DEBUG_FS
181 #include <linux/debugfs.h>
182 #include <linux/uaccess.h>
183 #include <linux/seq_file.h>
185 static int dbg_show_requester_chan(struct seq_file *s, void *p)
187 struct pxad_phy *phy = s->private;
191 seq_printf(s, "DMA channel %d requester :\n", phy->idx);
192 for (i = 0; i < 70; i++) {
193 drcmr = readl_relaxed(phy->base + pxad_drcmr(i));
194 if ((drcmr & DRCMR_CHLNUM) == phy->idx)
195 seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i,
196 !!(drcmr & DRCMR_MAPVLD));
201 static inline int dbg_burst_from_dcmd(u32 dcmd)
203 int burst = (dcmd >> 16) & 0x3;
205 return burst ? 4 << burst : 0;
208 static int is_phys_valid(unsigned long addr)
210 return pfn_valid(__phys_to_pfn(addr));
213 #define PXA_DCSR_STR(flag) (dcsr & PXA_DCSR_##flag ? #flag" " : "")
214 #define PXA_DCMD_STR(flag) (dcmd & PXA_DCMD_##flag ? #flag" " : "")
216 static int dbg_show_descriptors(struct seq_file *s, void *p)
218 struct pxad_phy *phy = s->private;
219 int i, max_show = 20, burst, width;
221 unsigned long phys_desc, ddadr;
222 struct pxad_desc_hw *desc;
224 phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR);
226 seq_printf(s, "DMA channel %d descriptors :\n", phy->idx);
227 seq_printf(s, "[%03d] First descriptor unknown\n", 0);
228 for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {
229 desc = phys_to_virt(phys_desc);
231 burst = dbg_burst_from_dcmd(dcmd);
232 width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
234 seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",
236 seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);
237 seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);
238 seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);
239 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
241 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
242 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
243 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
244 PXA_DCMD_STR(ENDIAN), burst, width,
245 dcmd & PXA_DCMD_LENGTH);
246 phys_desc = desc->ddadr;
249 seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",
252 seq_printf(s, "[%03d] Desc at %08lx is %s\n",
253 i, phys_desc, phys_desc == DDADR_STOP ?
254 "DDADR_STOP" : "invalid");
259 static int dbg_show_chan_state(struct seq_file *s, void *p)
261 struct pxad_phy *phy = s->private;
264 static const char * const str_prio[] = {
265 "high", "normal", "low", "invalid"
268 dcsr = _phy_readl_relaxed(phy, DCSR);
269 dcmd = _phy_readl_relaxed(phy, DCMD);
270 burst = dbg_burst_from_dcmd(dcmd);
271 width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
273 seq_printf(s, "DMA channel %d\n", phy->idx);
274 seq_printf(s, "\tPriority : %s\n",
275 str_prio[(phy->idx & 0xf) / 4]);
276 seq_printf(s, "\tUnaligned transfer bit: %s\n",
277 _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ?
279 seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
280 dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC),
281 PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN),
282 PXA_DCSR_STR(EORJMPEN), PXA_DCSR_STR(EORSTOPEN),
283 PXA_DCSR_STR(SETCMPST), PXA_DCSR_STR(CLRCMPST),
284 PXA_DCSR_STR(CMPST), PXA_DCSR_STR(EORINTR),
285 PXA_DCSR_STR(REQPEND), PXA_DCSR_STR(STOPSTATE),
286 PXA_DCSR_STR(ENDINTR), PXA_DCSR_STR(STARTINTR),
287 PXA_DCSR_STR(BUSERR));
289 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
291 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
292 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
293 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
294 PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH);
295 seq_printf(s, "\tDSADR = %08x\n", _phy_readl_relaxed(phy, DSADR));
296 seq_printf(s, "\tDTADR = %08x\n", _phy_readl_relaxed(phy, DTADR));
297 seq_printf(s, "\tDDADR = %08x\n", _phy_readl_relaxed(phy, DDADR));
302 static int dbg_show_state(struct seq_file *s, void *p)
304 struct pxad_device *pdev = s->private;
306 /* basic device status */
307 seq_puts(s, "DMA engine status\n");
308 seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans);
313 #define DBGFS_FUNC_DECL(name) \
314 static int dbg_open_##name(struct inode *inode, struct file *file) \
316 return single_open(file, dbg_show_##name, inode->i_private); \
318 static const struct file_operations dbg_fops_##name = { \
319 .owner = THIS_MODULE, \
320 .open = dbg_open_##name, \
321 .llseek = seq_lseek, \
323 .release = single_release, \
326 DBGFS_FUNC_DECL(state);
327 DBGFS_FUNC_DECL(chan_state);
328 DBGFS_FUNC_DECL(descriptors);
329 DBGFS_FUNC_DECL(requester_chan);
331 static struct dentry *pxad_dbg_alloc_chan(struct pxad_device *pdev,
332 int ch, struct dentry *chandir)
335 struct dentry *chan, *chan_state = NULL, *chan_descr = NULL;
336 struct dentry *chan_reqs = NULL;
339 scnprintf(chan_name, sizeof(chan_name), "%d", ch);
340 chan = debugfs_create_dir(chan_name, chandir);
341 dt = (void *)&pdev->phys[ch];
344 chan_state = debugfs_create_file("state", 0400, chan, dt,
345 &dbg_fops_chan_state);
347 chan_descr = debugfs_create_file("descriptors", 0400, chan, dt,
348 &dbg_fops_descriptors);
350 chan_reqs = debugfs_create_file("requesters", 0400, chan, dt,
351 &dbg_fops_requester_chan);
358 debugfs_remove_recursive(chan);
362 static void pxad_init_debugfs(struct pxad_device *pdev)
365 struct dentry *chandir;
367 pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL);
368 if (IS_ERR(pdev->dbgfs_root) || !pdev->dbgfs_root)
371 pdev->dbgfs_state = debugfs_create_file("state", 0400, pdev->dbgfs_root,
372 pdev, &dbg_fops_state);
373 if (!pdev->dbgfs_state)
377 kmalloc_array(pdev->nr_chans, sizeof(*pdev->dbgfs_state),
379 if (!pdev->dbgfs_chan)
382 chandir = debugfs_create_dir("channels", pdev->dbgfs_root);
386 for (i = 0; i < pdev->nr_chans; i++) {
387 pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir);
388 if (!pdev->dbgfs_chan[i])
395 kfree(pdev->dbgfs_chan);
398 debugfs_remove_recursive(pdev->dbgfs_root);
400 pr_err("pxad: debugfs is not available\n");
403 static void pxad_cleanup_debugfs(struct pxad_device *pdev)
405 debugfs_remove_recursive(pdev->dbgfs_root);
408 static inline void pxad_init_debugfs(struct pxad_device *pdev) {}
409 static inline void pxad_cleanup_debugfs(struct pxad_device *pdev) {}
413 * In the transition phase where legacy pxa handling is done at the same time as
414 * mmp_dma, the DMA physical channel split between the 2 DMA providers is done
415 * through legacy_reserved. Legacy code reserves DMA channels by settings
416 * corresponding bits in legacy_reserved.
418 static u32 legacy_reserved;
419 static u32 legacy_unavailable;
421 static struct pxad_phy *lookup_phy(struct pxad_chan *pchan)
424 struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device);
425 struct pxad_phy *phy, *found = NULL;
429 * dma channel priorities
430 * ch 0 - 3, 16 - 19 <--> (0)
431 * ch 4 - 7, 20 - 23 <--> (1)
432 * ch 8 - 11, 24 - 27 <--> (2)
433 * ch 12 - 15, 28 - 31 <--> (3)
436 spin_lock_irqsave(&pdev->phy_lock, flags);
437 for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) {
438 for (i = 0; i < pdev->nr_chans; i++) {
439 if (prio != (i & 0xf) >> 2)
441 if ((i < 32) && (legacy_reserved & BIT(i)))
443 phy = &pdev->phys[i];
448 legacy_unavailable |= BIT(i);
455 spin_unlock_irqrestore(&pdev->phy_lock, flags);
456 dev_dbg(&pchan->vc.chan.dev->device,
457 "%s(): phy=%p(%d)\n", __func__, found,
458 found ? found->idx : -1);
463 static void pxad_free_phy(struct pxad_chan *chan)
465 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
470 dev_dbg(&chan->vc.chan.dev->device,
471 "%s(): freeing\n", __func__);
475 /* clear the channel mapping in DRCMR */
476 if (chan->drcmr <= DRCMR_CHLNUM) {
477 reg = pxad_drcmr(chan->drcmr);
478 writel_relaxed(0, chan->phy->base + reg);
481 spin_lock_irqsave(&pdev->phy_lock, flags);
482 for (i = 0; i < 32; i++)
483 if (chan->phy == &pdev->phys[i])
484 legacy_unavailable &= ~BIT(i);
485 chan->phy->vchan = NULL;
487 spin_unlock_irqrestore(&pdev->phy_lock, flags);
490 static bool is_chan_running(struct pxad_chan *chan)
493 struct pxad_phy *phy = chan->phy;
497 dcsr = phy_readl_relaxed(phy, DCSR);
498 return dcsr & PXA_DCSR_RUN;
501 static bool is_running_chan_misaligned(struct pxad_chan *chan)
506 dalgn = phy_readl_relaxed(chan->phy, DALGN);
507 return dalgn & (BIT(chan->phy->idx));
510 static void phy_enable(struct pxad_phy *phy, bool misaligned)
517 dev_dbg(&phy->vchan->vc.chan.dev->device,
518 "%s(); phy=%p(%d) misaligned=%d\n", __func__,
519 phy, phy->idx, misaligned);
521 if (phy->vchan->drcmr <= DRCMR_CHLNUM) {
522 reg = pxad_drcmr(phy->vchan->drcmr);
523 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg);
526 dalgn = phy_readl_relaxed(phy, DALGN);
528 dalgn |= BIT(phy->idx);
530 dalgn &= ~BIT(phy->idx);
531 phy_writel_relaxed(phy, dalgn, DALGN);
533 phy_writel(phy, PXA_DCSR_STOPIRQEN | PXA_DCSR_ENDINTR |
534 PXA_DCSR_BUSERR | PXA_DCSR_RUN, DCSR);
537 static void phy_disable(struct pxad_phy *phy)
544 dcsr = phy_readl_relaxed(phy, DCSR);
545 dev_dbg(&phy->vchan->vc.chan.dev->device,
546 "%s(): phy=%p(%d)\n", __func__, phy, phy->idx);
547 phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR);
550 static void pxad_launch_chan(struct pxad_chan *chan,
551 struct pxad_desc_sw *desc)
553 dev_dbg(&chan->vc.chan.dev->device,
554 "%s(): desc=%p\n", __func__, desc);
556 chan->phy = lookup_phy(chan);
558 dev_dbg(&chan->vc.chan.dev->device,
559 "%s(): no free dma channel\n", __func__);
565 * Program the descriptor's address into the DMA controller,
566 * then start the DMA transaction
568 phy_writel(chan->phy, desc->first, DDADR);
569 phy_enable(chan->phy, chan->misaligned);
572 static void set_updater_desc(struct pxad_desc_sw *sw_desc,
575 struct pxad_desc_hw *updater =
576 sw_desc->hw_desc[sw_desc->nb_desc - 1];
577 dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr;
579 updater->ddadr = DDADR_STOP;
580 updater->dsadr = dma;
581 updater->dtadr = dma + 8;
582 updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 |
583 (PXA_DCMD_LENGTH & sizeof(u32));
584 if (flags & DMA_PREP_INTERRUPT)
585 updater->dcmd |= PXA_DCMD_ENDIRQEN;
587 sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first;
590 static bool is_desc_completed(struct virt_dma_desc *vd)
592 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
593 struct pxad_desc_hw *updater =
594 sw_desc->hw_desc[sw_desc->nb_desc - 1];
596 return updater->dtadr != (updater->dsadr + 8);
599 static void pxad_desc_chain(struct virt_dma_desc *vd1,
600 struct virt_dma_desc *vd2)
602 struct pxad_desc_sw *desc1 = to_pxad_sw_desc(vd1);
603 struct pxad_desc_sw *desc2 = to_pxad_sw_desc(vd2);
604 dma_addr_t dma_to_chain;
606 dma_to_chain = desc2->first;
607 desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain;
610 static bool pxad_try_hotchain(struct virt_dma_chan *vc,
611 struct virt_dma_desc *vd)
613 struct virt_dma_desc *vd_last_issued = NULL;
614 struct pxad_chan *chan = to_pxad_chan(&vc->chan);
617 * Attempt to hot chain the tx if the phy is still running. This is
618 * considered successful only if either the channel is still running
619 * after the chaining, or if the chained transfer is completed after
620 * having been hot chained.
621 * A change of alignment is not allowed, and forbids hotchaining.
623 if (is_chan_running(chan)) {
624 BUG_ON(list_empty(&vc->desc_issued));
626 if (!is_running_chan_misaligned(chan) &&
627 to_pxad_sw_desc(vd)->misaligned)
630 vd_last_issued = list_entry(vc->desc_issued.prev,
631 struct virt_dma_desc, node);
632 pxad_desc_chain(vd_last_issued, vd);
633 if (is_chan_running(chan) || is_desc_completed(vd_last_issued))
640 static unsigned int clear_chan_irq(struct pxad_phy *phy)
643 u32 dint = readl(phy->base + DINT);
645 if (!(dint & BIT(phy->idx)))
649 dcsr = phy_readl_relaxed(phy, DCSR);
650 phy_writel(phy, dcsr, DCSR);
651 if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan))
652 dev_warn(&phy->vchan->vc.chan.dev->device,
653 "%s(chan=%p): PXA_DCSR_BUSERR\n",
654 __func__, &phy->vchan);
656 return dcsr & ~PXA_DCSR_RUN;
659 static irqreturn_t pxad_chan_handler(int irq, void *dev_id)
661 struct pxad_phy *phy = dev_id;
662 struct pxad_chan *chan = phy->vchan;
663 struct virt_dma_desc *vd, *tmp;
669 dcsr = clear_chan_irq(phy);
670 if (dcsr & PXA_DCSR_RUN)
673 spin_lock_irqsave(&chan->vc.lock, flags);
674 list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) {
675 dev_dbg(&chan->vc.chan.dev->device,
676 "%s(): checking txd %p[%x]: completed=%d\n",
677 __func__, vd, vd->tx.cookie, is_desc_completed(vd));
678 if (to_pxad_sw_desc(vd)->cyclic) {
679 vchan_cyclic_callback(vd);
682 if (is_desc_completed(vd)) {
684 vchan_cookie_complete(vd);
690 if (dcsr & PXA_DCSR_STOPSTATE) {
691 dev_dbg(&chan->vc.chan.dev->device,
692 "%s(): channel stopped, submitted_empty=%d issued_empty=%d",
694 list_empty(&chan->vc.desc_submitted),
695 list_empty(&chan->vc.desc_issued));
696 phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR);
698 if (list_empty(&chan->vc.desc_issued)) {
700 !list_empty(&chan->vc.desc_submitted);
702 vd = list_first_entry(&chan->vc.desc_issued,
703 struct virt_dma_desc, node);
704 pxad_launch_chan(chan, to_pxad_sw_desc(vd));
707 spin_unlock_irqrestore(&chan->vc.lock, flags);
712 static irqreturn_t pxad_int_handler(int irq, void *dev_id)
714 struct pxad_device *pdev = dev_id;
715 struct pxad_phy *phy;
716 u32 dint = readl(pdev->base + DINT);
717 int i, ret = IRQ_NONE;
722 phy = &pdev->phys[i];
723 if ((i < 32) && (legacy_reserved & BIT(i)))
725 if (pxad_chan_handler(irq, phy) == IRQ_HANDLED)
732 static int pxad_alloc_chan_resources(struct dma_chan *dchan)
734 struct pxad_chan *chan = to_pxad_chan(dchan);
735 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
740 chan->desc_pool = dma_pool_create(dma_chan_name(dchan),
742 sizeof(struct pxad_desc_hw),
743 __alignof__(struct pxad_desc_hw),
745 if (!chan->desc_pool) {
746 dev_err(&chan->vc.chan.dev->device,
747 "%s(): unable to allocate descriptor pool\n",
755 static void pxad_free_chan_resources(struct dma_chan *dchan)
757 struct pxad_chan *chan = to_pxad_chan(dchan);
759 vchan_free_chan_resources(&chan->vc);
760 dma_pool_destroy(chan->desc_pool);
761 chan->desc_pool = NULL;
765 static void pxad_free_desc(struct virt_dma_desc *vd)
769 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
771 BUG_ON(sw_desc->nb_desc == 0);
772 for (i = sw_desc->nb_desc - 1; i >= 0; i--) {
774 dma = sw_desc->hw_desc[i - 1]->ddadr;
776 dma = sw_desc->first;
777 dma_pool_free(sw_desc->desc_pool,
778 sw_desc->hw_desc[i], dma);
780 sw_desc->nb_desc = 0;
784 static struct pxad_desc_sw *
785 pxad_alloc_desc(struct pxad_chan *chan, unsigned int nb_hw_desc)
787 struct pxad_desc_sw *sw_desc;
791 sw_desc = kzalloc(sizeof(*sw_desc) +
792 nb_hw_desc * sizeof(struct pxad_desc_hw *),
796 sw_desc->desc_pool = chan->desc_pool;
798 for (i = 0; i < nb_hw_desc; i++) {
799 sw_desc->hw_desc[i] = dma_pool_alloc(sw_desc->desc_pool,
801 if (!sw_desc->hw_desc[i]) {
802 dev_err(&chan->vc.chan.dev->device,
803 "%s(): Couldn't allocate the %dth hw_desc from dma_pool %p\n",
804 __func__, i, sw_desc->desc_pool);
809 sw_desc->first = dma;
811 sw_desc->hw_desc[i - 1]->ddadr = dma;
817 pxad_free_desc(&sw_desc->vd);
821 static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx)
823 struct virt_dma_chan *vc = to_virt_chan(tx->chan);
824 struct pxad_chan *chan = to_pxad_chan(&vc->chan);
825 struct virt_dma_desc *vd_chained = NULL,
826 *vd = container_of(tx, struct virt_dma_desc, tx);
830 set_updater_desc(to_pxad_sw_desc(vd), tx->flags);
832 spin_lock_irqsave(&vc->lock, flags);
833 cookie = dma_cookie_assign(tx);
835 if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) {
836 list_move_tail(&vd->node, &vc->desc_issued);
837 dev_dbg(&chan->vc.chan.dev->device,
838 "%s(): txd %p[%x]: submitted (hot linked)\n",
839 __func__, vd, cookie);
844 * Fallback to placing the tx in the submitted queue
846 if (!list_empty(&vc->desc_submitted)) {
847 vd_chained = list_entry(vc->desc_submitted.prev,
848 struct virt_dma_desc, node);
850 * Only chain the descriptors if no new misalignment is
851 * introduced. If a new misalignment is chained, let the channel
852 * stop, and be relaunched in misalign mode from the irq
855 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned)
856 pxad_desc_chain(vd_chained, vd);
860 dev_dbg(&chan->vc.chan.dev->device,
861 "%s(): txd %p[%x]: submitted (%s linked)\n",
862 __func__, vd, cookie, vd_chained ? "cold" : "not");
863 list_move_tail(&vd->node, &vc->desc_submitted);
864 chan->misaligned |= to_pxad_sw_desc(vd)->misaligned;
867 spin_unlock_irqrestore(&vc->lock, flags);
871 static void pxad_issue_pending(struct dma_chan *dchan)
873 struct pxad_chan *chan = to_pxad_chan(dchan);
874 struct virt_dma_desc *vd_first;
877 spin_lock_irqsave(&chan->vc.lock, flags);
878 if (list_empty(&chan->vc.desc_submitted))
881 vd_first = list_first_entry(&chan->vc.desc_submitted,
882 struct virt_dma_desc, node);
883 dev_dbg(&chan->vc.chan.dev->device,
884 "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie);
886 vchan_issue_pending(&chan->vc);
887 if (!pxad_try_hotchain(&chan->vc, vd_first))
888 pxad_launch_chan(chan, to_pxad_sw_desc(vd_first));
890 spin_unlock_irqrestore(&chan->vc.lock, flags);
893 static inline struct dma_async_tx_descriptor *
894 pxad_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd,
895 unsigned long tx_flags)
897 struct dma_async_tx_descriptor *tx;
898 struct pxad_chan *chan = container_of(vc, struct pxad_chan, vc);
900 INIT_LIST_HEAD(&vd->node);
901 tx = vchan_tx_prep(vc, vd, tx_flags);
902 tx->tx_submit = pxad_tx_submit;
903 dev_dbg(&chan->vc.chan.dev->device,
904 "%s(): vc=%p txd=%p[%x] flags=0x%lx\n", __func__,
905 vc, vd, vd->tx.cookie,
911 static void pxad_get_config(struct pxad_chan *chan,
912 enum dma_transfer_direction dir,
913 u32 *dcmd, u32 *dev_src, u32 *dev_dst)
915 u32 maxburst = 0, dev_addr = 0;
916 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
919 if (dir == DMA_DEV_TO_MEM) {
920 maxburst = chan->cfg.src_maxburst;
921 width = chan->cfg.src_addr_width;
922 dev_addr = chan->cfg.src_addr;
924 *dcmd |= PXA_DCMD_INCTRGADDR;
925 if (chan->drcmr <= DRCMR_CHLNUM)
926 *dcmd |= PXA_DCMD_FLOWSRC;
928 if (dir == DMA_MEM_TO_DEV) {
929 maxburst = chan->cfg.dst_maxburst;
930 width = chan->cfg.dst_addr_width;
931 dev_addr = chan->cfg.dst_addr;
933 *dcmd |= PXA_DCMD_INCSRCADDR;
934 if (chan->drcmr <= DRCMR_CHLNUM)
935 *dcmd |= PXA_DCMD_FLOWTRG;
937 if (dir == DMA_MEM_TO_MEM)
938 *dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR |
941 dev_dbg(&chan->vc.chan.dev->device,
942 "%s(): dev_addr=0x%x maxburst=%d width=%d dir=%d\n",
943 __func__, dev_addr, maxburst, width, dir);
945 if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
946 *dcmd |= PXA_DCMD_WIDTH1;
947 else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
948 *dcmd |= PXA_DCMD_WIDTH2;
949 else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
950 *dcmd |= PXA_DCMD_WIDTH4;
953 *dcmd |= PXA_DCMD_BURST8;
954 else if (maxburst == 16)
955 *dcmd |= PXA_DCMD_BURST16;
956 else if (maxburst == 32)
957 *dcmd |= PXA_DCMD_BURST32;
959 /* FIXME: drivers should be ported over to use the filter
960 * function. Once that's done, the following two lines can
963 if (chan->cfg.slave_id)
964 chan->drcmr = chan->cfg.slave_id;
967 static struct dma_async_tx_descriptor *
968 pxad_prep_memcpy(struct dma_chan *dchan,
969 dma_addr_t dma_dst, dma_addr_t dma_src,
970 size_t len, unsigned long flags)
972 struct pxad_chan *chan = to_pxad_chan(dchan);
973 struct pxad_desc_sw *sw_desc;
974 struct pxad_desc_hw *hw_desc;
976 unsigned int i, nb_desc = 0;
982 dev_dbg(&chan->vc.chan.dev->device,
983 "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n",
984 __func__, (unsigned long)dma_dst, (unsigned long)dma_src,
986 pxad_get_config(chan, DMA_MEM_TO_MEM, &dcmd, NULL, NULL);
988 nb_desc = DIV_ROUND_UP(len, PDMA_MAX_DESC_BYTES);
989 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
994 if (!IS_ALIGNED(dma_src, 1 << PDMA_ALIGNMENT) ||
995 !IS_ALIGNED(dma_dst, 1 << PDMA_ALIGNMENT))
996 sw_desc->misaligned = true;
1000 hw_desc = sw_desc->hw_desc[i++];
1001 copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
1002 hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy);
1003 hw_desc->dsadr = dma_src;
1004 hw_desc->dtadr = dma_dst;
1009 set_updater_desc(sw_desc, flags);
1011 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1014 static struct dma_async_tx_descriptor *
1015 pxad_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
1016 unsigned int sg_len, enum dma_transfer_direction dir,
1017 unsigned long flags, void *context)
1019 struct pxad_chan *chan = to_pxad_chan(dchan);
1020 struct pxad_desc_sw *sw_desc;
1022 struct scatterlist *sg;
1024 u32 dcmd, dsadr = 0, dtadr = 0;
1025 unsigned int nb_desc = 0, i, j = 0;
1027 if ((sgl == NULL) || (sg_len == 0))
1030 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);
1031 dev_dbg(&chan->vc.chan.dev->device,
1032 "%s(): dir=%d flags=%lx\n", __func__, dir, flags);
1034 for_each_sg(sgl, sg, sg_len, i)
1035 nb_desc += DIV_ROUND_UP(sg_dma_len(sg), PDMA_MAX_DESC_BYTES);
1036 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
1040 for_each_sg(sgl, sg, sg_len, i) {
1041 dma = sg_dma_address(sg);
1042 avail = sg_dma_len(sg);
1043 sw_desc->len += avail;
1046 len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
1048 sw_desc->misaligned = true;
1050 sw_desc->hw_desc[j]->dcmd =
1051 dcmd | (PXA_DCMD_LENGTH & len);
1052 sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma;
1053 sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma;
1059 set_updater_desc(sw_desc, flags);
1061 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1064 static struct dma_async_tx_descriptor *
1065 pxad_prep_dma_cyclic(struct dma_chan *dchan,
1066 dma_addr_t buf_addr, size_t len, size_t period_len,
1067 enum dma_transfer_direction dir, unsigned long flags)
1069 struct pxad_chan *chan = to_pxad_chan(dchan);
1070 struct pxad_desc_sw *sw_desc;
1071 struct pxad_desc_hw **phw_desc;
1073 u32 dcmd, dsadr = 0, dtadr = 0;
1074 unsigned int nb_desc = 0;
1076 if (!dchan || !len || !period_len)
1078 if ((dir != DMA_DEV_TO_MEM) && (dir != DMA_MEM_TO_DEV)) {
1079 dev_err(&chan->vc.chan.dev->device,
1080 "Unsupported direction for cyclic DMA\n");
1083 /* the buffer length must be a multiple of period_len */
1084 if (len % period_len != 0 || period_len > PDMA_MAX_DESC_BYTES ||
1085 !IS_ALIGNED(period_len, 1 << PDMA_ALIGNMENT))
1088 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);
1089 dcmd |= PXA_DCMD_ENDIRQEN | (PXA_DCMD_LENGTH & period_len);
1090 dev_dbg(&chan->vc.chan.dev->device,
1091 "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n",
1092 __func__, (unsigned long)buf_addr, len, period_len, dir, flags);
1094 nb_desc = DIV_ROUND_UP(period_len, PDMA_MAX_DESC_BYTES);
1095 nb_desc *= DIV_ROUND_UP(len, period_len);
1096 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
1099 sw_desc->cyclic = true;
1102 phw_desc = sw_desc->hw_desc;
1105 phw_desc[0]->dsadr = dsadr ? dsadr : dma;
1106 phw_desc[0]->dtadr = dtadr ? dtadr : dma;
1107 phw_desc[0]->dcmd = dcmd;
1112 set_updater_desc(sw_desc, flags);
1114 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1117 static int pxad_config(struct dma_chan *dchan,
1118 struct dma_slave_config *cfg)
1120 struct pxad_chan *chan = to_pxad_chan(dchan);
1129 static int pxad_terminate_all(struct dma_chan *dchan)
1131 struct pxad_chan *chan = to_pxad_chan(dchan);
1132 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
1133 struct virt_dma_desc *vd = NULL;
1134 unsigned long flags;
1135 struct pxad_phy *phy;
1138 dev_dbg(&chan->vc.chan.dev->device,
1139 "%s(): vchan %p: terminate all\n", __func__, &chan->vc);
1141 spin_lock_irqsave(&chan->vc.lock, flags);
1142 vchan_get_all_descriptors(&chan->vc, &head);
1144 list_for_each_entry(vd, &head, node) {
1145 dev_dbg(&chan->vc.chan.dev->device,
1146 "%s(): cancelling txd %p[%x] (completed=%d)", __func__,
1147 vd, vd->tx.cookie, is_desc_completed(vd));
1152 phy_disable(chan->phy);
1153 pxad_free_phy(chan);
1155 spin_lock(&pdev->phy_lock);
1157 spin_unlock(&pdev->phy_lock);
1159 spin_unlock_irqrestore(&chan->vc.lock, flags);
1160 vchan_dma_desc_free_list(&chan->vc, &head);
1165 static unsigned int pxad_residue(struct pxad_chan *chan,
1166 dma_cookie_t cookie)
1168 struct virt_dma_desc *vd = NULL;
1169 struct pxad_desc_sw *sw_desc = NULL;
1170 struct pxad_desc_hw *hw_desc = NULL;
1171 u32 curr, start, len, end, residue = 0;
1172 unsigned long flags;
1173 bool passed = false;
1177 * If the channel does not have a phy pointer anymore, it has already
1178 * been completed. Therefore, its residue is 0.
1183 spin_lock_irqsave(&chan->vc.lock, flags);
1185 vd = vchan_find_desc(&chan->vc, cookie);
1189 sw_desc = to_pxad_sw_desc(vd);
1190 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)
1191 curr = phy_readl_relaxed(chan->phy, DSADR);
1193 curr = phy_readl_relaxed(chan->phy, DTADR);
1196 * curr has to be actually read before checking descriptor
1197 * completion, so that a curr inside a status updater
1198 * descriptor implies the following test returns true, and
1199 * preventing reordering of curr load and the test.
1202 if (is_desc_completed(vd))
1205 for (i = 0; i < sw_desc->nb_desc - 1; i++) {
1206 hw_desc = sw_desc->hw_desc[i];
1207 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)
1208 start = hw_desc->dsadr;
1210 start = hw_desc->dtadr;
1211 len = hw_desc->dcmd & PXA_DCMD_LENGTH;
1215 * 'passed' will be latched once we found the descriptor
1216 * which lies inside the boundaries of the curr
1217 * pointer. All descriptors that occur in the list
1218 * _after_ we found that partially handled descriptor
1219 * are still to be processed and are hence added to the
1220 * residual bytes counter.
1225 } else if (curr >= start && curr <= end) {
1226 residue += end - curr;
1231 residue = sw_desc->len;
1234 spin_unlock_irqrestore(&chan->vc.lock, flags);
1235 dev_dbg(&chan->vc.chan.dev->device,
1236 "%s(): txd %p[%x] sw_desc=%p: %d\n",
1237 __func__, vd, cookie, sw_desc, residue);
1241 static enum dma_status pxad_tx_status(struct dma_chan *dchan,
1242 dma_cookie_t cookie,
1243 struct dma_tx_state *txstate)
1245 struct pxad_chan *chan = to_pxad_chan(dchan);
1246 enum dma_status ret;
1248 ret = dma_cookie_status(dchan, cookie, txstate);
1249 if (likely(txstate && (ret != DMA_ERROR)))
1250 dma_set_residue(txstate, pxad_residue(chan, cookie));
1255 static void pxad_free_channels(struct dma_device *dmadev)
1257 struct pxad_chan *c, *cn;
1259 list_for_each_entry_safe(c, cn, &dmadev->channels,
1260 vc.chan.device_node) {
1261 list_del(&c->vc.chan.device_node);
1262 tasklet_kill(&c->vc.task);
1266 static int pxad_remove(struct platform_device *op)
1268 struct pxad_device *pdev = platform_get_drvdata(op);
1270 pxad_cleanup_debugfs(pdev);
1271 pxad_free_channels(&pdev->slave);
1272 dma_async_device_unregister(&pdev->slave);
1276 static int pxad_init_phys(struct platform_device *op,
1277 struct pxad_device *pdev,
1278 unsigned int nb_phy_chans)
1280 int irq0, irq, nr_irq = 0, i, ret;
1281 struct pxad_phy *phy;
1283 irq0 = platform_get_irq(op, 0);
1287 pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans,
1288 sizeof(pdev->phys[0]), GFP_KERNEL);
1292 for (i = 0; i < nb_phy_chans; i++)
1293 if (platform_get_irq(op, i) > 0)
1296 for (i = 0; i < nb_phy_chans; i++) {
1297 phy = &pdev->phys[i];
1298 phy->base = pdev->base;
1300 irq = platform_get_irq(op, i);
1301 if ((nr_irq > 1) && (irq > 0))
1302 ret = devm_request_irq(&op->dev, irq,
1304 IRQF_SHARED, "pxa-dma", phy);
1305 if ((nr_irq == 1) && (i == 0))
1306 ret = devm_request_irq(&op->dev, irq0,
1308 IRQF_SHARED, "pxa-dma", pdev);
1310 dev_err(pdev->slave.dev,
1311 "%s(): can't request irq %d:%d\n", __func__,
1320 static const struct of_device_id const pxad_dt_ids[] = {
1321 { .compatible = "marvell,pdma-1.0", },
1324 MODULE_DEVICE_TABLE(of, pxad_dt_ids);
1326 static struct dma_chan *pxad_dma_xlate(struct of_phandle_args *dma_spec,
1327 struct of_dma *ofdma)
1329 struct pxad_device *d = ofdma->of_dma_data;
1330 struct dma_chan *chan;
1332 chan = dma_get_any_slave_channel(&d->slave);
1336 to_pxad_chan(chan)->drcmr = dma_spec->args[0];
1337 to_pxad_chan(chan)->prio = dma_spec->args[1];
1342 static int pxad_init_dmadev(struct platform_device *op,
1343 struct pxad_device *pdev,
1344 unsigned int nr_phy_chans)
1348 struct pxad_chan *c;
1350 pdev->nr_chans = nr_phy_chans;
1351 INIT_LIST_HEAD(&pdev->slave.channels);
1352 pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources;
1353 pdev->slave.device_free_chan_resources = pxad_free_chan_resources;
1354 pdev->slave.device_tx_status = pxad_tx_status;
1355 pdev->slave.device_issue_pending = pxad_issue_pending;
1356 pdev->slave.device_config = pxad_config;
1357 pdev->slave.device_terminate_all = pxad_terminate_all;
1359 if (op->dev.coherent_dma_mask)
1360 dma_set_mask(&op->dev, op->dev.coherent_dma_mask);
1362 dma_set_mask(&op->dev, DMA_BIT_MASK(32));
1364 ret = pxad_init_phys(op, pdev, nr_phy_chans);
1368 for (i = 0; i < nr_phy_chans; i++) {
1369 c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL);
1372 c->vc.desc_free = pxad_free_desc;
1373 vchan_init(&c->vc, &pdev->slave);
1376 return dma_async_device_register(&pdev->slave);
1379 static int pxad_probe(struct platform_device *op)
1381 struct pxad_device *pdev;
1382 const struct of_device_id *of_id;
1383 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
1384 struct resource *iores;
1385 int ret, dma_channels = 0;
1386 const enum dma_slave_buswidth widths =
1387 DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |
1388 DMA_SLAVE_BUSWIDTH_4_BYTES;
1390 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
1394 spin_lock_init(&pdev->phy_lock);
1396 iores = platform_get_resource(op, IORESOURCE_MEM, 0);
1397 pdev->base = devm_ioremap_resource(&op->dev, iores);
1398 if (IS_ERR(pdev->base))
1399 return PTR_ERR(pdev->base);
1401 of_id = of_match_device(pxad_dt_ids, &op->dev);
1403 of_property_read_u32(op->dev.of_node, "#dma-channels",
1405 else if (pdata && pdata->dma_channels)
1406 dma_channels = pdata->dma_channels;
1408 dma_channels = 32; /* default 32 channel */
1410 dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask);
1411 dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask);
1412 dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask);
1413 dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask);
1414 pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy;
1415 pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg;
1416 pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic;
1418 pdev->slave.copy_align = PDMA_ALIGNMENT;
1419 pdev->slave.src_addr_widths = widths;
1420 pdev->slave.dst_addr_widths = widths;
1421 pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1422 pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1423 pdev->slave.descriptor_reuse = true;
1425 pdev->slave.dev = &op->dev;
1426 ret = pxad_init_dmadev(op, pdev, dma_channels);
1428 dev_err(pdev->slave.dev, "unable to register\n");
1432 if (op->dev.of_node) {
1433 /* Device-tree DMA controller registration */
1434 ret = of_dma_controller_register(op->dev.of_node,
1435 pxad_dma_xlate, pdev);
1437 dev_err(pdev->slave.dev,
1438 "of_dma_controller_register failed\n");
1443 platform_set_drvdata(op, pdev);
1444 pxad_init_debugfs(pdev);
1445 dev_info(pdev->slave.dev, "initialized %d channels\n", dma_channels);
1449 static const struct platform_device_id pxad_id_table[] = {
1454 static struct platform_driver pxad_driver = {
1457 .of_match_table = pxad_dt_ids,
1459 .id_table = pxad_id_table,
1460 .probe = pxad_probe,
1461 .remove = pxad_remove,
1464 bool pxad_filter_fn(struct dma_chan *chan, void *param)
1466 struct pxad_chan *c = to_pxad_chan(chan);
1467 struct pxad_param *p = param;
1469 if (chan->device->dev->driver != &pxad_driver.driver)
1472 c->drcmr = p->drcmr;
1477 EXPORT_SYMBOL_GPL(pxad_filter_fn);
1479 int pxad_toggle_reserved_channel(int legacy_channel)
1481 if (legacy_unavailable & (BIT(legacy_channel)))
1483 legacy_reserved ^= BIT(legacy_channel);
1486 EXPORT_SYMBOL_GPL(pxad_toggle_reserved_channel);
1488 module_platform_driver(pxad_driver);
1490 MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver");
1491 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
1492 MODULE_LICENSE("GPL v2");