1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
10 #include <linux/debugfs.h>
11 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/amba/bus.h>
22 #include <linux/scatterlist.h>
24 #include <linux/of_dma.h>
25 #include <linux/err.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/bug.h>
28 #include <linux/reset.h>
30 #include "dmaengine.h"
31 #define PL330_MAX_CHAN 8
32 #define PL330_MAX_IRQS 32
33 #define PL330_MAX_PERI 32
34 #define PL330_MAX_BURST 16
36 #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
37 #define PL330_QUIRK_PERIPH_BURST BIT(1)
39 enum pl330_cachectrl {
40 CCTRL0, /* Noncacheable and nonbufferable */
41 CCTRL1, /* Bufferable only */
42 CCTRL2, /* Cacheable, but do not allocate */
43 CCTRL3, /* Cacheable and bufferable, but do not allocate */
44 INVALID1, /* AWCACHE = 0x1000 */
46 CCTRL6, /* Cacheable write-through, allocate on writes only */
47 CCTRL7, /* Cacheable write-back, allocate on writes only */
58 /* Register and Bit field Definitions */
60 #define DS_ST_STOP 0x0
61 #define DS_ST_EXEC 0x1
62 #define DS_ST_CMISS 0x2
63 #define DS_ST_UPDTPC 0x3
65 #define DS_ST_ATBRR 0x5
66 #define DS_ST_QBUSY 0x6
68 #define DS_ST_KILL 0x8
69 #define DS_ST_CMPLT 0x9
70 #define DS_ST_FLTCMP 0xe
71 #define DS_ST_FAULT 0xf
76 #define INTSTATUS 0x28
83 #define FTC(n) (_FTC + (n)*0x4)
86 #define CS(n) (_CS + (n)*0x8)
87 #define CS_CNS (1 << 21)
90 #define CPC(n) (_CPC + (n)*0x8)
93 #define SA(n) (_SA + (n)*0x20)
96 #define DA(n) (_DA + (n)*0x20)
99 #define CC(n) (_CC + (n)*0x20)
101 #define CC_SRCINC (1 << 0)
102 #define CC_DSTINC (1 << 14)
103 #define CC_SRCPRI (1 << 8)
104 #define CC_DSTPRI (1 << 22)
105 #define CC_SRCNS (1 << 9)
106 #define CC_DSTNS (1 << 23)
107 #define CC_SRCIA (1 << 10)
108 #define CC_DSTIA (1 << 24)
109 #define CC_SRCBRSTLEN_SHFT 4
110 #define CC_DSTBRSTLEN_SHFT 18
111 #define CC_SRCBRSTSIZE_SHFT 1
112 #define CC_DSTBRSTSIZE_SHFT 15
113 #define CC_SRCCCTRL_SHFT 11
114 #define CC_SRCCCTRL_MASK 0x7
115 #define CC_DSTCCTRL_SHFT 25
116 #define CC_DRCCCTRL_MASK 0x7
117 #define CC_SWAP_SHFT 28
120 #define LC0(n) (_LC0 + (n)*0x20)
123 #define LC1(n) (_LC1 + (n)*0x20)
125 #define DBGSTATUS 0xd00
126 #define DBG_BUSY (1 << 0)
129 #define DBGINST0 0xd08
130 #define DBGINST1 0xd0c
139 #define PERIPH_ID 0xfe0
140 #define PERIPH_REV_SHIFT 20
141 #define PERIPH_REV_MASK 0xf
142 #define PERIPH_REV_R0P0 0
143 #define PERIPH_REV_R1P0 1
144 #define PERIPH_REV_R1P1 2
146 #define CR0_PERIPH_REQ_SET (1 << 0)
147 #define CR0_BOOT_EN_SET (1 << 1)
148 #define CR0_BOOT_MAN_NS (1 << 2)
149 #define CR0_NUM_CHANS_SHIFT 4
150 #define CR0_NUM_CHANS_MASK 0x7
151 #define CR0_NUM_PERIPH_SHIFT 12
152 #define CR0_NUM_PERIPH_MASK 0x1f
153 #define CR0_NUM_EVENTS_SHIFT 17
154 #define CR0_NUM_EVENTS_MASK 0x1f
156 #define CR1_ICACHE_LEN_SHIFT 0
157 #define CR1_ICACHE_LEN_MASK 0x7
158 #define CR1_NUM_ICACHELINES_SHIFT 4
159 #define CR1_NUM_ICACHELINES_MASK 0xf
161 #define CRD_DATA_WIDTH_SHIFT 0
162 #define CRD_DATA_WIDTH_MASK 0x7
163 #define CRD_WR_CAP_SHIFT 4
164 #define CRD_WR_CAP_MASK 0x7
165 #define CRD_WR_Q_DEP_SHIFT 8
166 #define CRD_WR_Q_DEP_MASK 0xf
167 #define CRD_RD_CAP_SHIFT 12
168 #define CRD_RD_CAP_MASK 0x7
169 #define CRD_RD_Q_DEP_SHIFT 16
170 #define CRD_RD_Q_DEP_MASK 0xf
171 #define CRD_DATA_BUFF_SHIFT 20
172 #define CRD_DATA_BUFF_MASK 0x3ff
175 #define DESIGNER 0x41
177 #define INTEG_CFG 0x0
178 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
180 #define PL330_STATE_STOPPED (1 << 0)
181 #define PL330_STATE_EXECUTING (1 << 1)
182 #define PL330_STATE_WFE (1 << 2)
183 #define PL330_STATE_FAULTING (1 << 3)
184 #define PL330_STATE_COMPLETING (1 << 4)
185 #define PL330_STATE_WFP (1 << 5)
186 #define PL330_STATE_KILLING (1 << 6)
187 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
188 #define PL330_STATE_CACHEMISS (1 << 8)
189 #define PL330_STATE_UPDTPC (1 << 9)
190 #define PL330_STATE_ATBARRIER (1 << 10)
191 #define PL330_STATE_QUEUEBUSY (1 << 11)
192 #define PL330_STATE_INVALID (1 << 15)
194 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
195 | PL330_STATE_WFE | PL330_STATE_FAULTING)
197 #define CMD_DMAADDH 0x54
198 #define CMD_DMAEND 0x00
199 #define CMD_DMAFLUSHP 0x35
200 #define CMD_DMAGO 0xa0
201 #define CMD_DMALD 0x04
202 #define CMD_DMALDP 0x25
203 #define CMD_DMALP 0x20
204 #define CMD_DMALPEND 0x28
205 #define CMD_DMAKILL 0x01
206 #define CMD_DMAMOV 0xbc
207 #define CMD_DMANOP 0x18
208 #define CMD_DMARMB 0x12
209 #define CMD_DMASEV 0x34
210 #define CMD_DMAST 0x08
211 #define CMD_DMASTP 0x29
212 #define CMD_DMASTZ 0x0c
213 #define CMD_DMAWFE 0x36
214 #define CMD_DMAWFP 0x30
215 #define CMD_DMAWMB 0x13
219 #define SZ_DMAFLUSHP 2
223 #define SZ_DMALPEND 2
237 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
238 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
240 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
241 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
244 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
245 * at 1byte/burst for P<->M and M<->M respectively.
246 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
247 * should be enough for P<->M and M<->M respectively.
249 #define MCODE_BUFF_PER_REQ 256
251 /* Use this _only_ to wait on transient states */
252 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254 #ifdef PL330_DEBUG_MCGEN
255 static unsigned cmd_line;
256 #define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
261 #define PL330_DBGMC_START(addr) (cmd_line = addr)
263 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264 #define PL330_DBGMC_START(addr) do {} while (0)
267 /* The number of default descriptors */
269 #define NR_DEFAULT_DESC 16
271 /* Delay for runtime PM autosuspend, ms */
272 #define PL330_AUTOSUSPEND_DELAY 20
274 /* Populated by the PL330 core driver for DMA API driver's info */
275 struct pl330_config {
277 #define DMAC_MODE_NS (1 << 0)
279 unsigned int data_bus_width:10; /* In number of bits */
280 unsigned int data_buf_dep:11;
281 unsigned int num_chan:4;
282 unsigned int num_peri:6;
284 unsigned int num_events:6;
289 * Request Configuration.
290 * The PL330 core does not modify this and uses the last
291 * working configuration if the request doesn't provide any.
293 * The Client may want to provide this info only for the
294 * first request and a request with new settings.
296 struct pl330_reqcfg {
297 /* Address Incrementing */
302 * For now, the SRC & DST protection levels
303 * and burst size/length are assumed same.
309 unsigned brst_size:3; /* in power of 2 */
311 enum pl330_cachectrl dcctl;
312 enum pl330_cachectrl scctl;
313 enum pl330_byteswap swap;
314 struct pl330_config *pcfg;
318 * One cycle of DMAC operation.
319 * There may be more than one xfer in a request.
328 /* The xfer callbacks are made with one of these arguments. */
330 /* The all xfers in the request were success. */
332 /* If req aborted due to global error. */
334 /* If req failed due to problem with Channel. */
355 struct dma_pl330_desc;
360 struct dma_pl330_desc *desc;
363 /* ToBeDone for tasklet */
371 struct pl330_thread {
374 /* If the channel is not yet acquired by any client */
377 struct pl330_dmac *dmac;
378 /* Only two at a time */
379 struct _pl330_req req[2];
380 /* Index of the last enqueued request */
382 /* Index of the last submitted request or -1 if the DMA is stopped */
386 enum pl330_dmac_state {
393 /* In the DMAC pool */
396 * Allocated to some channel during prep_xxx
397 * Also may be sitting on the work_list.
401 * Sitting on the work_list and already submitted
402 * to the PL330 core. Not more than two descriptors
403 * of a channel can be BUSY at any time.
407 * Sitting on the channel work_list but xfer done
413 struct dma_pl330_chan {
414 /* Schedule desc completion */
415 struct tasklet_struct task;
417 /* DMA-Engine Channel */
418 struct dma_chan chan;
420 /* List of submitted descriptors */
421 struct list_head submitted_list;
422 /* List of issued descriptors */
423 struct list_head work_list;
424 /* List of completed descriptors */
425 struct list_head completed_list;
427 /* Pointer to the DMAC that manages this channel,
428 * NULL if the channel is available to be acquired.
429 * As the parent, this DMAC also provides descriptors
432 struct pl330_dmac *dmac;
434 /* To protect channel manipulation */
438 * Hardware channel thread of PL330 DMAC. NULL if the channel is
441 struct pl330_thread *thread;
443 /* For D-to-M and M-to-D channels */
444 int burst_sz; /* the peripheral fifo width */
445 int burst_len; /* the number of burst */
446 phys_addr_t fifo_addr;
447 /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
449 enum dma_data_direction dir;
450 struct dma_slave_config slave_config;
452 /* for cyclic capability */
455 /* for runtime pm tracking */
460 /* DMA-Engine Device */
461 struct dma_device ddma;
463 /* Holds info about sg limitations */
464 struct device_dma_parameters dma_parms;
466 /* Pool of descriptors available for the DMAC's channels */
467 struct list_head desc_pool;
468 /* To protect desc_pool manipulation */
469 spinlock_t pool_lock;
471 /* Size of MicroCode buffers for each channel. */
473 /* ioremap'ed address of PL330 registers. */
475 /* Populated by the PL330 core driver during pl330_add */
476 struct pl330_config pcfg;
479 /* Maximum possible events/irqs */
481 /* BUS address of MicroCode buffer */
482 dma_addr_t mcode_bus;
483 /* CPU address of MicroCode buffer */
485 /* List of all Channel threads */
486 struct pl330_thread *channels;
487 /* Pointer to the MANAGER thread */
488 struct pl330_thread *manager;
489 /* To handle bad news in interrupt */
490 struct tasklet_struct tasks;
491 struct _pl330_tbd dmac_tbd;
492 /* State of DMAC operation */
493 enum pl330_dmac_state state;
494 /* Holds list of reqs with due callbacks */
495 struct list_head req_done;
497 /* Peripheral channels connected to this DMAC */
498 unsigned int num_peripherals;
499 struct dma_pl330_chan *peripherals; /* keep at end */
502 struct reset_control *rstc;
503 struct reset_control *rstc_ocp;
506 static struct pl330_of_quirks {
511 .quirk = "arm,pl330-broken-no-flushp",
512 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
515 .quirk = "arm,pl330-periph-burst",
516 .id = PL330_QUIRK_PERIPH_BURST,
520 struct dma_pl330_desc {
521 /* To attach to a queue as child */
522 struct list_head node;
524 /* Descriptor for the DMA Engine API */
525 struct dma_async_tx_descriptor txd;
527 /* Xfer for PL330 core */
528 struct pl330_xfer px;
530 struct pl330_reqcfg rqcfg;
532 enum desc_status status;
537 /* The channel which currently holds this desc */
538 struct dma_pl330_chan *pchan;
540 enum dma_transfer_direction rqtype;
541 /* Index of peripheral for the xfer. */
543 /* Hook to attach to DMAC's list of reqs with due callback */
544 struct list_head rqd;
549 struct dma_pl330_desc *desc;
552 static int pl330_config_write(struct dma_chan *chan,
553 struct dma_slave_config *slave_config,
554 enum dma_transfer_direction direction);
556 static inline bool _queue_full(struct pl330_thread *thrd)
558 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
561 static inline bool is_manager(struct pl330_thread *thrd)
563 return thrd->dmac->manager == thrd;
566 /* If manager of the thread is in Non-Secure mode */
567 static inline bool _manager_ns(struct pl330_thread *thrd)
569 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
572 static inline u32 get_revision(u32 periph_id)
574 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
577 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
584 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
589 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
594 buf[0] = CMD_DMAFLUSHP;
600 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
605 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
613 buf[0] |= (0 << 1) | (1 << 0);
614 else if (cond == BURST)
615 buf[0] |= (1 << 1) | (1 << 0);
617 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
618 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
623 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
624 enum pl330_cond cond, u8 peri)
638 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
639 cond == SINGLE ? 'S' : 'B', peri >> 3);
644 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
645 unsigned loop, u8 cnt)
655 cnt--; /* DMAC increments by 1 internally */
658 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
664 enum pl330_cond cond;
670 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
671 const struct _arg_LPEND *arg)
673 enum pl330_cond cond = arg->cond;
674 bool forever = arg->forever;
675 unsigned loop = arg->loop;
676 u8 bjump = arg->bjump;
681 buf[0] = CMD_DMALPEND;
690 buf[0] |= (0 << 1) | (1 << 0);
691 else if (cond == BURST)
692 buf[0] |= (1 << 1) | (1 << 0);
696 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
697 forever ? "FE" : "END",
698 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
705 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
710 buf[0] = CMD_DMAKILL;
715 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
716 enum dmamov_dst dst, u32 val)
728 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
729 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
734 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
741 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
746 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
757 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
762 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
770 buf[0] |= (0 << 1) | (1 << 0);
771 else if (cond == BURST)
772 buf[0] |= (1 << 1) | (1 << 0);
774 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
775 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
780 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
781 enum pl330_cond cond, u8 peri)
795 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
796 cond == SINGLE ? 'S' : 'B', peri >> 3);
801 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
802 enum pl330_cond cond, u8 peri)
810 buf[0] |= (0 << 1) | (0 << 0);
811 else if (cond == BURST)
812 buf[0] |= (1 << 1) | (0 << 0);
814 buf[0] |= (0 << 1) | (1 << 0);
820 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
821 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
826 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
833 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
844 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
845 const struct _arg_GO *arg)
848 u32 addr = arg->addr;
849 unsigned ns = arg->ns;
865 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
867 /* Returns Time-Out */
868 static bool _until_dmac_idle(struct pl330_thread *thrd)
870 void __iomem *regs = thrd->dmac->base;
871 unsigned long loops = msecs_to_loops(5);
874 /* Until Manager is Idle */
875 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
887 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
888 u8 insn[], bool as_manager)
890 void __iomem *regs = thrd->dmac->base;
893 /* If timed out due to halted state-machine */
894 if (_until_dmac_idle(thrd)) {
895 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
899 val = (insn[0] << 16) | (insn[1] << 24);
902 val |= (thrd->id << 8); /* Channel Number */
904 writel(val, regs + DBGINST0);
906 val = le32_to_cpu(*((__le32 *)&insn[2]));
907 writel(val, regs + DBGINST1);
910 writel(0, regs + DBGCMD);
913 static inline u32 _state(struct pl330_thread *thrd)
915 void __iomem *regs = thrd->dmac->base;
918 if (is_manager(thrd))
919 val = readl(regs + DS) & 0xf;
921 val = readl(regs + CS(thrd->id)) & 0xf;
925 return PL330_STATE_STOPPED;
927 return PL330_STATE_EXECUTING;
929 return PL330_STATE_CACHEMISS;
931 return PL330_STATE_UPDTPC;
933 return PL330_STATE_WFE;
935 return PL330_STATE_FAULTING;
937 if (is_manager(thrd))
938 return PL330_STATE_INVALID;
940 return PL330_STATE_ATBARRIER;
942 if (is_manager(thrd))
943 return PL330_STATE_INVALID;
945 return PL330_STATE_QUEUEBUSY;
947 if (is_manager(thrd))
948 return PL330_STATE_INVALID;
950 return PL330_STATE_WFP;
952 if (is_manager(thrd))
953 return PL330_STATE_INVALID;
955 return PL330_STATE_KILLING;
957 if (is_manager(thrd))
958 return PL330_STATE_INVALID;
960 return PL330_STATE_COMPLETING;
962 if (is_manager(thrd))
963 return PL330_STATE_INVALID;
965 return PL330_STATE_FAULT_COMPLETING;
967 return PL330_STATE_INVALID;
971 static void _stop(struct pl330_thread *thrd)
973 void __iomem *regs = thrd->dmac->base;
974 u8 insn[6] = {0, 0, 0, 0, 0, 0};
975 u32 inten = readl(regs + INTEN);
977 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
978 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
980 /* Return if nothing needs to be done */
981 if (_state(thrd) == PL330_STATE_COMPLETING
982 || _state(thrd) == PL330_STATE_KILLING
983 || _state(thrd) == PL330_STATE_STOPPED)
988 _execute_DBGINSN(thrd, insn, is_manager(thrd));
990 /* clear the event */
991 if (inten & (1 << thrd->ev))
992 writel(1 << thrd->ev, regs + INTCLR);
993 /* Stop generating interrupts for SEV */
994 writel(inten & ~(1 << thrd->ev), regs + INTEN);
997 /* Start doing req 'idx' of thread 'thrd' */
998 static bool _trigger(struct pl330_thread *thrd)
1000 void __iomem *regs = thrd->dmac->base;
1001 struct _pl330_req *req;
1002 struct dma_pl330_desc *desc;
1005 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1008 /* Return if already ACTIVE */
1009 if (_state(thrd) != PL330_STATE_STOPPED)
1012 idx = 1 - thrd->lstenq;
1013 if (thrd->req[idx].desc != NULL) {
1014 req = &thrd->req[idx];
1017 if (thrd->req[idx].desc != NULL)
1018 req = &thrd->req[idx];
1023 /* Return if no request */
1027 /* Return if req is running */
1028 if (idx == thrd->req_running)
1033 ns = desc->rqcfg.nonsecure ? 1 : 0;
1035 /* See 'Abort Sources' point-4 at Page 2-25 */
1036 if (_manager_ns(thrd) && !ns)
1037 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1038 __func__, __LINE__);
1041 go.addr = req->mc_bus;
1043 _emit_GO(0, insn, &go);
1045 /* Set to generate interrupts for SEV */
1046 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1048 /* Only manager can execute GO */
1049 _execute_DBGINSN(thrd, insn, true);
1051 thrd->req_running = idx;
1056 static bool _start(struct pl330_thread *thrd)
1058 switch (_state(thrd)) {
1059 case PL330_STATE_FAULT_COMPLETING:
1060 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1062 if (_state(thrd) == PL330_STATE_KILLING)
1063 UNTIL(thrd, PL330_STATE_STOPPED)
1066 case PL330_STATE_FAULTING:
1070 case PL330_STATE_KILLING:
1071 case PL330_STATE_COMPLETING:
1072 UNTIL(thrd, PL330_STATE_STOPPED)
1075 case PL330_STATE_STOPPED:
1076 return _trigger(thrd);
1078 case PL330_STATE_WFP:
1079 case PL330_STATE_QUEUEBUSY:
1080 case PL330_STATE_ATBARRIER:
1081 case PL330_STATE_UPDTPC:
1082 case PL330_STATE_CACHEMISS:
1083 case PL330_STATE_EXECUTING:
1086 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1092 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1093 const struct _xfer_spec *pxs, int cyc)
1096 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1098 /* check lock-up free version */
1099 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1101 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1102 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1106 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1107 off += _emit_RMB(dry_run, &buf[off]);
1108 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1109 off += _emit_WMB(dry_run, &buf[off]);
1116 static u32 _emit_load(unsigned int dry_run, u8 buf[],
1117 enum pl330_cond cond, enum dma_transfer_direction direction,
1122 switch (direction) {
1123 case DMA_MEM_TO_MEM:
1125 case DMA_MEM_TO_DEV:
1126 off += _emit_LD(dry_run, &buf[off], cond);
1129 case DMA_DEV_TO_MEM:
1130 if (cond == ALWAYS) {
1131 off += _emit_LDP(dry_run, &buf[off], SINGLE,
1133 off += _emit_LDP(dry_run, &buf[off], BURST,
1136 off += _emit_LDP(dry_run, &buf[off], cond,
1142 /* this code should be unreachable */
1150 static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
1151 enum pl330_cond cond, enum dma_transfer_direction direction,
1156 switch (direction) {
1157 case DMA_MEM_TO_MEM:
1159 case DMA_DEV_TO_MEM:
1160 off += _emit_ST(dry_run, &buf[off], cond);
1163 case DMA_MEM_TO_DEV:
1164 if (cond == ALWAYS) {
1165 off += _emit_STP(dry_run, &buf[off], SINGLE,
1167 off += _emit_STP(dry_run, &buf[off], BURST,
1170 off += _emit_STP(dry_run, &buf[off], cond,
1176 /* this code should be unreachable */
1184 static inline int _ldst_peripheral(struct pl330_dmac *pl330,
1185 unsigned dry_run, u8 buf[],
1186 const struct _xfer_spec *pxs, int cyc,
1187 enum pl330_cond cond)
1192 * do FLUSHP at beginning to clear any stale dma requests before the
1195 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1196 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1198 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1199 off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1201 off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1208 static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1209 const struct _xfer_spec *pxs, int cyc)
1212 enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
1214 if (pl330->quirks & PL330_QUIRK_PERIPH_BURST)
1217 switch (pxs->desc->rqtype) {
1218 case DMA_MEM_TO_DEV:
1220 case DMA_DEV_TO_MEM:
1221 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
1225 case DMA_MEM_TO_MEM:
1226 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1230 /* this code should be unreachable */
1239 * only the unaligned burst transfers have the dregs.
1240 * so, still transfer dregs with a reduced size burst
1241 * for mem-to-mem, mem-to-dev or dev-to-mem.
1243 static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
1244 const struct _xfer_spec *pxs, int transfer_length)
1249 if (transfer_length == 0)
1253 * dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) /
1255 * the dregs len must be smaller than burst len,
1256 * so, for higher efficiency, we can modify CCR
1257 * to use a reduced size burst len for the dregs.
1259 dregs_ccr = pxs->ccr;
1260 dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
1261 (0xf << CC_DSTBRSTLEN_SHFT));
1262 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1263 CC_SRCBRSTLEN_SHFT);
1264 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1265 CC_DSTBRSTLEN_SHFT);
1267 switch (pxs->desc->rqtype) {
1268 case DMA_MEM_TO_DEV:
1270 case DMA_DEV_TO_MEM:
1271 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1272 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
1276 case DMA_MEM_TO_MEM:
1277 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1278 off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
1282 /* this code should be unreachable */
1290 /* Returns bytes consumed and updates bursts */
1291 static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1292 unsigned long *bursts, const struct _xfer_spec *pxs)
1294 int cyc, cycmax, szlp, szlpend, szbrst, off;
1295 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1296 struct _arg_LPEND lpend;
1299 return _bursts(pl330, dry_run, buf, pxs, 1);
1301 /* Max iterations possible in DMALP is 256 */
1302 if (*bursts >= 256*256) {
1305 cyc = *bursts / lcnt1 / lcnt0;
1306 } else if (*bursts > 256) {
1308 lcnt0 = *bursts / lcnt1;
1316 szlp = _emit_LP(1, buf, 0, 0);
1317 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1319 lpend.cond = ALWAYS;
1320 lpend.forever = false;
1323 szlpend = _emit_LPEND(1, buf, &lpend);
1331 * Max bursts that we can unroll due to limit on the
1332 * size of backward jump that can be encoded in DMALPEND
1333 * which is 8-bits and hence 255
1335 cycmax = (255 - (szlp + szlpend)) / szbrst;
1337 cyc = (cycmax < cyc) ? cycmax : cyc;
1342 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1346 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1349 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1351 lpend.cond = ALWAYS;
1352 lpend.forever = false;
1354 lpend.bjump = off - ljmp1;
1355 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1358 lpend.cond = ALWAYS;
1359 lpend.forever = false;
1361 lpend.bjump = off - ljmp0;
1362 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1365 *bursts = lcnt1 * cyc;
1372 static inline int _setup_loops(struct pl330_dmac *pl330,
1373 unsigned dry_run, u8 buf[],
1374 const struct _xfer_spec *pxs)
1376 struct pl330_xfer *x = &pxs->desc->px;
1378 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1379 int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
1385 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1388 off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1393 static inline int _setup_xfer(struct pl330_dmac *pl330,
1394 unsigned dry_run, u8 buf[],
1395 const struct _xfer_spec *pxs)
1397 struct pl330_xfer *x = &pxs->desc->px;
1400 /* DMAMOV SAR, x->src_addr */
1401 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1402 /* DMAMOV DAR, x->dst_addr */
1403 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1406 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1412 * A req is a sequence of one or more xfer units.
1413 * Returns the number of bytes taken to setup the MC for the req.
1415 static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1416 struct pl330_thread *thrd, unsigned index,
1417 struct _xfer_spec *pxs)
1419 struct _pl330_req *req = &thrd->req[index];
1420 u8 *buf = req->mc_cpu;
1423 PL330_DBGMC_START(req->mc_bus);
1425 /* DMAMOV CCR, ccr */
1426 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1428 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1430 /* DMASEV peripheral/event */
1431 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1433 off += _emit_END(dry_run, &buf[off]);
1438 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1448 /* We set same protection levels for Src and DST for now */
1449 if (rqc->privileged)
1450 ccr |= CC_SRCPRI | CC_DSTPRI;
1452 ccr |= CC_SRCNS | CC_DSTNS;
1453 if (rqc->insnaccess)
1454 ccr |= CC_SRCIA | CC_DSTIA;
1456 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1457 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1459 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1460 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1462 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1463 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1465 ccr |= (rqc->swap << CC_SWAP_SHFT);
1471 * Submit a list of xfers after which the client wants notification.
1472 * Client is not notified after each xfer unit, just once after all
1473 * xfer units are done or some error occurs.
1475 static int pl330_submit_req(struct pl330_thread *thrd,
1476 struct dma_pl330_desc *desc)
1478 struct pl330_dmac *pl330 = thrd->dmac;
1479 struct _xfer_spec xs;
1480 unsigned long flags;
1485 switch (desc->rqtype) {
1486 case DMA_MEM_TO_DEV:
1489 case DMA_DEV_TO_MEM:
1492 case DMA_MEM_TO_MEM:
1499 if (pl330->state == DYING
1500 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1501 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1502 __func__, __LINE__);
1506 /* If request for non-existing peripheral */
1507 if (desc->rqtype != DMA_MEM_TO_MEM &&
1508 desc->peri >= pl330->pcfg.num_peri) {
1509 dev_info(thrd->dmac->ddma.dev,
1510 "%s:%d Invalid peripheral(%u)!\n",
1511 __func__, __LINE__, desc->peri);
1515 spin_lock_irqsave(&pl330->lock, flags);
1517 if (_queue_full(thrd)) {
1522 /* Prefer Secure Channel */
1523 if (!_manager_ns(thrd))
1524 desc->rqcfg.nonsecure = 0;
1526 desc->rqcfg.nonsecure = 1;
1528 ccr = _prepare_ccr(&desc->rqcfg);
1530 idx = thrd->req[0].desc == NULL ? 0 : 1;
1535 /* First dry run to check if req is acceptable */
1536 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1540 if (ret > pl330->mcbufsz / 2) {
1541 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1542 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1547 /* Hook the request */
1549 thrd->req[idx].desc = desc;
1550 _setup_req(pl330, 0, thrd, idx, &xs);
1555 spin_unlock_irqrestore(&pl330->lock, flags);
1560 static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1562 struct dma_pl330_chan *pch;
1563 unsigned long flags;
1570 /* If desc aborted */
1574 spin_lock_irqsave(&pch->lock, flags);
1576 desc->status = DONE;
1578 spin_unlock_irqrestore(&pch->lock, flags);
1580 tasklet_schedule(&pch->task);
1583 static void pl330_dotask(unsigned long data)
1585 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1586 unsigned long flags;
1589 spin_lock_irqsave(&pl330->lock, flags);
1591 /* The DMAC itself gone nuts */
1592 if (pl330->dmac_tbd.reset_dmac) {
1593 pl330->state = DYING;
1594 /* Reset the manager too */
1595 pl330->dmac_tbd.reset_mngr = true;
1596 /* Clear the reset flag */
1597 pl330->dmac_tbd.reset_dmac = false;
1600 if (pl330->dmac_tbd.reset_mngr) {
1601 _stop(pl330->manager);
1602 /* Reset all channels */
1603 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1604 /* Clear the reset flag */
1605 pl330->dmac_tbd.reset_mngr = false;
1608 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1610 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1611 struct pl330_thread *thrd = &pl330->channels[i];
1612 void __iomem *regs = pl330->base;
1613 enum pl330_op_err err;
1617 if (readl(regs + FSC) & (1 << thrd->id))
1618 err = PL330_ERR_FAIL;
1620 err = PL330_ERR_ABORT;
1622 spin_unlock_irqrestore(&pl330->lock, flags);
1623 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1624 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1625 spin_lock_irqsave(&pl330->lock, flags);
1627 thrd->req[0].desc = NULL;
1628 thrd->req[1].desc = NULL;
1629 thrd->req_running = -1;
1631 /* Clear the reset flag */
1632 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1636 spin_unlock_irqrestore(&pl330->lock, flags);
1641 /* Returns 1 if state was updated, 0 otherwise */
1642 static int pl330_update(struct pl330_dmac *pl330)
1644 struct dma_pl330_desc *descdone;
1645 unsigned long flags;
1648 int id, ev, ret = 0;
1652 spin_lock_irqsave(&pl330->lock, flags);
1654 val = readl(regs + FSM) & 0x1;
1656 pl330->dmac_tbd.reset_mngr = true;
1658 pl330->dmac_tbd.reset_mngr = false;
1660 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1661 pl330->dmac_tbd.reset_chan |= val;
1664 while (i < pl330->pcfg.num_chan) {
1665 if (val & (1 << i)) {
1666 dev_info(pl330->ddma.dev,
1667 "Reset Channel-%d\t CS-%x FTC-%x\n",
1668 i, readl(regs + CS(i)),
1669 readl(regs + FTC(i)));
1670 _stop(&pl330->channels[i]);
1676 /* Check which event happened i.e, thread notified */
1677 val = readl(regs + ES);
1678 if (pl330->pcfg.num_events < 32
1679 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1680 pl330->dmac_tbd.reset_dmac = true;
1681 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1687 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1688 if (val & (1 << ev)) { /* Event occurred */
1689 struct pl330_thread *thrd;
1690 u32 inten = readl(regs + INTEN);
1693 /* Clear the event */
1694 if (inten & (1 << ev))
1695 writel(1 << ev, regs + INTCLR);
1699 id = pl330->events[ev];
1701 thrd = &pl330->channels[id];
1703 active = thrd->req_running;
1704 if (active == -1) /* Aborted */
1707 /* Detach the req */
1708 descdone = thrd->req[active].desc;
1709 thrd->req[active].desc = NULL;
1711 thrd->req_running = -1;
1713 /* Get going again ASAP */
1716 /* For now, just make a list of callbacks to be done */
1717 list_add_tail(&descdone->rqd, &pl330->req_done);
1721 /* Now that we are in no hurry, do the callbacks */
1722 while (!list_empty(&pl330->req_done)) {
1723 descdone = list_first_entry(&pl330->req_done,
1724 struct dma_pl330_desc, rqd);
1725 list_del(&descdone->rqd);
1726 spin_unlock_irqrestore(&pl330->lock, flags);
1727 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1728 spin_lock_irqsave(&pl330->lock, flags);
1732 spin_unlock_irqrestore(&pl330->lock, flags);
1734 if (pl330->dmac_tbd.reset_dmac
1735 || pl330->dmac_tbd.reset_mngr
1736 || pl330->dmac_tbd.reset_chan) {
1738 tasklet_schedule(&pl330->tasks);
1744 /* Reserve an event */
1745 static inline int _alloc_event(struct pl330_thread *thrd)
1747 struct pl330_dmac *pl330 = thrd->dmac;
1750 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1751 if (pl330->events[ev] == -1) {
1752 pl330->events[ev] = thrd->id;
1759 static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1761 return pl330->pcfg.irq_ns & (1 << i);
1764 /* Upon success, returns IdentityToken for the
1765 * allocated channel, NULL otherwise.
1767 static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1769 struct pl330_thread *thrd = NULL;
1772 if (pl330->state == DYING)
1775 chans = pl330->pcfg.num_chan;
1777 for (i = 0; i < chans; i++) {
1778 thrd = &pl330->channels[i];
1779 if ((thrd->free) && (!_manager_ns(thrd) ||
1780 _chan_ns(pl330, i))) {
1781 thrd->ev = _alloc_event(thrd);
1782 if (thrd->ev >= 0) {
1785 thrd->req[0].desc = NULL;
1786 thrd->req[1].desc = NULL;
1787 thrd->req_running = -1;
1797 /* Release an event */
1798 static inline void _free_event(struct pl330_thread *thrd, int ev)
1800 struct pl330_dmac *pl330 = thrd->dmac;
1802 /* If the event is valid and was held by the thread */
1803 if (ev >= 0 && ev < pl330->pcfg.num_events
1804 && pl330->events[ev] == thrd->id)
1805 pl330->events[ev] = -1;
1808 static void pl330_release_channel(struct pl330_thread *thrd)
1810 if (!thrd || thrd->free)
1815 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1816 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1818 _free_event(thrd, thrd->ev);
1822 /* Initialize the structure for PL330 configuration, that can be used
1823 * by the client driver the make best use of the DMAC
1825 static void read_dmac_config(struct pl330_dmac *pl330)
1827 void __iomem *regs = pl330->base;
1830 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1831 val &= CRD_DATA_WIDTH_MASK;
1832 pl330->pcfg.data_bus_width = 8 * (1 << val);
1834 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1835 val &= CRD_DATA_BUFF_MASK;
1836 pl330->pcfg.data_buf_dep = val + 1;
1838 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1839 val &= CR0_NUM_CHANS_MASK;
1841 pl330->pcfg.num_chan = val;
1843 val = readl(regs + CR0);
1844 if (val & CR0_PERIPH_REQ_SET) {
1845 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1847 pl330->pcfg.num_peri = val;
1848 pl330->pcfg.peri_ns = readl(regs + CR4);
1850 pl330->pcfg.num_peri = 0;
1853 val = readl(regs + CR0);
1854 if (val & CR0_BOOT_MAN_NS)
1855 pl330->pcfg.mode |= DMAC_MODE_NS;
1857 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1859 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1860 val &= CR0_NUM_EVENTS_MASK;
1862 pl330->pcfg.num_events = val;
1864 pl330->pcfg.irq_ns = readl(regs + CR3);
1867 static inline void _reset_thread(struct pl330_thread *thrd)
1869 struct pl330_dmac *pl330 = thrd->dmac;
1871 thrd->req[0].mc_cpu = pl330->mcode_cpu
1872 + (thrd->id * pl330->mcbufsz);
1873 thrd->req[0].mc_bus = pl330->mcode_bus
1874 + (thrd->id * pl330->mcbufsz);
1875 thrd->req[0].desc = NULL;
1877 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1878 + pl330->mcbufsz / 2;
1879 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1880 + pl330->mcbufsz / 2;
1881 thrd->req[1].desc = NULL;
1883 thrd->req_running = -1;
1886 static int dmac_alloc_threads(struct pl330_dmac *pl330)
1888 int chans = pl330->pcfg.num_chan;
1889 struct pl330_thread *thrd;
1892 /* Allocate 1 Manager and 'chans' Channel threads */
1893 pl330->channels = kcalloc(1 + chans, sizeof(*thrd),
1895 if (!pl330->channels)
1898 /* Init Channel threads */
1899 for (i = 0; i < chans; i++) {
1900 thrd = &pl330->channels[i];
1903 _reset_thread(thrd);
1907 /* MANAGER is indexed at the end */
1908 thrd = &pl330->channels[chans];
1912 pl330->manager = thrd;
1917 static int dmac_alloc_resources(struct pl330_dmac *pl330)
1919 int chans = pl330->pcfg.num_chan;
1923 * Alloc MicroCode buffer for 'chans' Channel threads.
1924 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1926 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1927 chans * pl330->mcbufsz,
1928 &pl330->mcode_bus, GFP_KERNEL,
1929 DMA_ATTR_PRIVILEGED);
1930 if (!pl330->mcode_cpu) {
1931 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1932 __func__, __LINE__);
1936 ret = dmac_alloc_threads(pl330);
1938 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1939 __func__, __LINE__);
1940 dma_free_attrs(pl330->ddma.dev,
1941 chans * pl330->mcbufsz,
1942 pl330->mcode_cpu, pl330->mcode_bus,
1943 DMA_ATTR_PRIVILEGED);
1950 static int pl330_add(struct pl330_dmac *pl330)
1954 /* Check if we can handle this DMAC */
1955 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1956 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1957 pl330->pcfg.periph_id);
1961 /* Read the configuration of the DMAC */
1962 read_dmac_config(pl330);
1964 if (pl330->pcfg.num_events == 0) {
1965 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1966 __func__, __LINE__);
1970 spin_lock_init(&pl330->lock);
1972 INIT_LIST_HEAD(&pl330->req_done);
1974 /* Use default MC buffer size if not provided */
1975 if (!pl330->mcbufsz)
1976 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1978 /* Mark all events as free */
1979 for (i = 0; i < pl330->pcfg.num_events; i++)
1980 pl330->events[i] = -1;
1982 /* Allocate resources needed by the DMAC */
1983 ret = dmac_alloc_resources(pl330);
1985 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1989 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1991 pl330->state = INIT;
1996 static int dmac_free_threads(struct pl330_dmac *pl330)
1998 struct pl330_thread *thrd;
2001 /* Release Channel threads */
2002 for (i = 0; i < pl330->pcfg.num_chan; i++) {
2003 thrd = &pl330->channels[i];
2004 pl330_release_channel(thrd);
2008 kfree(pl330->channels);
2013 static void pl330_del(struct pl330_dmac *pl330)
2015 pl330->state = UNINIT;
2017 tasklet_kill(&pl330->tasks);
2019 /* Free DMAC resources */
2020 dmac_free_threads(pl330);
2022 dma_free_attrs(pl330->ddma.dev,
2023 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
2024 pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
2027 /* forward declaration */
2028 static struct amba_driver pl330_driver;
2030 static inline struct dma_pl330_chan *
2031 to_pchan(struct dma_chan *ch)
2036 return container_of(ch, struct dma_pl330_chan, chan);
2039 static inline struct dma_pl330_desc *
2040 to_desc(struct dma_async_tx_descriptor *tx)
2042 return container_of(tx, struct dma_pl330_desc, txd);
2045 static inline void fill_queue(struct dma_pl330_chan *pch)
2047 struct dma_pl330_desc *desc;
2050 list_for_each_entry(desc, &pch->work_list, node) {
2052 /* If already submitted */
2053 if (desc->status == BUSY)
2056 ret = pl330_submit_req(pch->thread, desc);
2058 desc->status = BUSY;
2059 } else if (ret == -EAGAIN) {
2060 /* QFull or DMAC Dying */
2063 /* Unacceptable request */
2064 desc->status = DONE;
2065 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2066 __func__, __LINE__, desc->txd.cookie);
2067 tasklet_schedule(&pch->task);
2072 static void pl330_tasklet(unsigned long data)
2074 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2075 struct dma_pl330_desc *desc, *_dt;
2076 unsigned long flags;
2077 bool power_down = false;
2079 spin_lock_irqsave(&pch->lock, flags);
2081 /* Pick up ripe tomatoes */
2082 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2083 if (desc->status == DONE) {
2085 dma_cookie_complete(&desc->txd);
2086 list_move_tail(&desc->node, &pch->completed_list);
2089 /* Try to submit a req imm. next to the last completed cookie */
2092 if (list_empty(&pch->work_list)) {
2093 spin_lock(&pch->thread->dmac->lock);
2095 spin_unlock(&pch->thread->dmac->lock);
2097 pch->active = false;
2099 /* Make sure the PL330 Channel thread is active */
2100 spin_lock(&pch->thread->dmac->lock);
2101 _start(pch->thread);
2102 spin_unlock(&pch->thread->dmac->lock);
2105 while (!list_empty(&pch->completed_list)) {
2106 struct dmaengine_desc_callback cb;
2108 desc = list_first_entry(&pch->completed_list,
2109 struct dma_pl330_desc, node);
2111 dmaengine_desc_get_callback(&desc->txd, &cb);
2114 desc->status = PREP;
2115 list_move_tail(&desc->node, &pch->work_list);
2118 spin_lock(&pch->thread->dmac->lock);
2119 _start(pch->thread);
2120 spin_unlock(&pch->thread->dmac->lock);
2124 desc->status = FREE;
2125 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2128 dma_descriptor_unmap(&desc->txd);
2130 if (dmaengine_desc_callback_valid(&cb)) {
2131 spin_unlock_irqrestore(&pch->lock, flags);
2132 dmaengine_desc_callback_invoke(&cb, NULL);
2133 spin_lock_irqsave(&pch->lock, flags);
2136 spin_unlock_irqrestore(&pch->lock, flags);
2138 /* If work list empty, power down */
2140 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2141 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2145 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2146 struct of_dma *ofdma)
2148 int count = dma_spec->args_count;
2149 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2150 unsigned int chan_id;
2158 chan_id = dma_spec->args[0];
2159 if (chan_id >= pl330->num_peripherals)
2162 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2165 static int pl330_alloc_chan_resources(struct dma_chan *chan)
2167 struct dma_pl330_chan *pch = to_pchan(chan);
2168 struct pl330_dmac *pl330 = pch->dmac;
2169 unsigned long flags;
2171 spin_lock_irqsave(&pl330->lock, flags);
2173 dma_cookie_init(chan);
2174 pch->cyclic = false;
2176 pch->thread = pl330_request_channel(pl330);
2178 spin_unlock_irqrestore(&pl330->lock, flags);
2182 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2184 spin_unlock_irqrestore(&pl330->lock, flags);
2190 * We need the data direction between the DMAC (the dma-mapping "device") and
2191 * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
2193 static enum dma_data_direction
2194 pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
2197 case DMA_MEM_TO_DEV:
2198 return DMA_FROM_DEVICE;
2199 case DMA_DEV_TO_MEM:
2200 return DMA_TO_DEVICE;
2201 case DMA_DEV_TO_DEV:
2202 return DMA_BIDIRECTIONAL;
2208 static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
2210 if (pch->dir != DMA_NONE)
2211 dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
2212 1 << pch->burst_sz, pch->dir, 0);
2213 pch->dir = DMA_NONE;
2217 static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
2218 enum dma_transfer_direction dir)
2220 struct device *dev = pch->chan.device->dev;
2221 enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
2223 /* Already mapped for this config? */
2224 if (pch->dir == dma_dir)
2227 pl330_unprep_slave_fifo(pch);
2228 pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
2229 1 << pch->burst_sz, dma_dir, 0);
2230 if (dma_mapping_error(dev, pch->fifo_dma))
2237 static int fixup_burst_len(int max_burst_len, int quirks)
2239 if (max_burst_len > PL330_MAX_BURST)
2240 return PL330_MAX_BURST;
2241 else if (max_burst_len < 1)
2244 return max_burst_len;
2247 static int pl330_config_write(struct dma_chan *chan,
2248 struct dma_slave_config *slave_config,
2249 enum dma_transfer_direction direction)
2251 struct dma_pl330_chan *pch = to_pchan(chan);
2253 pl330_unprep_slave_fifo(pch);
2254 if (direction == DMA_MEM_TO_DEV) {
2255 if (slave_config->dst_addr)
2256 pch->fifo_addr = slave_config->dst_addr;
2257 if (slave_config->dst_addr_width)
2258 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2259 pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
2261 } else if (direction == DMA_DEV_TO_MEM) {
2262 if (slave_config->src_addr)
2263 pch->fifo_addr = slave_config->src_addr;
2264 if (slave_config->src_addr_width)
2265 pch->burst_sz = __ffs(slave_config->src_addr_width);
2266 pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
2273 static int pl330_config(struct dma_chan *chan,
2274 struct dma_slave_config *slave_config)
2276 struct dma_pl330_chan *pch = to_pchan(chan);
2278 memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
2283 static int pl330_terminate_all(struct dma_chan *chan)
2285 struct dma_pl330_chan *pch = to_pchan(chan);
2286 struct dma_pl330_desc *desc;
2287 unsigned long flags;
2288 struct pl330_dmac *pl330 = pch->dmac;
2289 bool power_down = false;
2291 pm_runtime_get_sync(pl330->ddma.dev);
2292 spin_lock_irqsave(&pch->lock, flags);
2294 spin_lock(&pl330->lock);
2296 pch->thread->req[0].desc = NULL;
2297 pch->thread->req[1].desc = NULL;
2298 pch->thread->req_running = -1;
2299 spin_unlock(&pl330->lock);
2301 power_down = pch->active;
2302 pch->active = false;
2304 /* Mark all desc done */
2305 list_for_each_entry(desc, &pch->submitted_list, node) {
2306 desc->status = FREE;
2307 dma_cookie_complete(&desc->txd);
2310 list_for_each_entry(desc, &pch->work_list , node) {
2311 desc->status = FREE;
2312 dma_cookie_complete(&desc->txd);
2315 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2316 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2317 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2318 spin_unlock_irqrestore(&pch->lock, flags);
2319 pm_runtime_mark_last_busy(pl330->ddma.dev);
2321 pm_runtime_put_autosuspend(pl330->ddma.dev);
2322 pm_runtime_put_autosuspend(pl330->ddma.dev);
2328 * We don't support DMA_RESUME command because of hardware
2329 * limitations, so after pausing the channel we cannot restore
2330 * it to active state. We have to terminate channel and setup
2331 * DMA transfer again. This pause feature was implemented to
2332 * allow safely read residue before channel termination.
2334 static int pl330_pause(struct dma_chan *chan)
2336 struct dma_pl330_chan *pch = to_pchan(chan);
2337 struct pl330_dmac *pl330 = pch->dmac;
2338 unsigned long flags;
2340 pm_runtime_get_sync(pl330->ddma.dev);
2341 spin_lock_irqsave(&pch->lock, flags);
2343 spin_lock(&pl330->lock);
2345 spin_unlock(&pl330->lock);
2347 spin_unlock_irqrestore(&pch->lock, flags);
2348 pm_runtime_mark_last_busy(pl330->ddma.dev);
2349 pm_runtime_put_autosuspend(pl330->ddma.dev);
2354 static void pl330_free_chan_resources(struct dma_chan *chan)
2356 struct dma_pl330_chan *pch = to_pchan(chan);
2357 struct pl330_dmac *pl330 = pch->dmac;
2358 unsigned long flags;
2360 tasklet_kill(&pch->task);
2362 pm_runtime_get_sync(pch->dmac->ddma.dev);
2363 spin_lock_irqsave(&pl330->lock, flags);
2365 pl330_release_channel(pch->thread);
2369 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2371 spin_unlock_irqrestore(&pl330->lock, flags);
2372 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2373 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2374 pl330_unprep_slave_fifo(pch);
2377 static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2378 struct dma_pl330_desc *desc)
2380 struct pl330_thread *thrd = pch->thread;
2381 struct pl330_dmac *pl330 = pch->dmac;
2382 void __iomem *regs = thrd->dmac->base;
2385 pm_runtime_get_sync(pl330->ddma.dev);
2387 if (desc->rqcfg.src_inc) {
2388 val = readl(regs + SA(thrd->id));
2389 addr = desc->px.src_addr;
2391 val = readl(regs + DA(thrd->id));
2392 addr = desc->px.dst_addr;
2394 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2395 pm_runtime_put_autosuspend(pl330->ddma.dev);
2397 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2404 static enum dma_status
2405 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2406 struct dma_tx_state *txstate)
2408 enum dma_status ret;
2409 unsigned long flags;
2410 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2411 struct dma_pl330_chan *pch = to_pchan(chan);
2412 unsigned int transferred, residual = 0;
2414 ret = dma_cookie_status(chan, cookie, txstate);
2419 if (ret == DMA_COMPLETE)
2422 spin_lock_irqsave(&pch->lock, flags);
2423 spin_lock(&pch->thread->dmac->lock);
2425 if (pch->thread->req_running != -1)
2426 running = pch->thread->req[pch->thread->req_running].desc;
2428 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2430 /* Check in pending list */
2431 list_for_each_entry(desc, &pch->work_list, node) {
2432 if (desc->status == DONE)
2433 transferred = desc->bytes_requested;
2434 else if (running && desc == running)
2436 pl330_get_current_xferred_count(pch, desc);
2437 else if (desc->status == BUSY)
2439 * Busy but not running means either just enqueued,
2440 * or finished and not yet marked done
2442 if (desc == last_enq)
2445 transferred = desc->bytes_requested;
2448 residual += desc->bytes_requested - transferred;
2449 if (desc->txd.cookie == cookie) {
2450 switch (desc->status) {
2456 ret = DMA_IN_PROGRESS;
2466 spin_unlock(&pch->thread->dmac->lock);
2467 spin_unlock_irqrestore(&pch->lock, flags);
2470 dma_set_residue(txstate, residual);
2475 static void pl330_issue_pending(struct dma_chan *chan)
2477 struct dma_pl330_chan *pch = to_pchan(chan);
2478 unsigned long flags;
2480 spin_lock_irqsave(&pch->lock, flags);
2481 if (list_empty(&pch->work_list)) {
2483 * Warn on nothing pending. Empty submitted_list may
2484 * break our pm_runtime usage counter as it is
2485 * updated on work_list emptiness status.
2487 WARN_ON(list_empty(&pch->submitted_list));
2489 pm_runtime_get_sync(pch->dmac->ddma.dev);
2491 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2492 spin_unlock_irqrestore(&pch->lock, flags);
2494 pl330_tasklet((unsigned long)pch);
2498 * We returned the last one of the circular list of descriptor(s)
2499 * from prep_xxx, so the argument to submit corresponds to the last
2500 * descriptor of the list.
2502 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2504 struct dma_pl330_desc *desc, *last = to_desc(tx);
2505 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2506 dma_cookie_t cookie;
2507 unsigned long flags;
2509 spin_lock_irqsave(&pch->lock, flags);
2511 /* Assign cookies to all nodes */
2512 while (!list_empty(&last->node)) {
2513 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2515 desc->txd.callback = last->txd.callback;
2516 desc->txd.callback_param = last->txd.callback_param;
2520 dma_cookie_assign(&desc->txd);
2522 list_move_tail(&desc->node, &pch->submitted_list);
2526 cookie = dma_cookie_assign(&last->txd);
2527 list_add_tail(&last->node, &pch->submitted_list);
2528 spin_unlock_irqrestore(&pch->lock, flags);
2533 static inline void _init_desc(struct dma_pl330_desc *desc)
2535 desc->rqcfg.swap = SWAP_NO;
2536 desc->rqcfg.scctl = CCTRL0;
2537 desc->rqcfg.dcctl = CCTRL0;
2538 desc->txd.tx_submit = pl330_tx_submit;
2540 INIT_LIST_HEAD(&desc->node);
2543 /* Returns the number of descriptors added to the DMAC pool */
2544 static int add_desc(struct list_head *pool, spinlock_t *lock,
2545 gfp_t flg, int count)
2547 struct dma_pl330_desc *desc;
2548 unsigned long flags;
2551 desc = kcalloc(count, sizeof(*desc), flg);
2555 spin_lock_irqsave(lock, flags);
2557 for (i = 0; i < count; i++) {
2558 _init_desc(&desc[i]);
2559 list_add_tail(&desc[i].node, pool);
2562 spin_unlock_irqrestore(lock, flags);
2567 static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
2570 struct dma_pl330_desc *desc = NULL;
2571 unsigned long flags;
2573 spin_lock_irqsave(lock, flags);
2575 if (!list_empty(pool)) {
2576 desc = list_entry(pool->next,
2577 struct dma_pl330_desc, node);
2579 list_del_init(&desc->node);
2581 desc->status = PREP;
2582 desc->txd.callback = NULL;
2585 spin_unlock_irqrestore(lock, flags);
2590 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2592 struct pl330_dmac *pl330 = pch->dmac;
2593 u8 *peri_id = pch->chan.private;
2594 struct dma_pl330_desc *desc;
2596 /* Pluck one desc from the pool of DMAC */
2597 desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
2599 /* If the DMAC pool is empty, alloc new */
2601 DEFINE_SPINLOCK(lock);
2604 if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
2607 desc = pluck_desc(&pool, &lock);
2608 WARN_ON(!desc || !list_empty(&pool));
2611 /* Initialize the descriptor */
2613 desc->txd.cookie = 0;
2614 async_tx_ack(&desc->txd);
2616 desc->peri = peri_id ? pch->chan.chan_id : 0;
2617 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2619 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2624 static inline void fill_px(struct pl330_xfer *px,
2625 dma_addr_t dst, dma_addr_t src, size_t len)
2632 static struct dma_pl330_desc *
2633 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2634 dma_addr_t src, size_t len)
2636 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2639 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2640 __func__, __LINE__);
2645 * Ideally we should lookout for reqs bigger than
2646 * those that can be programmed with 256 bytes of
2647 * MC buffer, but considering a req size is seldom
2648 * going to be word-unaligned and more than 200MB,
2650 * Also, should the limit is reached we'd rather
2651 * have the platform increase MC buffer size than
2652 * complicating this API driver.
2654 fill_px(&desc->px, dst, src, len);
2659 /* Call after fixing burst size */
2660 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2662 struct dma_pl330_chan *pch = desc->pchan;
2663 struct pl330_dmac *pl330 = pch->dmac;
2666 burst_len = pl330->pcfg.data_bus_width / 8;
2667 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2668 burst_len >>= desc->rqcfg.brst_size;
2670 /* src/dst_burst_len can't be more than 16 */
2671 if (burst_len > PL330_MAX_BURST)
2672 burst_len = PL330_MAX_BURST;
2677 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2678 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2679 size_t period_len, enum dma_transfer_direction direction,
2680 unsigned long flags)
2682 struct dma_pl330_desc *desc = NULL, *first = NULL;
2683 struct dma_pl330_chan *pch = to_pchan(chan);
2684 struct pl330_dmac *pl330 = pch->dmac;
2689 if (len % period_len != 0)
2692 if (!is_slave_direction(direction)) {
2693 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2694 __func__, __LINE__);
2698 pl330_config_write(chan, &pch->slave_config, direction);
2700 if (!pl330_prep_slave_fifo(pch, direction))
2703 for (i = 0; i < len / period_len; i++) {
2704 desc = pl330_get_desc(pch);
2706 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2707 __func__, __LINE__);
2712 spin_lock_irqsave(&pl330->pool_lock, flags);
2714 while (!list_empty(&first->node)) {
2715 desc = list_entry(first->node.next,
2716 struct dma_pl330_desc, node);
2717 list_move_tail(&desc->node, &pl330->desc_pool);
2720 list_move_tail(&first->node, &pl330->desc_pool);
2722 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2727 switch (direction) {
2728 case DMA_MEM_TO_DEV:
2729 desc->rqcfg.src_inc = 1;
2730 desc->rqcfg.dst_inc = 0;
2732 dst = pch->fifo_dma;
2734 case DMA_DEV_TO_MEM:
2735 desc->rqcfg.src_inc = 0;
2736 desc->rqcfg.dst_inc = 1;
2737 src = pch->fifo_dma;
2744 desc->rqtype = direction;
2745 desc->rqcfg.brst_size = pch->burst_sz;
2746 desc->rqcfg.brst_len = pch->burst_len;
2747 desc->bytes_requested = period_len;
2748 fill_px(&desc->px, dst, src, period_len);
2753 list_add_tail(&desc->node, &first->node);
2755 dma_addr += period_len;
2762 desc->txd.flags = flags;
2767 static struct dma_async_tx_descriptor *
2768 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2769 dma_addr_t src, size_t len, unsigned long flags)
2771 struct dma_pl330_desc *desc;
2772 struct dma_pl330_chan *pch = to_pchan(chan);
2773 struct pl330_dmac *pl330;
2776 if (unlikely(!pch || !len))
2781 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2785 desc->rqcfg.src_inc = 1;
2786 desc->rqcfg.dst_inc = 1;
2787 desc->rqtype = DMA_MEM_TO_MEM;
2789 /* Select max possible burst size */
2790 burst = pl330->pcfg.data_bus_width / 8;
2793 * Make sure we use a burst size that aligns with all the memcpy
2794 * parameters because our DMA programming algorithm doesn't cope with
2795 * transfers which straddle an entry in the DMA device's MFIFO.
2797 while ((src | dst | len) & (burst - 1))
2800 desc->rqcfg.brst_size = 0;
2801 while (burst != (1 << desc->rqcfg.brst_size))
2802 desc->rqcfg.brst_size++;
2805 * If burst size is smaller than bus width then make sure we only
2806 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2808 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2809 desc->rqcfg.brst_len = 1;
2811 desc->rqcfg.brst_len = get_burst_len(desc, len);
2812 desc->bytes_requested = len;
2814 desc->txd.flags = flags;
2819 static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2820 struct dma_pl330_desc *first)
2822 unsigned long flags;
2823 struct dma_pl330_desc *desc;
2828 spin_lock_irqsave(&pl330->pool_lock, flags);
2830 while (!list_empty(&first->node)) {
2831 desc = list_entry(first->node.next,
2832 struct dma_pl330_desc, node);
2833 list_move_tail(&desc->node, &pl330->desc_pool);
2836 list_move_tail(&first->node, &pl330->desc_pool);
2838 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2841 static struct dma_async_tx_descriptor *
2842 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2843 unsigned int sg_len, enum dma_transfer_direction direction,
2844 unsigned long flg, void *context)
2846 struct dma_pl330_desc *first, *desc = NULL;
2847 struct dma_pl330_chan *pch = to_pchan(chan);
2848 struct scatterlist *sg;
2851 if (unlikely(!pch || !sgl || !sg_len))
2854 pl330_config_write(chan, &pch->slave_config, direction);
2856 if (!pl330_prep_slave_fifo(pch, direction))
2861 for_each_sg(sgl, sg, sg_len, i) {
2863 desc = pl330_get_desc(pch);
2865 struct pl330_dmac *pl330 = pch->dmac;
2867 dev_err(pch->dmac->ddma.dev,
2868 "%s:%d Unable to fetch desc\n",
2869 __func__, __LINE__);
2870 __pl330_giveback_desc(pl330, first);
2878 list_add_tail(&desc->node, &first->node);
2880 if (direction == DMA_MEM_TO_DEV) {
2881 desc->rqcfg.src_inc = 1;
2882 desc->rqcfg.dst_inc = 0;
2883 fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
2886 desc->rqcfg.src_inc = 0;
2887 desc->rqcfg.dst_inc = 1;
2888 fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
2892 desc->rqcfg.brst_size = pch->burst_sz;
2893 desc->rqcfg.brst_len = pch->burst_len;
2894 desc->rqtype = direction;
2895 desc->bytes_requested = sg_dma_len(sg);
2898 /* Return the last desc in the chain */
2899 desc->txd.flags = flg;
2903 static irqreturn_t pl330_irq_handler(int irq, void *data)
2905 if (pl330_update(data))
2911 #define PL330_DMA_BUSWIDTHS \
2912 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2913 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2914 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2915 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2916 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2918 #ifdef CONFIG_DEBUG_FS
2919 static int pl330_debugfs_show(struct seq_file *s, void *data)
2921 struct pl330_dmac *pl330 = s->private;
2922 int chans, pchs, ch, pr;
2924 chans = pl330->pcfg.num_chan;
2925 pchs = pl330->num_peripherals;
2927 seq_puts(s, "PL330 physical channels:\n");
2928 seq_puts(s, "THREAD:\t\tCHANNEL:\n");
2929 seq_puts(s, "--------\t-----\n");
2930 for (ch = 0; ch < chans; ch++) {
2931 struct pl330_thread *thrd = &pl330->channels[ch];
2934 for (pr = 0; pr < pchs; pr++) {
2935 struct dma_pl330_chan *pch = &pl330->peripherals[pr];
2937 if (!pch->thread || thrd->id != pch->thread->id)
2943 seq_printf(s, "%d\t\t", thrd->id);
2945 seq_puts(s, "--\n");
2947 seq_printf(s, "%d\n", found);
2953 DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
2955 static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2957 debugfs_create_file(dev_name(pl330->ddma.dev),
2958 S_IFREG | 0444, NULL, pl330,
2959 &pl330_debugfs_fops);
2962 static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2968 * Runtime PM callbacks are provided by amba/bus.c driver.
2970 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2971 * bus driver will only disable/enable the clock in runtime PM callbacks.
2973 static int __maybe_unused pl330_suspend(struct device *dev)
2975 struct amba_device *pcdev = to_amba_device(dev);
2977 pm_runtime_force_suspend(dev);
2978 amba_pclk_unprepare(pcdev);
2983 static int __maybe_unused pl330_resume(struct device *dev)
2985 struct amba_device *pcdev = to_amba_device(dev);
2988 ret = amba_pclk_prepare(pcdev);
2992 pm_runtime_force_resume(dev);
2997 static const struct dev_pm_ops pl330_pm = {
2998 SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume)
3002 pl330_probe(struct amba_device *adev, const struct amba_id *id)
3004 struct pl330_config *pcfg;
3005 struct pl330_dmac *pl330;
3006 struct dma_pl330_chan *pch, *_p;
3007 struct dma_device *pd;
3008 struct resource *res;
3011 struct device_node *np = adev->dev.of_node;
3013 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
3017 /* Allocate a new DMAC and its Channels */
3018 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
3023 pd->dev = &adev->dev;
3028 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
3029 if (of_property_read_bool(np, of_quirks[i].quirk))
3030 pl330->quirks |= of_quirks[i].id;
3033 pl330->base = devm_ioremap_resource(&adev->dev, res);
3034 if (IS_ERR(pl330->base))
3035 return PTR_ERR(pl330->base);
3037 amba_set_drvdata(adev, pl330);
3039 pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
3040 if (IS_ERR(pl330->rstc)) {
3041 if (PTR_ERR(pl330->rstc) != -EPROBE_DEFER)
3042 dev_err(&adev->dev, "Failed to get reset!\n");
3043 return PTR_ERR(pl330->rstc);
3045 ret = reset_control_deassert(pl330->rstc);
3047 dev_err(&adev->dev, "Couldn't deassert the device from reset!\n");
3052 pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
3053 if (IS_ERR(pl330->rstc_ocp)) {
3054 if (PTR_ERR(pl330->rstc_ocp) != -EPROBE_DEFER)
3055 dev_err(&adev->dev, "Failed to get OCP reset!\n");
3056 return PTR_ERR(pl330->rstc_ocp);
3058 ret = reset_control_deassert(pl330->rstc_ocp);
3060 dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n");
3065 for (i = 0; i < AMBA_NR_IRQS; i++) {
3068 ret = devm_request_irq(&adev->dev, irq,
3069 pl330_irq_handler, 0,
3070 dev_name(&adev->dev), pl330);
3078 pcfg = &pl330->pcfg;
3080 pcfg->periph_id = adev->periphid;
3081 ret = pl330_add(pl330);
3085 INIT_LIST_HEAD(&pl330->desc_pool);
3086 spin_lock_init(&pl330->pool_lock);
3088 /* Create a descriptor pool of default size */
3089 if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
3090 GFP_KERNEL, NR_DEFAULT_DESC))
3091 dev_warn(&adev->dev, "unable to allocate desc\n");
3093 INIT_LIST_HEAD(&pd->channels);
3095 /* Initialize channel parameters */
3096 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
3098 pl330->num_peripherals = num_chan;
3100 pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL);
3101 if (!pl330->peripherals) {
3106 for (i = 0; i < num_chan; i++) {
3107 pch = &pl330->peripherals[i];
3109 pch->chan.private = adev->dev.of_node;
3110 INIT_LIST_HEAD(&pch->submitted_list);
3111 INIT_LIST_HEAD(&pch->work_list);
3112 INIT_LIST_HEAD(&pch->completed_list);
3113 spin_lock_init(&pch->lock);
3115 pch->chan.device = pd;
3117 pch->dir = DMA_NONE;
3119 /* Add the channel to the DMAC list */
3120 list_add_tail(&pch->chan.device_node, &pd->channels);
3123 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
3124 if (pcfg->num_peri) {
3125 dma_cap_set(DMA_SLAVE, pd->cap_mask);
3126 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
3127 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3130 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3131 pd->device_free_chan_resources = pl330_free_chan_resources;
3132 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3133 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3134 pd->device_tx_status = pl330_tx_status;
3135 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3136 pd->device_config = pl330_config;
3137 pd->device_pause = pl330_pause;
3138 pd->device_terminate_all = pl330_terminate_all;
3139 pd->device_issue_pending = pl330_issue_pending;
3140 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
3141 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
3142 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
3143 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
3144 pd->max_burst = PL330_MAX_BURST;
3146 ret = dma_async_device_register(pd);
3148 dev_err(&adev->dev, "unable to register DMAC\n");
3152 if (adev->dev.of_node) {
3153 ret = of_dma_controller_register(adev->dev.of_node,
3154 of_dma_pl330_xlate, pl330);
3157 "unable to register DMA to the generic DT DMA helpers\n");
3161 adev->dev.dma_parms = &pl330->dma_parms;
3164 * This is the limit for transfers with a buswidth of 1, larger
3165 * buswidths will have larger limits.
3167 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3169 dev_err(&adev->dev, "unable to set the seg size\n");
3172 init_pl330_debugfs(pl330);
3173 dev_info(&adev->dev,
3174 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3175 dev_info(&adev->dev,
3176 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3177 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
3178 pcfg->num_peri, pcfg->num_events);
3180 pm_runtime_irq_safe(&adev->dev);
3181 pm_runtime_use_autosuspend(&adev->dev);
3182 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3183 pm_runtime_mark_last_busy(&adev->dev);
3184 pm_runtime_put_autosuspend(&adev->dev);
3189 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3192 /* Remove the channel */
3193 list_del(&pch->chan.device_node);
3195 /* Flush the channel */
3197 pl330_terminate_all(&pch->chan);
3198 pl330_free_chan_resources(&pch->chan);
3204 if (pl330->rstc_ocp)
3205 reset_control_assert(pl330->rstc_ocp);
3208 reset_control_assert(pl330->rstc);
3212 static int pl330_remove(struct amba_device *adev)
3214 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3215 struct dma_pl330_chan *pch, *_p;
3218 pm_runtime_get_noresume(pl330->ddma.dev);
3220 if (adev->dev.of_node)
3221 of_dma_controller_free(adev->dev.of_node);
3223 for (i = 0; i < AMBA_NR_IRQS; i++) {
3226 devm_free_irq(&adev->dev, irq, pl330);
3229 dma_async_device_unregister(&pl330->ddma);
3232 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3235 /* Remove the channel */
3236 list_del(&pch->chan.device_node);
3238 /* Flush the channel */
3240 pl330_terminate_all(&pch->chan);
3241 pl330_free_chan_resources(&pch->chan);
3247 if (pl330->rstc_ocp)
3248 reset_control_assert(pl330->rstc_ocp);
3251 reset_control_assert(pl330->rstc);
3255 static const struct amba_id pl330_ids[] = {
3263 MODULE_DEVICE_TABLE(amba, pl330_ids);
3265 static struct amba_driver pl330_driver = {
3267 .owner = THIS_MODULE,
3268 .name = "dma-pl330",
3271 .id_table = pl330_ids,
3272 .probe = pl330_probe,
3273 .remove = pl330_remove,
3276 module_amba_driver(pl330_driver);
3278 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3279 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3280 MODULE_LICENSE("GPL");