drivers/dma/moxart-dma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * MOXA ART SoCs DMA Engine support.
   4  *
   5  * Copyright (C) 2013 Jonas Jensen
   6  *
   7  * Jonas Jensen <jonas.jensen@gmail.com>
   8  */
   9
  10 #include <linux/dmaengine.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/err.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/bitops.h>
  24
  25 #include <asm/cacheflush.h>
  26
  27 #include "dmaengine.h"
  28 #include "virt-dma.h"
  29
  30 #define APB_DMA_MAX_CHANNEL                     4
  31
  32 #define REG_OFF_ADDRESS_SOURCE                  0
  33 #define REG_OFF_ADDRESS_DEST                    4
  34 #define REG_OFF_CYCLES                          8
  35 #define REG_OFF_CTRL                            12
  36 #define REG_OFF_CHAN_SIZE                       16
  37
  38 #define APB_DMA_ENABLE                          BIT(0)
  39 #define APB_DMA_FIN_INT_STS                     BIT(1)
  40 #define APB_DMA_FIN_INT_EN                      BIT(2)
  41 #define APB_DMA_BURST_MODE                      BIT(3)
  42 #define APB_DMA_ERR_INT_STS                     BIT(4)
  43 #define APB_DMA_ERR_INT_EN                      BIT(5)
  44
  45 /*
  46  * Unset: APB
  47  * Set:   AHB
  48  */
  49 #define APB_DMA_SOURCE_SELECT                   0x40
  50 #define APB_DMA_DEST_SELECT                     0x80
  51
  52 #define APB_DMA_SOURCE                          0x100
  53 #define APB_DMA_DEST                            0x1000
  54
  55 #define APB_DMA_SOURCE_MASK                     0x700
  56 #define APB_DMA_DEST_MASK                       0x7000
  57
  58 /*
  59  * 000: No increment
  60  * 001: +1 (Burst=0), +4  (Burst=1)
  61  * 010: +2 (Burst=0), +8  (Burst=1)
  62  * 011: +4 (Burst=0), +16 (Burst=1)
  63  * 101: -1 (Burst=0), -4  (Burst=1)
  64  * 110: -2 (Burst=0), -8  (Burst=1)
  65  * 111: -4 (Burst=0), -16 (Burst=1)
  66  */
  67 #define APB_DMA_SOURCE_INC_0                    0
  68 #define APB_DMA_SOURCE_INC_1_4                  0x100
  69 #define APB_DMA_SOURCE_INC_2_8                  0x200
  70 #define APB_DMA_SOURCE_INC_4_16                 0x300
  71 #define APB_DMA_SOURCE_DEC_1_4                  0x500
  72 #define APB_DMA_SOURCE_DEC_2_8                  0x600
  73 #define APB_DMA_SOURCE_DEC_4_16                 0x700
  74 #define APB_DMA_DEST_INC_0                      0
  75 #define APB_DMA_DEST_INC_1_4                    0x1000
  76 #define APB_DMA_DEST_INC_2_8                    0x2000
  77 #define APB_DMA_DEST_INC_4_16                   0x3000
  78 #define APB_DMA_DEST_DEC_1_4                    0x5000
  79 #define APB_DMA_DEST_DEC_2_8                    0x6000
  80 #define APB_DMA_DEST_DEC_4_16                   0x7000
  81
  82 /*
  83  * Request signal select source/destination address for DMA hardware handshake.
  84  *
  85  * The request line number is a property of the DMA controller itself,
  86  * e.g. MMC must always request channels where dma_slave_config->slave_id is 5.
  87  *
  88  * 0:    No request / Grant signal
  89  * 1-15: Request    / Grant signal
  90  */
  91 #define APB_DMA_SOURCE_REQ_NO                   0x1000000
  92 #define APB_DMA_SOURCE_REQ_NO_MASK              0xf000000
  93 #define APB_DMA_DEST_REQ_NO                     0x10000
  94 #define APB_DMA_DEST_REQ_NO_MASK                0xf0000
  95
  96 #define APB_DMA_DATA_WIDTH                      0x100000
  97 #define APB_DMA_DATA_WIDTH_MASK                 0x300000
  98 /*
  99  * Data width of transfer:
 100  *
 101  * 00: Word
 102  * 01: Half
 103  * 10: Byte
 104  */
 105 #define APB_DMA_DATA_WIDTH_4                    0
 106 #define APB_DMA_DATA_WIDTH_2                    0x100000
 107 #define APB_DMA_DATA_WIDTH_1                    0x200000
 108
 109 #define APB_DMA_CYCLES_MASK                     0x00ffffff
 110
 111 #define MOXART_DMA_DATA_TYPE_S8                 0x00
 112 #define MOXART_DMA_DATA_TYPE_S16                0x01
 113 #define MOXART_DMA_DATA_TYPE_S32                0x02
 114
 115 struct moxart_sg {
 116         dma_addr_t addr;
 117         uint32_t len;
 118 };
 119
 120 struct moxart_desc {
 121         enum dma_transfer_direction     dma_dir;
 122         dma_addr_t                      dev_addr;
 123         unsigned int                    sglen;
 124         unsigned int                    dma_cycles;
 125         struct virt_dma_desc            vd;
 126         uint8_t                         es;
 127         struct moxart_sg                sg[];
 128 };
 129
 130 struct moxart_chan {
 131         struct virt_dma_chan            vc;
 132
 133         void __iomem                    *base;
 134         struct moxart_desc              *desc;
 135
 136         struct dma_slave_config         cfg;
 137
 138         bool                            allocated;
 139         bool                            error;
 140         int                             ch_num;
 141         unsigned int                    line_reqno;
 142         unsigned int                    sgidx;
 143 };
 144
 145 struct moxart_dmadev {
 146         struct dma_device               dma_slave;
 147         struct moxart_chan              slave_chans[APB_DMA_MAX_CHANNEL];
 148         unsigned int                    irq;
 149 };
 150
 151 struct moxart_filter_data {
 152         struct moxart_dmadev            *mdc;
 153         struct of_phandle_args          *dma_spec;
 154 };
 155
 156 static const unsigned int es_bytes[] = {
 157         [MOXART_DMA_DATA_TYPE_S8] = 1,
 158         [MOXART_DMA_DATA_TYPE_S16] = 2,
 159         [MOXART_DMA_DATA_TYPE_S32] = 4,
 160 };
 161
 162 static struct device *chan2dev(struct dma_chan *chan)
 163 {
 164         return &chan->dev->device;
 165 }
 166
 167 static inline struct moxart_chan *to_moxart_dma_chan(struct dma_chan *c)
 168 {
 169         return container_of(c, struct moxart_chan, vc.chan);
 170 }
 171
 172 static inline struct moxart_desc *to_moxart_dma_desc(
 173         struct dma_async_tx_descriptor *t)
 174 {
 175         return container_of(t, struct moxart_desc, vd.tx);
 176 }
 177
 178 static void moxart_dma_desc_free(struct virt_dma_desc *vd)
 179 {
 180         kfree(container_of(vd, struct moxart_desc, vd));
 181 }
 182
 183 static int moxart_terminate_all(struct dma_chan *chan)
 184 {
 185         struct moxart_chan *ch = to_moxart_dma_chan(chan);
 186         unsigned long flags;
 187         LIST_HEAD(head);
 188         u32 ctrl;
 189
 190         dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch);
 191
 192         spin_lock_irqsave(&ch->vc.lock, flags);
 193
 194         if (ch->desc) {
 195                 moxart_dma_desc_free(&ch->desc->vd);
 196                 ch->desc = NULL;
 197         }
 198
 199         ctrl = readl(ch->base + REG_OFF_CTRL);
 200         ctrl &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
 201         writel(ctrl, ch->base + REG_OFF_CTRL);
 202
 203         vchan_get_all_descriptors(&ch->vc, &head);
 204         spin_unlock_irqrestore(&ch->vc.lock, flags);
 205         vchan_dma_desc_free_list(&ch->vc, &head);
 206
 207         return 0;
 208 }
 209
 210 static int moxart_slave_config(struct dma_chan *chan,
 211                                struct dma_slave_config *cfg)
 212 {
 213         struct moxart_chan *ch = to_moxart_dma_chan(chan);
 214         u32 ctrl;
 215
 216         ch->cfg = *cfg;
 217
 218         ctrl = readl(ch->base + REG_OFF_CTRL);
 219         ctrl |= APB_DMA_BURST_MODE;
 220         ctrl &= ~(APB_DMA_DEST_MASK | APB_DMA_SOURCE_MASK);
 221         ctrl &= ~(APB_DMA_DEST_REQ_NO_MASK | APB_DMA_SOURCE_REQ_NO_MASK);
 222
 223         switch (ch->cfg.src_addr_width) {
 224         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 225                 ctrl |= APB_DMA_DATA_WIDTH_1;
 226                 if (ch->cfg.direction != DMA_MEM_TO_DEV)
 227                         ctrl |= APB_DMA_DEST_INC_1_4;
 228                 else
 229                         ctrl |= APB_DMA_SOURCE_INC_1_4;
 230                 break;
 231         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 232                 ctrl |= APB_DMA_DATA_WIDTH_2;
 233                 if (ch->cfg.direction != DMA_MEM_TO_DEV)
 234                         ctrl |= APB_DMA_DEST_INC_2_8;
 235                 else
 236                         ctrl |= APB_DMA_SOURCE_INC_2_8;
 237                 break;
 238         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 239                 ctrl &= ~APB_DMA_DATA_WIDTH;
 240                 if (ch->cfg.direction != DMA_MEM_TO_DEV)
 241                         ctrl |= APB_DMA_DEST_INC_4_16;
 242                 else
 243                         ctrl |= APB_DMA_SOURCE_INC_4_16;
 244                 break;
 245         default:
 246                 return -EINVAL;
 247         }
 248
 249         if (ch->cfg.direction == DMA_MEM_TO_DEV) {
 250                 ctrl &= ~APB_DMA_DEST_SELECT;
 251                 ctrl |= APB_DMA_SOURCE_SELECT;
 252                 ctrl |= (ch->line_reqno << 16 &
 253                          APB_DMA_DEST_REQ_NO_MASK);
 254         } else {
 255                 ctrl |= APB_DMA_DEST_SELECT;
 256                 ctrl &= ~APB_DMA_SOURCE_SELECT;
 257                 ctrl |= (ch->line_reqno << 24 &
 258                          APB_DMA_SOURCE_REQ_NO_MASK);
 259         }
 260
 261         writel(ctrl, ch->base + REG_OFF_CTRL);
 262
 263         return 0;
 264 }
 265
 266 static struct dma_async_tx_descriptor *moxart_prep_slave_sg(
 267         struct dma_chan *chan, struct scatterlist *sgl,
 268         unsigned int sg_len, enum dma_transfer_direction dir,
 269         unsigned long tx_flags, void *context)
 270 {
 271         struct moxart_chan *ch = to_moxart_dma_chan(chan);
 272         struct moxart_desc *d;
 273         enum dma_slave_buswidth dev_width;
 274         dma_addr_t dev_addr;
 275         struct scatterlist *sgent;
 276         unsigned int es;
 277         unsigned int i;
 278
 279         if (!is_slave_direction(dir)) {
 280                 dev_err(chan2dev(chan), "%s: invalid DMA direction\n",
 281                         __func__);
 282                 return NULL;
 283         }
 284
 285         if (dir == DMA_DEV_TO_MEM) {
 286                 dev_addr = ch->cfg.src_addr;
 287                 dev_width = ch->cfg.src_addr_width;
 288         } else {
 289                 dev_addr = ch->cfg.dst_addr;
 290                 dev_width = ch->cfg.dst_addr_width;
 291         }
 292
 293         switch (dev_width) {
 294         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 295                 es = MOXART_DMA_DATA_TYPE_S8;
 296                 break;
 297         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 298                 es = MOXART_DMA_DATA_TYPE_S16;
 299                 break;
 300         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 301                 es = MOXART_DMA_DATA_TYPE_S32;
 302                 break;
 303         default:
 304                 dev_err(chan2dev(chan), "%s: unsupported data width (%u)\n",
 305                         __func__, dev_width);
 306                 return NULL;
 307         }
 308
 309         d = kzalloc(struct_size(d, sg, sg_len), GFP_ATOMIC);
 310         if (!d)
 311                 return NULL;
 312
 313         d->dma_dir = dir;
 314         d->dev_addr = dev_addr;
 315         d->es = es;
 316
 317         for_each_sg(sgl, sgent, sg_len, i) {
 318                 d->sg[i].addr = sg_dma_address(sgent);
 319                 d->sg[i].len = sg_dma_len(sgent);
 320         }
 321
 322         d->sglen = sg_len;
 323
 324         ch->error = 0;
 325
 326         return vchan_tx_prep(&ch->vc, &d->vd, tx_flags);
 327 }
 328
 329 static struct dma_chan *moxart_of_xlate(struct of_phandle_args *dma_spec,
 330                                         struct of_dma *ofdma)
 331 {
 332         struct moxart_dmadev *mdc = ofdma->of_dma_data;
 333         struct dma_chan *chan;
 334         struct moxart_chan *ch;
 335
 336         chan = dma_get_any_slave_channel(&mdc->dma_slave);
 337         if (!chan)
 338                 return NULL;
 339
 340         ch = to_moxart_dma_chan(chan);
 341         ch->line_reqno = dma_spec->args[0];
 342
 343         return chan;
 344 }
 345
 346 static int moxart_alloc_chan_resources(struct dma_chan *chan)
 347 {
 348         struct moxart_chan *ch = to_moxart_dma_chan(chan);
 349
 350         dev_dbg(chan2dev(chan), "%s: allocating channel #%u\n",
 351                 __func__, ch->ch_num);
 352         ch->allocated = 1;
 353
 354         return 0;
 355 }
 356
 357 static void moxart_free_chan_resources(struct dma_chan *chan)
 358 {
 359         struct moxart_chan *ch = to_moxart_dma_chan(chan);
 360
 361         vchan_free_chan_resources(&ch->vc);
 362
 363         dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n",
 364                 __func__, ch->ch_num);
 365         ch->allocated = 0;
 366 }
 367
 368 static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr,
 369                                   dma_addr_t dst_addr)
 370 {
 371         writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE);
 372         writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST);
 373 }
 374
 375 static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len)
 376 {
 377         struct moxart_desc *d = ch->desc;
 378         unsigned int sglen_div = es_bytes[d->es];
 379
 380         d->dma_cycles = len >> sglen_div;
 381
 382         /*
 383          * There are 4 cycles on 64 bytes copied, i.e. one cycle copies 16
 384          * bytes ( when width is APB_DMAB_DATA_WIDTH_4 ).
 385          */
 386         writel(d->dma_cycles, ch->base + REG_OFF_CYCLES);
 387
 388         dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n",
 389                 __func__, d->dma_cycles, len);
 390 }
 391
 392 static void moxart_start_dma(struct moxart_chan *ch)
 393 {
 394         u32 ctrl;
 395
 396         ctrl = readl(ch->base + REG_OFF_CTRL);
 397         ctrl |= (APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
 398         writel(ctrl, ch->base + REG_OFF_CTRL);
 399 }
 400
 401 static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx)
 402 {
 403         struct moxart_desc *d = ch->desc;
 404         struct moxart_sg *sg = ch->desc->sg + idx;
 405
 406         if (ch->desc->dma_dir == DMA_MEM_TO_DEV)
 407                 moxart_dma_set_params(ch, sg->addr, d->dev_addr);
 408         else if (ch->desc->dma_dir == DMA_DEV_TO_MEM)
 409                 moxart_dma_set_params(ch, d->dev_addr, sg->addr);
 410
 411         moxart_set_transfer_params(ch, sg->len);
 412
 413         moxart_start_dma(ch);
 414 }
 415
 416 static void moxart_dma_start_desc(struct dma_chan *chan)
 417 {
 418         struct moxart_chan *ch = to_moxart_dma_chan(chan);
 419         struct virt_dma_desc *vd;
 420
 421         vd = vchan_next_desc(&ch->vc);
 422
 423         if (!vd) {
 424                 ch->desc = NULL;
 425                 return;
 426         }
 427
 428         list_del(&vd->node);
 429
 430         ch->desc = to_moxart_dma_desc(&vd->tx);
 431         ch->sgidx = 0;
 432
 433         moxart_dma_start_sg(ch, 0);
 434 }
 435
 436 static void moxart_issue_pending(struct dma_chan *chan)
 437 {
 438         struct moxart_chan *ch = to_moxart_dma_chan(chan);
 439         unsigned long flags;
 440
 441         spin_lock_irqsave(&ch->vc.lock, flags);
 442         if (vchan_issue_pending(&ch->vc) && !ch->desc)
 443                 moxart_dma_start_desc(chan);
 444         spin_unlock_irqrestore(&ch->vc.lock, flags);
 445 }
 446
 447 static size_t moxart_dma_desc_size(struct moxart_desc *d,
 448                                    unsigned int completed_sgs)
 449 {
 450         unsigned int i;
 451         size_t size;
 452
 453         for (size = i = completed_sgs; i < d->sglen; i++)
 454                 size += d->sg[i].len;
 455
 456         return size;
 457 }
 458
 459 static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch)
 460 {
 461         size_t size;
 462         unsigned int completed_cycles, cycles;
 463
 464         size = moxart_dma_desc_size(ch->desc, ch->sgidx);
 465         cycles = readl(ch->base + REG_OFF_CYCLES);
 466         completed_cycles = (ch->desc->dma_cycles - cycles);
 467         size -= completed_cycles << es_bytes[ch->desc->es];
 468
 469         dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size);
 470
 471         return size;
 472 }
 473
 474 static enum dma_status moxart_tx_status(struct dma_chan *chan,
 475                                         dma_cookie_t cookie,
 476                                         struct dma_tx_state *txstate)
 477 {
 478         struct moxart_chan *ch = to_moxart_dma_chan(chan);
 479         struct virt_dma_desc *vd;
 480         struct moxart_desc *d;
 481         enum dma_status ret;
 482         unsigned long flags;
 483
 484         /*
 485          * dma_cookie_status() assigns initial residue value.
 486          */
 487         ret = dma_cookie_status(chan, cookie, txstate);
 488
 489         spin_lock_irqsave(&ch->vc.lock, flags);
 490         vd = vchan_find_desc(&ch->vc, cookie);
 491         if (vd) {
 492                 d = to_moxart_dma_desc(&vd->tx);
 493                 txstate->residue = moxart_dma_desc_size(d, 0);
 494         } else if (ch->desc && ch->desc->vd.tx.cookie == cookie) {
 495                 txstate->residue = moxart_dma_desc_size_in_flight(ch);
 496         }
 497         spin_unlock_irqrestore(&ch->vc.lock, flags);
 498
 499         if (ch->error)
 500                 return DMA_ERROR;
 501
 502         return ret;
 503 }
 504
 505 static void moxart_dma_init(struct dma_device *dma, struct device *dev)
 506 {
 507         dma->device_prep_slave_sg               = moxart_prep_slave_sg;
 508         dma->device_alloc_chan_resources        = moxart_alloc_chan_resources;
 509         dma->device_free_chan_resources         = moxart_free_chan_resources;
 510         dma->device_issue_pending               = moxart_issue_pending;
 511         dma->device_tx_status                   = moxart_tx_status;
 512         dma->device_config                      = moxart_slave_config;
 513         dma->device_terminate_all               = moxart_terminate_all;
 514         dma->dev                                = dev;
 515
 516         INIT_LIST_HEAD(&dma->channels);
 517 }
 518
 519 static irqreturn_t moxart_dma_interrupt(int irq, void *devid)
 520 {
 521         struct moxart_dmadev *mc = devid;
 522         struct moxart_chan *ch = &mc->slave_chans[0];
 523         unsigned int i;
 524         u32 ctrl;
 525
 526         dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__);
 527
 528         for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
 529                 if (!ch->allocated)
 530                         continue;
 531
 532                 ctrl = readl(ch->base + REG_OFF_CTRL);
 533
 534                 dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n",
 535                         __func__, ch, ch->base, ctrl);
 536
 537                 if (ctrl & APB_DMA_FIN_INT_STS) {
 538                         ctrl &= ~APB_DMA_FIN_INT_STS;
 539                         if (ch->desc) {
 540                                 spin_lock(&ch->vc.lock);
 541                                 if (++ch->sgidx < ch->desc->sglen) {
 542                                         moxart_dma_start_sg(ch, ch->sgidx);
 543                                 } else {
 544                                         vchan_cookie_complete(&ch->desc->vd);
 545                                         moxart_dma_start_desc(&ch->vc.chan);
 546                                 }
 547                                 spin_unlock(&ch->vc.lock);
 548                         }
 549                 }
 550
 551                 if (ctrl & APB_DMA_ERR_INT_STS) {
 552                         ctrl &= ~APB_DMA_ERR_INT_STS;
 553                         ch->error = 1;
 554                 }
 555
 556                 writel(ctrl, ch->base + REG_OFF_CTRL);
 557         }
 558
 559         return IRQ_HANDLED;
 560 }
 561
 562 static int moxart_probe(struct platform_device *pdev)
 563 {
 564         struct device *dev = &pdev->dev;
 565         struct device_node *node = dev->of_node;
 566         void __iomem *dma_base_addr;
 567         int ret, i;
 568         unsigned int irq;
 569         struct moxart_chan *ch;
 570         struct moxart_dmadev *mdc;
 571
 572         mdc = devm_kzalloc(dev, sizeof(*mdc), GFP_KERNEL);
 573         if (!mdc)
 574                 return -ENOMEM;
 575
 576         irq = irq_of_parse_and_map(node, 0);
 577         if (!irq) {
 578                 dev_err(dev, "no IRQ resource\n");
 579                 return -EINVAL;
 580         }
 581
 582         dma_base_addr = devm_platform_ioremap_resource(pdev, 0);
 583         if (IS_ERR(dma_base_addr))
 584                 return PTR_ERR(dma_base_addr);
 585
 586         dma_cap_zero(mdc->dma_slave.cap_mask);
 587         dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask);
 588         dma_cap_set(DMA_PRIVATE, mdc->dma_slave.cap_mask);
 589
 590         moxart_dma_init(&mdc->dma_slave, dev);
 591
 592         ch = &mdc->slave_chans[0];
 593         for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
 594                 ch->ch_num = i;
 595                 ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE;
 596                 ch->allocated = 0;
 597
 598                 ch->vc.desc_free = moxart_dma_desc_free;
 599                 vchan_init(&ch->vc, &mdc->dma_slave);
 600
 601                 dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n",
 602                         __func__, i, ch->ch_num, ch->base);
 603         }
 604
 605         platform_set_drvdata(pdev, mdc);
 606
 607         ret = devm_request_irq(dev, irq, moxart_dma_interrupt, 0,
 608                                "moxart-dma-engine", mdc);
 609         if (ret) {
 610                 dev_err(dev, "devm_request_irq failed\n");
 611                 return ret;
 612         }
 613         mdc->irq = irq;
 614
 615         ret = dma_async_device_register(&mdc->dma_slave);
 616         if (ret) {
 617                 dev_err(dev, "dma_async_device_register failed\n");
 618                 return ret;
 619         }
 620
 621         ret = of_dma_controller_register(node, moxart_of_xlate, mdc);
 622         if (ret) {
 623                 dev_err(dev, "of_dma_controller_register failed\n");
 624                 dma_async_device_unregister(&mdc->dma_slave);
 625                 return ret;
 626         }
 627
 628         dev_dbg(dev, "%s: IRQ=%u\n", __func__, irq);
 629
 630         return 0;
 631 }
 632
 633 static int moxart_remove(struct platform_device *pdev)
 634 {
 635         struct moxart_dmadev *m = platform_get_drvdata(pdev);
 636
 637         devm_free_irq(&pdev->dev, m->irq, m);
 638
 639         dma_async_device_unregister(&m->dma_slave);
 640
 641         if (pdev->dev.of_node)
 642                 of_dma_controller_free(pdev->dev.of_node);
 643
 644         return 0;
 645 }
 646
 647 static const struct of_device_id moxart_dma_match[] = {
 648         { .compatible = "moxa,moxart-dma" },
 649         { }
 650 };
 651 MODULE_DEVICE_TABLE(of, moxart_dma_match);
 652
 653 static struct platform_driver moxart_driver = {
 654         .probe  = moxart_probe,
 655         .remove = moxart_remove,
 656         .driver = {
 657                 .name           = "moxart-dma-engine",
 658                 .of_match_table = moxart_dma_match,
 659         },
 660 };
 661
 662 static int moxart_init(void)
 663 {
 664         return platform_driver_register(&moxart_driver);
 665 }
 666 subsys_initcall(moxart_init);
 667
 668 static void __exit moxart_exit(void)
 669 {
 670         platform_driver_unregister(&moxart_driver);
 671 }
 672 module_exit(moxart_exit);
 673
 674 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
 675 MODULE_DESCRIPTION("MOXART DMA engine driver");
 676 MODULE_LICENSE("GPL v2");