2 * Copyright 2012 Marvell International Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/interrupt.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/dmaengine.h>
17 #include <linux/platform_device.h>
18 #include <linux/device.h>
19 #include <linux/platform_data/mmp_dma.h>
20 #include <linux/dmapool.h>
21 #include <linux/of_device.h>
22 #include <linux/of_dma.h>
24 #include <linux/dma/mmp-pdma.h>
26 #include "dmaengine.h"
32 #define DSADR(n) (0x0204 + ((n) << 4))
33 #define DTADR(n) (0x0208 + ((n) << 4))
36 #define DCSR_RUN BIT(31) /* Run Bit (read / write) */
37 #define DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
38 #define DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (read / write) */
39 #define DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
40 #define DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
41 #define DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */
42 #define DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */
43 #define DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */
45 #define DCSR_EORIRQEN BIT(28) /* End of Receive Interrupt Enable (R/W) */
46 #define DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */
47 #define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */
48 #define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */
49 #define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */
50 #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */
51 #define DCSR_EORINTR BIT(9) /* The end of Receive */
53 #define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + (((n) & 0x3f) << 2))
54 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */
55 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
57 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
58 #define DDADR_STOP BIT(0) /* Stop (read / write) */
60 #define DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */
61 #define DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */
62 #define DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */
63 #define DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */
64 #define DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */
65 #define DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */
66 #define DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
67 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
68 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
69 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
70 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
71 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
72 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
73 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
75 #define PDMA_MAX_DESC_BYTES DCMD_LENGTH
77 struct mmp_pdma_desc_hw {
78 u32 ddadr; /* Points to the next descriptor + flags */
79 u32 dsadr; /* DSADR value for the current transfer */
80 u32 dtadr; /* DTADR value for the current transfer */
81 u32 dcmd; /* DCMD value for the current transfer */
84 struct mmp_pdma_desc_sw {
85 struct mmp_pdma_desc_hw desc;
86 struct list_head node;
87 struct list_head tx_list;
88 struct dma_async_tx_descriptor async_tx;
93 struct mmp_pdma_chan {
96 struct dma_async_tx_descriptor desc;
97 struct mmp_pdma_phy *phy;
98 enum dma_transfer_direction dir;
99 struct dma_slave_config slave_config;
101 struct mmp_pdma_desc_sw *cyclic_first; /* first desc_sw if channel
102 * is in cyclic mode */
104 /* channel's basic info */
105 struct tasklet_struct tasklet;
111 spinlock_t desc_lock; /* Descriptor list lock */
112 struct list_head chain_pending; /* Link descriptors queue for pending */
113 struct list_head chain_running; /* Link descriptors queue for running */
114 bool idle; /* channel statue machine */
117 struct dma_pool *desc_pool; /* Descriptors pool */
120 struct mmp_pdma_phy {
123 struct mmp_pdma_chan *vchan;
126 struct mmp_pdma_device {
130 struct dma_device device;
131 struct mmp_pdma_phy *phy;
132 spinlock_t phy_lock; /* protect alloc/free phy channels */
135 #define tx_to_mmp_pdma_desc(tx) \
136 container_of(tx, struct mmp_pdma_desc_sw, async_tx)
137 #define to_mmp_pdma_desc(lh) \
138 container_of(lh, struct mmp_pdma_desc_sw, node)
139 #define to_mmp_pdma_chan(dchan) \
140 container_of(dchan, struct mmp_pdma_chan, chan)
141 #define to_mmp_pdma_dev(dmadev) \
142 container_of(dmadev, struct mmp_pdma_device, device)
144 static int mmp_pdma_config_write(struct dma_chan *dchan,
145 struct dma_slave_config *cfg,
146 enum dma_transfer_direction direction);
148 static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr)
150 u32 reg = (phy->idx << 4) + DDADR;
152 writel(addr, phy->base + reg);
155 static void enable_chan(struct mmp_pdma_phy *phy)
162 reg = DRCMR(phy->vchan->drcmr);
163 writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
165 dalgn = readl(phy->base + DALGN);
166 if (phy->vchan->byte_align)
167 dalgn |= 1 << phy->idx;
169 dalgn &= ~(1 << phy->idx);
170 writel(dalgn, phy->base + DALGN);
172 reg = (phy->idx << 2) + DCSR;
173 writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg);
176 static void disable_chan(struct mmp_pdma_phy *phy)
183 reg = (phy->idx << 2) + DCSR;
184 writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg);
187 static int clear_chan_irq(struct mmp_pdma_phy *phy)
190 u32 dint = readl(phy->base + DINT);
191 u32 reg = (phy->idx << 2) + DCSR;
193 if (!(dint & BIT(phy->idx)))
197 dcsr = readl(phy->base + reg);
198 writel(dcsr, phy->base + reg);
199 if ((dcsr & DCSR_BUSERR) && (phy->vchan))
200 dev_warn(phy->vchan->dev, "DCSR_BUSERR\n");
205 static irqreturn_t mmp_pdma_chan_handler(int irq, void *dev_id)
207 struct mmp_pdma_phy *phy = dev_id;
209 if (clear_chan_irq(phy) != 0)
212 tasklet_schedule(&phy->vchan->tasklet);
216 static irqreturn_t mmp_pdma_int_handler(int irq, void *dev_id)
218 struct mmp_pdma_device *pdev = dev_id;
219 struct mmp_pdma_phy *phy;
220 u32 dint = readl(pdev->base + DINT);
226 /* only handle interrupts belonging to pdma driver*/
227 if (i >= pdev->dma_channels)
231 ret = mmp_pdma_chan_handler(irq, phy);
232 if (ret == IRQ_HANDLED)
242 /* lookup free phy channel as descending priority */
243 static struct mmp_pdma_phy *lookup_phy(struct mmp_pdma_chan *pchan)
246 struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device);
247 struct mmp_pdma_phy *phy, *found = NULL;
251 * dma channel priorities
252 * ch 0 - 3, 16 - 19 <--> (0)
253 * ch 4 - 7, 20 - 23 <--> (1)
254 * ch 8 - 11, 24 - 27 <--> (2)
255 * ch 12 - 15, 28 - 31 <--> (3)
258 spin_lock_irqsave(&pdev->phy_lock, flags);
259 for (prio = 0; prio <= ((pdev->dma_channels - 1) & 0xf) >> 2; prio++) {
260 for (i = 0; i < pdev->dma_channels; i++) {
261 if (prio != (i & 0xf) >> 2)
273 spin_unlock_irqrestore(&pdev->phy_lock, flags);
277 static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan)
279 struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device);
286 /* clear the channel mapping in DRCMR */
287 reg = DRCMR(pchan->drcmr);
288 writel(0, pchan->phy->base + reg);
290 spin_lock_irqsave(&pdev->phy_lock, flags);
291 pchan->phy->vchan = NULL;
293 spin_unlock_irqrestore(&pdev->phy_lock, flags);
297 * start_pending_queue - transfer any pending transactions
298 * pending list ==> running list
300 static void start_pending_queue(struct mmp_pdma_chan *chan)
302 struct mmp_pdma_desc_sw *desc;
304 /* still in running, irq will start the pending list */
306 dev_dbg(chan->dev, "DMA controller still busy\n");
310 if (list_empty(&chan->chain_pending)) {
311 /* chance to re-fetch phy channel with higher prio */
312 mmp_pdma_free_phy(chan);
313 dev_dbg(chan->dev, "no pending list\n");
318 chan->phy = lookup_phy(chan);
320 dev_dbg(chan->dev, "no free dma channel\n");
327 * reintilize pending list
329 desc = list_first_entry(&chan->chain_pending,
330 struct mmp_pdma_desc_sw, node);
331 list_splice_tail_init(&chan->chain_pending, &chan->chain_running);
334 * Program the descriptor's address into the DMA controller,
335 * then start the DMA transaction
337 set_desc(chan->phy, desc->async_tx.phys);
338 enable_chan(chan->phy);
343 /* desc->tx_list ==> pending list */
344 static dma_cookie_t mmp_pdma_tx_submit(struct dma_async_tx_descriptor *tx)
346 struct mmp_pdma_chan *chan = to_mmp_pdma_chan(tx->chan);
347 struct mmp_pdma_desc_sw *desc = tx_to_mmp_pdma_desc(tx);
348 struct mmp_pdma_desc_sw *child;
350 dma_cookie_t cookie = -EBUSY;
352 spin_lock_irqsave(&chan->desc_lock, flags);
354 list_for_each_entry(child, &desc->tx_list, node) {
355 cookie = dma_cookie_assign(&child->async_tx);
358 /* softly link to pending list - desc->tx_list ==> pending list */
359 list_splice_tail_init(&desc->tx_list, &chan->chain_pending);
361 spin_unlock_irqrestore(&chan->desc_lock, flags);
366 static struct mmp_pdma_desc_sw *
367 mmp_pdma_alloc_descriptor(struct mmp_pdma_chan *chan)
369 struct mmp_pdma_desc_sw *desc;
372 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
374 dev_err(chan->dev, "out of memory for link descriptor\n");
378 INIT_LIST_HEAD(&desc->tx_list);
379 dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
380 /* each desc has submit */
381 desc->async_tx.tx_submit = mmp_pdma_tx_submit;
382 desc->async_tx.phys = pdesc;
388 * mmp_pdma_alloc_chan_resources - Allocate resources for DMA channel.
390 * This function will create a dma pool for descriptor allocation.
391 * Request irq only when channel is requested
392 * Return - The number of allocated descriptors.
395 static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan)
397 struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
402 chan->desc_pool = dma_pool_create(dev_name(&dchan->dev->device),
404 sizeof(struct mmp_pdma_desc_sw),
405 __alignof__(struct mmp_pdma_desc_sw),
407 if (!chan->desc_pool) {
408 dev_err(chan->dev, "unable to allocate descriptor pool\n");
412 mmp_pdma_free_phy(chan);
418 static void mmp_pdma_free_desc_list(struct mmp_pdma_chan *chan,
419 struct list_head *list)
421 struct mmp_pdma_desc_sw *desc, *_desc;
423 list_for_each_entry_safe(desc, _desc, list, node) {
424 list_del(&desc->node);
425 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
429 static void mmp_pdma_free_chan_resources(struct dma_chan *dchan)
431 struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
434 spin_lock_irqsave(&chan->desc_lock, flags);
435 mmp_pdma_free_desc_list(chan, &chan->chain_pending);
436 mmp_pdma_free_desc_list(chan, &chan->chain_running);
437 spin_unlock_irqrestore(&chan->desc_lock, flags);
439 dma_pool_destroy(chan->desc_pool);
440 chan->desc_pool = NULL;
443 mmp_pdma_free_phy(chan);
447 static struct dma_async_tx_descriptor *
448 mmp_pdma_prep_memcpy(struct dma_chan *dchan,
449 dma_addr_t dma_dst, dma_addr_t dma_src,
450 size_t len, unsigned long flags)
452 struct mmp_pdma_chan *chan;
453 struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
462 chan = to_mmp_pdma_chan(dchan);
463 chan->byte_align = false;
466 chan->dir = DMA_MEM_TO_MEM;
467 chan->dcmd = DCMD_INCTRGADDR | DCMD_INCSRCADDR;
468 chan->dcmd |= DCMD_BURST32;
472 /* Allocate the link descriptor from DMA pool */
473 new = mmp_pdma_alloc_descriptor(chan);
475 dev_err(chan->dev, "no memory for desc\n");
479 copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
480 if (dma_src & 0x7 || dma_dst & 0x7)
481 chan->byte_align = true;
483 new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy);
484 new->desc.dsadr = dma_src;
485 new->desc.dtadr = dma_dst;
490 prev->desc.ddadr = new->async_tx.phys;
492 new->async_tx.cookie = 0;
493 async_tx_ack(&new->async_tx);
498 if (chan->dir == DMA_MEM_TO_DEV) {
500 } else if (chan->dir == DMA_DEV_TO_MEM) {
502 } else if (chan->dir == DMA_MEM_TO_MEM) {
507 /* Insert the link descriptor to the LD ring */
508 list_add_tail(&new->node, &first->tx_list);
511 first->async_tx.flags = flags; /* client is in control of this ack */
512 first->async_tx.cookie = -EBUSY;
514 /* last desc and fire IRQ */
515 new->desc.ddadr = DDADR_STOP;
516 new->desc.dcmd |= DCMD_ENDIRQEN;
518 chan->cyclic_first = NULL;
520 return &first->async_tx;
524 mmp_pdma_free_desc_list(chan, &first->tx_list);
528 static struct dma_async_tx_descriptor *
529 mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
530 unsigned int sg_len, enum dma_transfer_direction dir,
531 unsigned long flags, void *context)
533 struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
534 struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL;
536 struct scatterlist *sg;
540 if ((sgl == NULL) || (sg_len == 0))
543 chan->byte_align = false;
545 mmp_pdma_config_write(dchan, &chan->slave_config, dir);
547 for_each_sg(sgl, sg, sg_len, i) {
548 addr = sg_dma_address(sg);
549 avail = sg_dma_len(sgl);
552 len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
554 chan->byte_align = true;
556 /* allocate and populate the descriptor */
557 new = mmp_pdma_alloc_descriptor(chan);
559 dev_err(chan->dev, "no memory for desc\n");
563 new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len);
564 if (dir == DMA_MEM_TO_DEV) {
565 new->desc.dsadr = addr;
566 new->desc.dtadr = chan->dev_addr;
568 new->desc.dsadr = chan->dev_addr;
569 new->desc.dtadr = addr;
575 prev->desc.ddadr = new->async_tx.phys;
577 new->async_tx.cookie = 0;
578 async_tx_ack(&new->async_tx);
581 /* Insert the link descriptor to the LD ring */
582 list_add_tail(&new->node, &first->tx_list);
584 /* update metadata */
590 first->async_tx.cookie = -EBUSY;
591 first->async_tx.flags = flags;
593 /* last desc and fire IRQ */
594 new->desc.ddadr = DDADR_STOP;
595 new->desc.dcmd |= DCMD_ENDIRQEN;
598 chan->cyclic_first = NULL;
600 return &first->async_tx;
604 mmp_pdma_free_desc_list(chan, &first->tx_list);
608 static struct dma_async_tx_descriptor *
609 mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan,
610 dma_addr_t buf_addr, size_t len, size_t period_len,
611 enum dma_transfer_direction direction,
614 struct mmp_pdma_chan *chan;
615 struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
616 dma_addr_t dma_src, dma_dst;
618 if (!dchan || !len || !period_len)
621 /* the buffer length must be a multiple of period_len */
622 if (len % period_len != 0)
625 if (period_len > PDMA_MAX_DESC_BYTES)
628 chan = to_mmp_pdma_chan(dchan);
629 mmp_pdma_config_write(dchan, &chan->slave_config, direction);
634 dma_dst = chan->dev_addr;
638 dma_src = chan->dev_addr;
641 dev_err(chan->dev, "Unsupported direction for cyclic DMA\n");
645 chan->dir = direction;
648 /* Allocate the link descriptor from DMA pool */
649 new = mmp_pdma_alloc_descriptor(chan);
651 dev_err(chan->dev, "no memory for desc\n");
655 new->desc.dcmd = (chan->dcmd | DCMD_ENDIRQEN |
656 (DCMD_LENGTH & period_len));
657 new->desc.dsadr = dma_src;
658 new->desc.dtadr = dma_dst;
663 prev->desc.ddadr = new->async_tx.phys;
665 new->async_tx.cookie = 0;
666 async_tx_ack(&new->async_tx);
671 if (chan->dir == DMA_MEM_TO_DEV)
672 dma_src += period_len;
674 dma_dst += period_len;
676 /* Insert the link descriptor to the LD ring */
677 list_add_tail(&new->node, &first->tx_list);
680 first->async_tx.flags = flags; /* client is in control of this ack */
681 first->async_tx.cookie = -EBUSY;
683 /* make the cyclic link */
684 new->desc.ddadr = first->async_tx.phys;
685 chan->cyclic_first = first;
687 return &first->async_tx;
691 mmp_pdma_free_desc_list(chan, &first->tx_list);
695 static int mmp_pdma_config_write(struct dma_chan *dchan,
696 struct dma_slave_config *cfg,
697 enum dma_transfer_direction direction)
699 struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
700 u32 maxburst = 0, addr = 0;
701 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
706 if (direction == DMA_DEV_TO_MEM) {
707 chan->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC;
708 maxburst = cfg->src_maxburst;
709 width = cfg->src_addr_width;
710 addr = cfg->src_addr;
711 } else if (direction == DMA_MEM_TO_DEV) {
712 chan->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG;
713 maxburst = cfg->dst_maxburst;
714 width = cfg->dst_addr_width;
715 addr = cfg->dst_addr;
718 if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
719 chan->dcmd |= DCMD_WIDTH1;
720 else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
721 chan->dcmd |= DCMD_WIDTH2;
722 else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
723 chan->dcmd |= DCMD_WIDTH4;
726 chan->dcmd |= DCMD_BURST8;
727 else if (maxburst == 16)
728 chan->dcmd |= DCMD_BURST16;
729 else if (maxburst == 32)
730 chan->dcmd |= DCMD_BURST32;
732 chan->dir = direction;
733 chan->dev_addr = addr;
734 /* FIXME: drivers should be ported over to use the filter
735 * function. Once that's done, the following two lines can
739 chan->drcmr = cfg->slave_id;
744 static int mmp_pdma_config(struct dma_chan *dchan,
745 struct dma_slave_config *cfg)
747 struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
749 memcpy(&chan->slave_config, cfg, sizeof(*cfg));
753 static int mmp_pdma_terminate_all(struct dma_chan *dchan)
755 struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
761 disable_chan(chan->phy);
762 mmp_pdma_free_phy(chan);
763 spin_lock_irqsave(&chan->desc_lock, flags);
764 mmp_pdma_free_desc_list(chan, &chan->chain_pending);
765 mmp_pdma_free_desc_list(chan, &chan->chain_running);
766 spin_unlock_irqrestore(&chan->desc_lock, flags);
772 static unsigned int mmp_pdma_residue(struct mmp_pdma_chan *chan,
775 struct mmp_pdma_desc_sw *sw;
776 u32 curr, residue = 0;
778 bool cyclic = chan->cyclic_first != NULL;
781 * If the channel does not have a phy pointer anymore, it has already
782 * been completed. Therefore, its residue is 0.
787 if (chan->dir == DMA_DEV_TO_MEM)
788 curr = readl(chan->phy->base + DTADR(chan->phy->idx));
790 curr = readl(chan->phy->base + DSADR(chan->phy->idx));
792 list_for_each_entry(sw, &chan->chain_running, node) {
795 if (chan->dir == DMA_DEV_TO_MEM)
796 start = sw->desc.dtadr;
798 start = sw->desc.dsadr;
800 len = sw->desc.dcmd & DCMD_LENGTH;
804 * 'passed' will be latched once we found the descriptor which
805 * lies inside the boundaries of the curr pointer. All
806 * descriptors that occur in the list _after_ we found that
807 * partially handled descriptor are still to be processed and
808 * are hence added to the residual bytes counter.
813 } else if (curr >= start && curr <= end) {
814 residue += end - curr;
819 * Descriptors that have the ENDIRQEN bit set mark the end of a
820 * transaction chain, and the cookie assigned with it has been
821 * returned previously from mmp_pdma_tx_submit().
823 * In case we have multiple transactions in the running chain,
824 * and the cookie does not match the one the user asked us
825 * about, reset the state variables and start over.
827 * This logic does not apply to cyclic transactions, where all
828 * descriptors have the ENDIRQEN bit set, and for which we
829 * can't have multiple transactions on one channel anyway.
831 if (cyclic || !(sw->desc.dcmd & DCMD_ENDIRQEN))
834 if (sw->async_tx.cookie == cookie) {
842 /* We should only get here in case of cyclic transactions */
846 static enum dma_status mmp_pdma_tx_status(struct dma_chan *dchan,
848 struct dma_tx_state *txstate)
850 struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
853 ret = dma_cookie_status(dchan, cookie, txstate);
854 if (likely(ret != DMA_ERROR))
855 dma_set_residue(txstate, mmp_pdma_residue(chan, cookie));
861 * mmp_pdma_issue_pending - Issue the DMA start command
862 * pending list ==> running list
864 static void mmp_pdma_issue_pending(struct dma_chan *dchan)
866 struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
869 spin_lock_irqsave(&chan->desc_lock, flags);
870 start_pending_queue(chan);
871 spin_unlock_irqrestore(&chan->desc_lock, flags);
879 static void dma_do_tasklet(unsigned long data)
881 struct mmp_pdma_chan *chan = (struct mmp_pdma_chan *)data;
882 struct mmp_pdma_desc_sw *desc, *_desc;
883 LIST_HEAD(chain_cleanup);
885 struct dmaengine_desc_callback cb;
887 if (chan->cyclic_first) {
888 spin_lock_irqsave(&chan->desc_lock, flags);
889 desc = chan->cyclic_first;
890 dmaengine_desc_get_callback(&desc->async_tx, &cb);
891 spin_unlock_irqrestore(&chan->desc_lock, flags);
893 dmaengine_desc_callback_invoke(&cb, NULL);
898 /* submit pending list; callback for each desc; free desc */
899 spin_lock_irqsave(&chan->desc_lock, flags);
901 list_for_each_entry_safe(desc, _desc, &chan->chain_running, node) {
903 * move the descriptors to a temporary list so we can drop
904 * the lock during the entire cleanup operation
906 list_move(&desc->node, &chain_cleanup);
909 * Look for the first list entry which has the ENDIRQEN flag
910 * set. That is the descriptor we got an interrupt for, so
911 * complete that transaction and its cookie.
913 if (desc->desc.dcmd & DCMD_ENDIRQEN) {
914 dma_cookie_t cookie = desc->async_tx.cookie;
915 dma_cookie_complete(&desc->async_tx);
916 dev_dbg(chan->dev, "completed_cookie=%d\n", cookie);
922 * The hardware is idle and ready for more when the
923 * chain_running list is empty.
925 chan->idle = list_empty(&chan->chain_running);
927 /* Start any pending transactions automatically */
928 start_pending_queue(chan);
929 spin_unlock_irqrestore(&chan->desc_lock, flags);
931 /* Run the callback for each descriptor, in order */
932 list_for_each_entry_safe(desc, _desc, &chain_cleanup, node) {
933 struct dma_async_tx_descriptor *txd = &desc->async_tx;
935 /* Remove from the list of transactions */
936 list_del(&desc->node);
937 /* Run the link descriptor callback function */
938 dmaengine_desc_get_callback(txd, &cb);
939 dmaengine_desc_callback_invoke(&cb, NULL);
941 dma_pool_free(chan->desc_pool, desc, txd->phys);
945 static int mmp_pdma_remove(struct platform_device *op)
947 struct mmp_pdma_device *pdev = platform_get_drvdata(op);
948 struct mmp_pdma_phy *phy;
949 int i, irq = 0, irq_num = 0;
952 for (i = 0; i < pdev->dma_channels; i++) {
953 if (platform_get_irq(op, i) > 0)
957 if (irq_num != pdev->dma_channels) {
958 irq = platform_get_irq(op, 0);
959 devm_free_irq(&op->dev, irq, pdev);
961 for (i = 0; i < pdev->dma_channels; i++) {
963 irq = platform_get_irq(op, i);
964 devm_free_irq(&op->dev, irq, phy);
968 dma_async_device_unregister(&pdev->device);
972 static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev, int idx, int irq)
974 struct mmp_pdma_phy *phy = &pdev->phy[idx];
975 struct mmp_pdma_chan *chan;
978 chan = devm_kzalloc(pdev->dev, sizeof(*chan), GFP_KERNEL);
983 phy->base = pdev->base;
986 ret = devm_request_irq(pdev->dev, irq, mmp_pdma_chan_handler,
987 IRQF_SHARED, "pdma", phy);
989 dev_err(pdev->dev, "channel request irq fail!\n");
994 spin_lock_init(&chan->desc_lock);
995 chan->dev = pdev->dev;
996 chan->chan.device = &pdev->device;
997 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
998 INIT_LIST_HEAD(&chan->chain_pending);
999 INIT_LIST_HEAD(&chan->chain_running);
1001 /* register virt channel to dma engine */
1002 list_add_tail(&chan->chan.device_node, &pdev->device.channels);
1007 static const struct of_device_id mmp_pdma_dt_ids[] = {
1008 { .compatible = "marvell,pdma-1.0", },
1011 MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids);
1013 static struct dma_chan *mmp_pdma_dma_xlate(struct of_phandle_args *dma_spec,
1014 struct of_dma *ofdma)
1016 struct mmp_pdma_device *d = ofdma->of_dma_data;
1017 struct dma_chan *chan;
1019 chan = dma_get_any_slave_channel(&d->device);
1023 to_mmp_pdma_chan(chan)->drcmr = dma_spec->args[0];
1028 static int mmp_pdma_probe(struct platform_device *op)
1030 struct mmp_pdma_device *pdev;
1031 const struct of_device_id *of_id;
1032 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
1033 struct resource *iores;
1034 int i, ret, irq = 0;
1035 int dma_channels = 0, irq_num = 0;
1036 const enum dma_slave_buswidth widths =
1037 DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |
1038 DMA_SLAVE_BUSWIDTH_4_BYTES;
1040 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
1044 pdev->dev = &op->dev;
1046 spin_lock_init(&pdev->phy_lock);
1048 iores = platform_get_resource(op, IORESOURCE_MEM, 0);
1049 pdev->base = devm_ioremap_resource(pdev->dev, iores);
1050 if (IS_ERR(pdev->base))
1051 return PTR_ERR(pdev->base);
1053 of_id = of_match_device(mmp_pdma_dt_ids, pdev->dev);
1055 of_property_read_u32(pdev->dev->of_node, "#dma-channels",
1057 else if (pdata && pdata->dma_channels)
1058 dma_channels = pdata->dma_channels;
1060 dma_channels = 32; /* default 32 channel */
1061 pdev->dma_channels = dma_channels;
1063 for (i = 0; i < dma_channels; i++) {
1064 if (platform_get_irq(op, i) > 0)
1068 pdev->phy = devm_kcalloc(pdev->dev, dma_channels, sizeof(*pdev->phy),
1070 if (pdev->phy == NULL)
1073 INIT_LIST_HEAD(&pdev->device.channels);
1075 if (irq_num != dma_channels) {
1076 /* all chan share one irq, demux inside */
1077 irq = platform_get_irq(op, 0);
1078 ret = devm_request_irq(pdev->dev, irq, mmp_pdma_int_handler,
1079 IRQF_SHARED, "pdma", pdev);
1084 for (i = 0; i < dma_channels; i++) {
1085 irq = (irq_num != dma_channels) ? 0 : platform_get_irq(op, i);
1086 ret = mmp_pdma_chan_init(pdev, i, irq);
1091 dma_cap_set(DMA_SLAVE, pdev->device.cap_mask);
1092 dma_cap_set(DMA_MEMCPY, pdev->device.cap_mask);
1093 dma_cap_set(DMA_CYCLIC, pdev->device.cap_mask);
1094 dma_cap_set(DMA_PRIVATE, pdev->device.cap_mask);
1095 pdev->device.dev = &op->dev;
1096 pdev->device.device_alloc_chan_resources = mmp_pdma_alloc_chan_resources;
1097 pdev->device.device_free_chan_resources = mmp_pdma_free_chan_resources;
1098 pdev->device.device_tx_status = mmp_pdma_tx_status;
1099 pdev->device.device_prep_dma_memcpy = mmp_pdma_prep_memcpy;
1100 pdev->device.device_prep_slave_sg = mmp_pdma_prep_slave_sg;
1101 pdev->device.device_prep_dma_cyclic = mmp_pdma_prep_dma_cyclic;
1102 pdev->device.device_issue_pending = mmp_pdma_issue_pending;
1103 pdev->device.device_config = mmp_pdma_config;
1104 pdev->device.device_terminate_all = mmp_pdma_terminate_all;
1105 pdev->device.copy_align = DMAENGINE_ALIGN_8_BYTES;
1106 pdev->device.src_addr_widths = widths;
1107 pdev->device.dst_addr_widths = widths;
1108 pdev->device.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1109 pdev->device.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1111 if (pdev->dev->coherent_dma_mask)
1112 dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask);
1114 dma_set_mask(pdev->dev, DMA_BIT_MASK(64));
1116 ret = dma_async_device_register(&pdev->device);
1118 dev_err(pdev->device.dev, "unable to register\n");
1122 if (op->dev.of_node) {
1123 /* Device-tree DMA controller registration */
1124 ret = of_dma_controller_register(op->dev.of_node,
1125 mmp_pdma_dma_xlate, pdev);
1127 dev_err(&op->dev, "of_dma_controller_register failed\n");
1132 platform_set_drvdata(op, pdev);
1133 dev_info(pdev->device.dev, "initialized %d channels\n", dma_channels);
1137 static const struct platform_device_id mmp_pdma_id_table[] = {
1142 static struct platform_driver mmp_pdma_driver = {
1145 .of_match_table = mmp_pdma_dt_ids,
1147 .id_table = mmp_pdma_id_table,
1148 .probe = mmp_pdma_probe,
1149 .remove = mmp_pdma_remove,
1152 bool mmp_pdma_filter_fn(struct dma_chan *chan, void *param)
1154 struct mmp_pdma_chan *c = to_mmp_pdma_chan(chan);
1156 if (chan->device->dev->driver != &mmp_pdma_driver.driver)
1159 c->drcmr = *(unsigned int *)param;
1163 EXPORT_SYMBOL_GPL(mmp_pdma_filter_fn);
1165 module_platform_driver(mmp_pdma_driver);
1167 MODULE_DESCRIPTION("MARVELL MMP Peripheral DMA Driver");
1168 MODULE_AUTHOR("Marvell International Ltd.");
1169 MODULE_LICENSE("GPL v2");