1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #include <linux/init.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
7 #include <linux/device.h>
8 #include <linux/io-64-nonatomic-lo-hi.h>
9 #include <linux/dmaengine.h>
10 #include <uapi/linux/idxd.h>
11 #include "../dmaengine.h"
12 #include "registers.h"
15 static inline struct idxd_wq *to_idxd_wq(struct dma_chan *c)
17 struct idxd_dma_chan *idxd_chan;
19 idxd_chan = container_of(c, struct idxd_dma_chan, chan);
23 void idxd_dma_complete_txd(struct idxd_desc *desc,
24 enum idxd_complete_type comp_type)
26 struct dma_async_tx_descriptor *tx;
27 struct dmaengine_result res;
30 if (desc->completion->status == DSA_COMP_SUCCESS)
31 res.result = DMA_TRANS_NOERROR;
32 else if (desc->completion->status)
33 res.result = DMA_TRANS_WRITE_FAILED;
34 else if (comp_type == IDXD_COMPLETE_ABORT)
35 res.result = DMA_TRANS_ABORTED;
40 if (complete && tx->cookie) {
41 dma_cookie_complete(tx);
42 dma_descriptor_unmap(tx);
43 dmaengine_desc_get_callback_invoke(tx, &res);
45 tx->callback_result = NULL;
49 static void op_flag_setup(unsigned long flags, u32 *desc_flags)
51 *desc_flags = IDXD_OP_FLAG_CRAV | IDXD_OP_FLAG_RCR;
52 if (flags & DMA_PREP_INTERRUPT)
53 *desc_flags |= IDXD_OP_FLAG_RCI;
56 static inline void set_completion_address(struct idxd_desc *desc,
59 *compl_addr = desc->compl_dma;
62 static inline void idxd_prep_desc_common(struct idxd_wq *wq,
63 struct dsa_hw_desc *hw, char opcode,
64 u64 addr_f1, u64 addr_f2, u64 len,
69 hw->src_addr = addr_f1;
70 hw->dst_addr = addr_f2;
72 hw->priv = !!(wq->type == IDXD_WQT_KERNEL);
73 hw->completion_addr = compl;
76 static struct dma_async_tx_descriptor *
77 idxd_dma_submit_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
78 dma_addr_t dma_src, size_t len, unsigned long flags)
80 struct idxd_wq *wq = to_idxd_wq(c);
82 struct idxd_device *idxd = wq->idxd;
83 struct idxd_desc *desc;
85 if (wq->state != IDXD_WQ_ENABLED)
88 if (len > idxd->max_xfer_bytes)
91 op_flag_setup(flags, &desc_flags);
92 desc = idxd_alloc_desc(wq, IDXD_OP_BLOCK);
96 idxd_prep_desc_common(wq, desc->hw, DSA_OPCODE_MEMMOVE,
97 dma_src, dma_dest, len, desc->compl_dma,
100 desc->txd.flags = flags;
105 static int idxd_dma_alloc_chan_resources(struct dma_chan *chan)
107 struct idxd_wq *wq = to_idxd_wq(chan);
108 struct device *dev = &wq->idxd->pdev->dev;
111 dev_dbg(dev, "%s: client_count: %d\n", __func__,
112 idxd_wq_refcount(wq));
116 static void idxd_dma_free_chan_resources(struct dma_chan *chan)
118 struct idxd_wq *wq = to_idxd_wq(chan);
119 struct device *dev = &wq->idxd->pdev->dev;
122 dev_dbg(dev, "%s: client_count: %d\n", __func__,
123 idxd_wq_refcount(wq));
126 static enum dma_status idxd_dma_tx_status(struct dma_chan *dma_chan,
128 struct dma_tx_state *txstate)
130 return DMA_OUT_OF_ORDER;
134 * issue_pending() does not need to do anything since tx_submit() does the job
137 static void idxd_dma_issue_pending(struct dma_chan *dma_chan)
141 static dma_cookie_t idxd_dma_tx_submit(struct dma_async_tx_descriptor *tx)
143 struct dma_chan *c = tx->chan;
144 struct idxd_wq *wq = to_idxd_wq(c);
147 struct idxd_desc *desc = container_of(tx, struct idxd_desc, txd);
149 cookie = dma_cookie_assign(tx);
151 rc = idxd_submit_desc(wq, desc);
153 idxd_free_desc(wq, desc);
160 static void idxd_dma_release(struct dma_device *device)
162 struct idxd_dma_dev *idxd_dma = container_of(device, struct idxd_dma_dev, dma);
167 int idxd_register_dma_device(struct idxd_device *idxd)
169 struct idxd_dma_dev *idxd_dma;
170 struct dma_device *dma;
171 struct device *dev = &idxd->pdev->dev;
174 idxd_dma = kzalloc_node(sizeof(*idxd_dma), GFP_KERNEL, dev_to_node(dev));
178 dma = &idxd_dma->dma;
179 INIT_LIST_HEAD(&dma->channels);
182 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
183 dma_cap_set(DMA_COMPLETION_NO_ORDER, dma->cap_mask);
184 dma->device_release = idxd_dma_release;
186 if (idxd->hw.opcap.bits[0] & IDXD_OPCAP_MEMMOVE) {
187 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
188 dma->device_prep_dma_memcpy = idxd_dma_submit_memcpy;
191 dma->device_tx_status = idxd_dma_tx_status;
192 dma->device_issue_pending = idxd_dma_issue_pending;
193 dma->device_alloc_chan_resources = idxd_dma_alloc_chan_resources;
194 dma->device_free_chan_resources = idxd_dma_free_chan_resources;
196 rc = dma_async_device_register(dma);
202 idxd_dma->idxd = idxd;
204 * This pointer is protected by the refs taken by the dma_chan. It will remain valid
205 * as long as there are outstanding channels.
207 idxd->idxd_dma = idxd_dma;
211 void idxd_unregister_dma_device(struct idxd_device *idxd)
213 dma_async_device_unregister(&idxd->idxd_dma->dma);
216 int idxd_register_dma_channel(struct idxd_wq *wq)
218 struct idxd_device *idxd = wq->idxd;
219 struct dma_device *dma = &idxd->idxd_dma->dma;
220 struct device *dev = &idxd->pdev->dev;
221 struct idxd_dma_chan *idxd_chan;
222 struct dma_chan *chan;
225 idxd_chan = kzalloc_node(sizeof(*idxd_chan), GFP_KERNEL, dev_to_node(dev));
229 chan = &idxd_chan->chan;
231 list_add_tail(&chan->device_node, &dma->channels);
233 for (i = 0; i < wq->num_descs; i++) {
234 struct idxd_desc *desc = wq->descs[i];
236 dma_async_tx_descriptor_init(&desc->txd, chan);
237 desc->txd.tx_submit = idxd_dma_tx_submit;
240 rc = dma_async_device_channel_register(dma, chan);
246 wq->idxd_chan = idxd_chan;
248 get_device(&wq->conf_dev);
253 void idxd_unregister_dma_channel(struct idxd_wq *wq)
255 struct idxd_dma_chan *idxd_chan = wq->idxd_chan;
256 struct dma_chan *chan = &idxd_chan->chan;
257 struct idxd_dma_dev *idxd_dma = wq->idxd->idxd_dma;
259 dma_async_device_channel_unregister(&idxd_dma->dma, chan);
260 list_del(&chan->device_node);
261 kfree(wq->idxd_chan);
262 wq->idxd_chan = NULL;
263 put_device(&wq->conf_dev);