drivers/dma/fsl-edma-main.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * drivers/dma/fsl-edma.c
   4  *
   5  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   6  *
   7  * Driver for the Freescale eDMA engine with flexible channel multiplexing
   8  * capability for DMA request sources. The eDMA block can be found on some
   9  * Vybrid and Layerscape SoCs.
  10  */
  11
  12 #include <dt-bindings/dma/fsl-edma.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/module.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/clk.h>
  17 #include <linux/of.h>
  18 #include <linux/of_dma.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/property.h>
  23
  24 #include "fsl-edma-common.h"
  25
  26 static void fsl_edma_synchronize(struct dma_chan *chan)
  27 {
  28         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
  29
  30         vchan_synchronize(&fsl_chan->vchan);
  31 }
  32
  33 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
  34 {
  35         struct fsl_edma_engine *fsl_edma = dev_id;
  36         unsigned int intr, ch;
  37         struct edma_regs *regs = &fsl_edma->regs;
  38
  39         intr = edma_readl(fsl_edma, regs->intl);
  40         if (!intr)
  41                 return IRQ_NONE;
  42
  43         for (ch = 0; ch < fsl_edma->n_chans; ch++) {
  44                 if (intr & (0x1 << ch)) {
  45                         edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
  46                         fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]);
  47                 }
  48         }
  49         return IRQ_HANDLED;
  50 }
  51
  52 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id)
  53 {
  54         struct fsl_edma_chan *fsl_chan = dev_id;
  55         unsigned int intr;
  56
  57         intr = edma_readl_chreg(fsl_chan, ch_int);
  58         if (!intr)
  59                 return IRQ_HANDLED;
  60
  61         edma_writel_chreg(fsl_chan, 1, ch_int);
  62
  63         fsl_edma_tx_chan_handler(fsl_chan);
  64
  65         return IRQ_HANDLED;
  66 }
  67
  68 static irqreturn_t fsl_edma2_tx_handler(int irq, void *devi_id)
  69 {
  70         struct fsl_edma_chan *fsl_chan = devi_id;
  71
  72         return fsl_edma_tx_handler(irq, fsl_chan->edma);
  73 }
  74
  75 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
  76 {
  77         struct fsl_edma_engine *fsl_edma = dev_id;
  78         unsigned int err, ch;
  79         struct edma_regs *regs = &fsl_edma->regs;
  80
  81         err = edma_readl(fsl_edma, regs->errl);
  82         if (!err)
  83                 return IRQ_NONE;
  84
  85         for (ch = 0; ch < fsl_edma->n_chans; ch++) {
  86                 if (err & (0x1 << ch)) {
  87                         fsl_edma_disable_request(&fsl_edma->chans[ch]);
  88                         edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
  89                         fsl_edma_err_chan_handler(&fsl_edma->chans[ch]);
  90                 }
  91         }
  92         return IRQ_HANDLED;
  93 }
  94
  95 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
  96 {
  97         if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
  98                 return IRQ_HANDLED;
  99
 100         return fsl_edma_err_handler(irq, dev_id);
 101 }
 102
 103 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
 104                 struct of_dma *ofdma)
 105 {
 106         struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
 107         struct dma_chan *chan, *_chan;
 108         struct fsl_edma_chan *fsl_chan;
 109         u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
 110         unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
 111
 112         if (dma_spec->args_count != 2)
 113                 return NULL;
 114
 115         guard(mutex)(&fsl_edma->fsl_edma_mutex);
 116
 117         list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
 118                 if (chan->client_count)
 119                         continue;
 120                 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
 121                         chan = dma_get_slave_channel(chan);
 122                         if (chan) {
 123                                 chan->device->privatecnt++;
 124                                 fsl_chan = to_fsl_edma_chan(chan);
 125                                 fsl_chan->srcid = dma_spec->args[1];
 126
 127                                 if (!fsl_chan->srcid) {
 128                                         dev_err(&fsl_chan->pdev->dev, "Invalidate srcid %d\n",
 129                                                 fsl_chan->srcid);
 130                                         return NULL;
 131                                 }
 132
 133                                 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid,
 134                                                 true);
 135                                 return chan;
 136                         }
 137                 }
 138         }
 139         return NULL;
 140 }
 141
 142 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
 143                                         struct of_dma *ofdma)
 144 {
 145         struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
 146         struct dma_chan *chan, *_chan;
 147         struct fsl_edma_chan *fsl_chan;
 148         bool b_chmux;
 149         int i;
 150
 151         if (dma_spec->args_count != 3)
 152                 return NULL;
 153
 154         b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX);
 155
 156         mutex_lock(&fsl_edma->fsl_edma_mutex);
 157         list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels,
 158                                         device_node) {
 159
 160                 if (chan->client_count)
 161                         continue;
 162
 163                 fsl_chan = to_fsl_edma_chan(chan);
 164                 i = fsl_chan - fsl_edma->chans;
 165
 166                 fsl_chan->priority = dma_spec->args[1];
 167                 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX;
 168                 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE;
 169                 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO;
 170
 171                 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1))
 172                         continue;
 173
 174                 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1))
 175                         continue;
 176
 177                 if (!b_chmux && i == dma_spec->args[0]) {
 178                         chan = dma_get_slave_channel(chan);
 179                         chan->device->privatecnt++;
 180                         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 181                         return chan;
 182                 } else if (b_chmux && !fsl_chan->srcid) {
 183                         /* if controller support channel mux, choose a free channel */
 184                         chan = dma_get_slave_channel(chan);
 185                         chan->device->privatecnt++;
 186                         fsl_chan->srcid = dma_spec->args[0];
 187                         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 188                         return chan;
 189                 }
 190         }
 191         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 192         return NULL;
 193 }
 194
 195 static int
 196 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 197 {
 198         int ret;
 199
 200         edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
 201
 202         fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
 203         if (fsl_edma->txirq < 0)
 204                 return fsl_edma->txirq;
 205
 206         fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
 207         if (fsl_edma->errirq < 0)
 208                 return fsl_edma->errirq;
 209
 210         if (fsl_edma->txirq == fsl_edma->errirq) {
 211                 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
 212                                 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
 213                 if (ret) {
 214                         dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
 215                         return ret;
 216                 }
 217         } else {
 218                 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
 219                                 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
 220                 if (ret) {
 221                         dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
 222                         return ret;
 223                 }
 224
 225                 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
 226                                 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
 227                 if (ret) {
 228                         dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
 229                         return ret;
 230                 }
 231         }
 232
 233         return 0;
 234 }
 235
 236 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 237 {
 238         int i;
 239
 240         for (i = 0; i < fsl_edma->n_chans; i++) {
 241
 242                 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
 243
 244                 if (fsl_edma->chan_masked & BIT(i))
 245                         continue;
 246
 247                 /* request channel irq */
 248                 fsl_chan->txirq = platform_get_irq(pdev, i);
 249                 if (fsl_chan->txirq < 0)
 250                         return  -EINVAL;
 251
 252                 fsl_chan->irq_handler = fsl_edma3_tx_handler;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int
 259 fsl_edma2_irq_init(struct platform_device *pdev,
 260                    struct fsl_edma_engine *fsl_edma)
 261 {
 262         int i, ret, irq;
 263         int count;
 264
 265         edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
 266
 267         count = platform_irq_count(pdev);
 268         dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
 269         if (count <= 2) {
 270                 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
 271                 return -EINVAL;
 272         }
 273         /*
 274          * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
 275          * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
 276          * For now, just simply request irq without IRQF_SHARED flag, since 16
 277          * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
 278          */
 279         for (i = 0; i < count; i++) {
 280                 irq = platform_get_irq(pdev, i);
 281                 ret = 0;
 282                 if (irq < 0)
 283                         return -ENXIO;
 284
 285                 /* The last IRQ is for eDMA err */
 286                 if (i == count - 1) {
 287                         ret = devm_request_irq(&pdev->dev, irq,
 288                                                 fsl_edma_err_handler,
 289                                                 0, "eDMA2-ERR", fsl_edma);
 290                 } else {
 291                         fsl_edma->chans[i].txirq = irq;
 292                         fsl_edma->chans[i].irq_handler = fsl_edma2_tx_handler;
 293                 }
 294
 295                 if (ret)
 296                         return ret;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static void fsl_edma_irq_exit(
 303                 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 304 {
 305         if (fsl_edma->txirq == fsl_edma->errirq) {
 306                 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
 307         } else {
 308                 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
 309                 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
 310         }
 311 }
 312
 313 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
 314 {
 315         int i;
 316
 317         for (i = 0; i < nr_clocks; i++)
 318                 clk_disable_unprepare(fsl_edma->muxclk[i]);
 319 }
 320
 321 static struct fsl_edma_drvdata vf610_data = {
 322         .dmamuxs = DMAMUX_NR,
 323         .flags = FSL_EDMA_DRV_WRAP_IO,
 324         .chreg_off = EDMA_TCD,
 325         .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
 326         .setup_irq = fsl_edma_irq_init,
 327 };
 328
 329 static struct fsl_edma_drvdata ls1028a_data = {
 330         .dmamuxs = DMAMUX_NR,
 331         .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO,
 332         .chreg_off = EDMA_TCD,
 333         .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
 334         .setup_irq = fsl_edma_irq_init,
 335 };
 336
 337 static struct fsl_edma_drvdata imx7ulp_data = {
 338         .dmamuxs = 1,
 339         .chreg_off = EDMA_TCD,
 340         .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
 341         .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
 342         .setup_irq = fsl_edma2_irq_init,
 343 };
 344
 345 static struct fsl_edma_drvdata imx8qm_data = {
 346         .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MEM_REMOTE,
 347         .chreg_space_sz = 0x10000,
 348         .chreg_off = 0x10000,
 349         .setup_irq = fsl_edma3_irq_init,
 350 };
 351
 352 static struct fsl_edma_drvdata imx8ulp_data = {
 353         .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK |
 354                  FSL_EDMA_DRV_EDMA3,
 355         .chreg_space_sz = 0x10000,
 356         .chreg_off = 0x10000,
 357         .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
 358         .mux_skip = 0x10000,
 359         .setup_irq = fsl_edma3_irq_init,
 360 };
 361
 362 static struct fsl_edma_drvdata imx93_data3 = {
 363         .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
 364         .chreg_space_sz = 0x10000,
 365         .chreg_off = 0x10000,
 366         .setup_irq = fsl_edma3_irq_init,
 367 };
 368
 369 static struct fsl_edma_drvdata imx93_data4 = {
 370         .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4,
 371         .chreg_space_sz = 0x8000,
 372         .chreg_off = 0x10000,
 373         .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
 374         .mux_skip = 0x8000,
 375         .setup_irq = fsl_edma3_irq_init,
 376 };
 377
 378 static struct fsl_edma_drvdata imx95_data5 = {
 379         .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 |
 380                  FSL_EDMA_DRV_TCD64,
 381         .chreg_space_sz = 0x8000,
 382         .chreg_off = 0x10000,
 383         .mux_off = 0x200,
 384         .mux_skip = sizeof(u32),
 385         .setup_irq = fsl_edma3_irq_init,
 386 };
 387
 388 static const struct of_device_id fsl_edma_dt_ids[] = {
 389         { .compatible = "fsl,vf610-edma", .data = &vf610_data},
 390         { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
 391         { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
 392         { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
 393         { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data},
 394         { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
 395         { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
 396         { .compatible = "fsl,imx95-edma5", .data = &imx95_data5},
 397         { /* sentinel */ }
 398 };
 399 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
 400
 401 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 402 {
 403         struct fsl_edma_chan *fsl_chan;
 404         struct device_link *link;
 405         struct device *pd_chan;
 406         struct device *dev;
 407         int i;
 408
 409         dev = &pdev->dev;
 410
 411         for (i = 0; i < fsl_edma->n_chans; i++) {
 412                 if (fsl_edma->chan_masked & BIT(i))
 413                         continue;
 414
 415                 fsl_chan = &fsl_edma->chans[i];
 416
 417                 pd_chan = dev_pm_domain_attach_by_id(dev, i);
 418                 if (IS_ERR_OR_NULL(pd_chan)) {
 419                         dev_err(dev, "Failed attach pd %d\n", i);
 420                         return -EINVAL;
 421                 }
 422
 423                 link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
 424                                              DL_FLAG_PM_RUNTIME |
 425                                              DL_FLAG_RPM_ACTIVE);
 426                 if (!link) {
 427                         dev_err(dev, "Failed to add device_link to %d\n", i);
 428                         return -EINVAL;
 429                 }
 430
 431                 fsl_chan->pd_dev = pd_chan;
 432
 433                 pm_runtime_use_autosuspend(fsl_chan->pd_dev);
 434                 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200);
 435                 pm_runtime_set_active(fsl_chan->pd_dev);
 436         }
 437
 438         return 0;
 439 }
 440
 441 static int fsl_edma_probe(struct platform_device *pdev)
 442 {
 443         struct device_node *np = pdev->dev.of_node;
 444         struct fsl_edma_engine *fsl_edma;
 445         const struct fsl_edma_drvdata *drvdata = NULL;
 446         u32 chan_mask[2] = {0, 0};
 447         char clk_name[36];
 448         struct edma_regs *regs;
 449         int chans;
 450         int ret, i;
 451
 452         drvdata = device_get_match_data(&pdev->dev);
 453         if (!drvdata) {
 454                 dev_err(&pdev->dev, "unable to find driver data\n");
 455                 return -EINVAL;
 456         }
 457
 458         ret = of_property_read_u32(np, "dma-channels", &chans);
 459         if (ret) {
 460                 dev_err(&pdev->dev, "Can't get dma-channels.\n");
 461                 return ret;
 462         }
 463
 464         fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans),
 465                                 GFP_KERNEL);
 466         if (!fsl_edma)
 467                 return -ENOMEM;
 468
 469         fsl_edma->drvdata = drvdata;
 470         fsl_edma->n_chans = chans;
 471         mutex_init(&fsl_edma->fsl_edma_mutex);
 472
 473         fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0);
 474         if (IS_ERR(fsl_edma->membase))
 475                 return PTR_ERR(fsl_edma->membase);
 476
 477         if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) {
 478                 fsl_edma_setup_regs(fsl_edma);
 479                 regs = &fsl_edma->regs;
 480         }
 481
 482         if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
 483                 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
 484                 if (IS_ERR(fsl_edma->dmaclk)) {
 485                         dev_err(&pdev->dev, "Missing DMA block clock.\n");
 486                         return PTR_ERR(fsl_edma->dmaclk);
 487                 }
 488         }
 489
 490         ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2);
 491
 492         if (ret > 0) {
 493                 fsl_edma->chan_masked = chan_mask[1];
 494                 fsl_edma->chan_masked <<= 32;
 495                 fsl_edma->chan_masked |= chan_mask[0];
 496         }
 497
 498         for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
 499                 char clkname[32];
 500
 501                 /* eDMAv3 mux register move to TCD area if ch_mux exist */
 502                 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)
 503                         break;
 504
 505                 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev,
 506                                                                       1 + i);
 507                 if (IS_ERR(fsl_edma->muxbase[i])) {
 508                         /* on error: disable all previously enabled clks */
 509                         fsl_disable_clocks(fsl_edma, i);
 510                         return PTR_ERR(fsl_edma->muxbase[i]);
 511                 }
 512
 513                 sprintf(clkname, "dmamux%d", i);
 514                 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname);
 515                 if (IS_ERR(fsl_edma->muxclk[i])) {
 516                         dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
 517                         /* on error: disable all previously enabled clks */
 518                         return PTR_ERR(fsl_edma->muxclk[i]);
 519                 }
 520         }
 521
 522         fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
 523
 524         if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) {
 525                 ret = fsl_edma3_attach_pd(pdev, fsl_edma);
 526                 if (ret)
 527                         return ret;
 528         }
 529
 530         if (drvdata->flags & FSL_EDMA_DRV_TCD64)
 531                 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 532
 533         INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
 534         for (i = 0; i < fsl_edma->n_chans; i++) {
 535                 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
 536                 int len;
 537
 538                 if (fsl_edma->chan_masked & BIT(i))
 539                         continue;
 540
 541                 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d",
 542                                                            dev_name(&pdev->dev), i);
 543
 544                 fsl_chan->edma = fsl_edma;
 545                 fsl_chan->pm_state = RUNNING;
 546                 fsl_chan->srcid = 0;
 547                 fsl_chan->dma_dir = DMA_NONE;
 548                 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
 549
 550                 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ?
 551                                 offsetof(struct fsl_edma3_ch_reg, tcd) : 0;
 552                 fsl_chan->tcd = fsl_edma->membase
 553                                 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
 554                 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip;
 555
 556                 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
 557                         snprintf(clk_name, sizeof(clk_name), "ch%02d", i);
 558                         fsl_chan->clk = devm_clk_get_enabled(&pdev->dev,
 559                                                              (const char *)clk_name);
 560
 561                         if (IS_ERR(fsl_chan->clk))
 562                                 return PTR_ERR(fsl_chan->clk);
 563                 }
 564                 fsl_chan->pdev = pdev;
 565                 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
 566
 567                 edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr);
 568                 fsl_edma_chan_mux(fsl_chan, 0, false);
 569                 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK)
 570                         clk_disable_unprepare(fsl_chan->clk);
 571         }
 572
 573         ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
 574         if (ret)
 575                 return ret;
 576
 577         dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
 578         dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
 579         dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
 580         dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask);
 581
 582         fsl_edma->dma_dev.dev = &pdev->dev;
 583         fsl_edma->dma_dev.device_alloc_chan_resources
 584                 = fsl_edma_alloc_chan_resources;
 585         fsl_edma->dma_dev.device_free_chan_resources
 586                 = fsl_edma_free_chan_resources;
 587         fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
 588         fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
 589         fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
 590         fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy;
 591         fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
 592         fsl_edma->dma_dev.device_pause = fsl_edma_pause;
 593         fsl_edma->dma_dev.device_resume = fsl_edma_resume;
 594         fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
 595         fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
 596         fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
 597
 598         fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
 599         fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
 600
 601         if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) {
 602                 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
 603                 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
 604         }
 605
 606         fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 607         if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV)
 608                 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV);
 609
 610         fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ?
 611                                         DMAENGINE_ALIGN_64_BYTES :
 612                                         DMAENGINE_ALIGN_32_BYTES;
 613
 614         /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
 615         dma_set_max_seg_size(fsl_edma->dma_dev.dev,
 616                              FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK));
 617
 618         fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
 619
 620         platform_set_drvdata(pdev, fsl_edma);
 621
 622         ret = dma_async_device_register(&fsl_edma->dma_dev);
 623         if (ret) {
 624                 dev_err(&pdev->dev,
 625                         "Can't register Freescale eDMA engine. (%d)\n", ret);
 626                 return ret;
 627         }
 628
 629         ret = of_dma_controller_register(np,
 630                         drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate,
 631                         fsl_edma);
 632         if (ret) {
 633                 dev_err(&pdev->dev,
 634                         "Can't register Freescale eDMA of_dma. (%d)\n", ret);
 635                 dma_async_device_unregister(&fsl_edma->dma_dev);
 636                 return ret;
 637         }
 638
 639         /* enable round robin arbitration */
 640         if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
 641                 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
 642
 643         return 0;
 644 }
 645
 646 static void fsl_edma_remove(struct platform_device *pdev)
 647 {
 648         struct device_node *np = pdev->dev.of_node;
 649         struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
 650
 651         fsl_edma_irq_exit(pdev, fsl_edma);
 652         fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
 653         of_dma_controller_free(np);
 654         dma_async_device_unregister(&fsl_edma->dma_dev);
 655         fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
 656 }
 657
 658 static int fsl_edma_suspend_late(struct device *dev)
 659 {
 660         struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
 661         struct fsl_edma_chan *fsl_chan;
 662         unsigned long flags;
 663         int i;
 664
 665         for (i = 0; i < fsl_edma->n_chans; i++) {
 666                 fsl_chan = &fsl_edma->chans[i];
 667                 if (fsl_edma->chan_masked & BIT(i))
 668                         continue;
 669                 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 670                 /* Make sure chan is idle or will force disable. */
 671                 if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) {
 672                         dev_warn(dev, "WARN: There is non-idle channel.");
 673                         fsl_edma_disable_request(fsl_chan);
 674                         fsl_edma_chan_mux(fsl_chan, 0, false);
 675                 }
 676
 677                 fsl_chan->pm_state = SUSPENDED;
 678                 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 679         }
 680
 681         return 0;
 682 }
 683
 684 static int fsl_edma_resume_early(struct device *dev)
 685 {
 686         struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
 687         struct fsl_edma_chan *fsl_chan;
 688         struct edma_regs *regs = &fsl_edma->regs;
 689         int i;
 690
 691         for (i = 0; i < fsl_edma->n_chans; i++) {
 692                 fsl_chan = &fsl_edma->chans[i];
 693                 if (fsl_edma->chan_masked & BIT(i))
 694                         continue;
 695                 fsl_chan->pm_state = RUNNING;
 696                 edma_write_tcdreg(fsl_chan, 0, csr);
 697                 if (fsl_chan->srcid != 0)
 698                         fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, true);
 699         }
 700
 701         if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
 702                 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
 703
 704         return 0;
 705 }
 706
 707 /*
 708  * eDMA provides the service to others, so it should be suspend late
 709  * and resume early. When eDMA suspend, all of the clients should stop
 710  * the DMA data transmission and let the channel idle.
 711  */
 712 static const struct dev_pm_ops fsl_edma_pm_ops = {
 713         .suspend_late   = fsl_edma_suspend_late,
 714         .resume_early   = fsl_edma_resume_early,
 715 };
 716
 717 static struct platform_driver fsl_edma_driver = {
 718         .driver         = {
 719                 .name   = "fsl-edma",
 720                 .of_match_table = fsl_edma_dt_ids,
 721                 .pm     = &fsl_edma_pm_ops,
 722         },
 723         .probe          = fsl_edma_probe,
 724         .remove_new     = fsl_edma_remove,
 725 };
 726
 727 static int __init fsl_edma_init(void)
 728 {
 729         return platform_driver_register(&fsl_edma_driver);
 730 }
 731 subsys_initcall(fsl_edma_init);
 732
 733 static void __exit fsl_edma_exit(void)
 734 {
 735         platform_driver_unregister(&fsl_edma_driver);
 736 }
 737 module_exit(fsl_edma_exit);
 738
 739 MODULE_ALIAS("platform:fsl-edma");
 740 MODULE_DESCRIPTION("Freescale eDMA engine driver");
 741 MODULE_LICENSE("GPL v2");