drivers/dma/fsl-edma-common.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
   4 // Copyright (c) 2017 Sysam, Angelo Dureghello  <angelo@sysam.it>
   5
   6 #include <linux/dmapool.h>
   7 #include <linux/module.h>
   8 #include <linux/slab.h>
   9
  10 #include "fsl-edma-common.h"
  11
  12 #define EDMA_CR                 0x00
  13 #define EDMA_ES                 0x04
  14 #define EDMA_ERQ                0x0C
  15 #define EDMA_EEI                0x14
  16 #define EDMA_SERQ               0x1B
  17 #define EDMA_CERQ               0x1A
  18 #define EDMA_SEEI               0x19
  19 #define EDMA_CEEI               0x18
  20 #define EDMA_CINT               0x1F
  21 #define EDMA_CERR               0x1E
  22 #define EDMA_SSRT               0x1D
  23 #define EDMA_CDNE               0x1C
  24 #define EDMA_INTR               0x24
  25 #define EDMA_ERR                0x2C
  26
  27 #define EDMA64_ERQH             0x08
  28 #define EDMA64_EEIH             0x10
  29 #define EDMA64_SERQ             0x18
  30 #define EDMA64_CERQ             0x19
  31 #define EDMA64_SEEI             0x1a
  32 #define EDMA64_CEEI             0x1b
  33 #define EDMA64_CINT             0x1c
  34 #define EDMA64_CERR             0x1d
  35 #define EDMA64_SSRT             0x1e
  36 #define EDMA64_CDNE             0x1f
  37 #define EDMA64_INTH             0x20
  38 #define EDMA64_INTL             0x24
  39 #define EDMA64_ERRH             0x28
  40 #define EDMA64_ERRL             0x2c
  41
  42 #define EDMA_TCD                0x1000
  43
  44 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
  45 {
  46         struct edma_regs *regs = &fsl_chan->edma->regs;
  47         u32 ch = fsl_chan->vchan.chan.chan_id;
  48
  49         if (fsl_chan->edma->version == v1) {
  50                 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
  51                 edma_writeb(fsl_chan->edma, ch, regs->serq);
  52         } else {
  53                 /* ColdFire is big endian, and accesses natively
  54                  * big endian I/O peripherals
  55                  */
  56                 iowrite8(EDMA_SEEI_SEEI(ch), regs->seei);
  57                 iowrite8(ch, regs->serq);
  58         }
  59 }
  60
  61 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
  62 {
  63         struct edma_regs *regs = &fsl_chan->edma->regs;
  64         u32 ch = fsl_chan->vchan.chan.chan_id;
  65
  66         if (fsl_chan->edma->version == v1) {
  67                 edma_writeb(fsl_chan->edma, ch, regs->cerq);
  68                 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
  69         } else {
  70                 /* ColdFire is big endian, and accesses natively
  71                  * big endian I/O peripherals
  72                  */
  73                 iowrite8(ch, regs->cerq);
  74                 iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei);
  75         }
  76 }
  77 EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
  78
  79 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
  80                         unsigned int slot, bool enable)
  81 {
  82         u32 ch = fsl_chan->vchan.chan.chan_id;
  83         void __iomem *muxaddr;
  84         unsigned int chans_per_mux, ch_off;
  85
  86         chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
  87         ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
  88         muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
  89         slot = EDMAMUX_CHCFG_SOURCE(slot);
  90
  91         if (enable)
  92                 iowrite8(EDMAMUX_CHCFG_ENBL | slot, muxaddr + ch_off);
  93         else
  94                 iowrite8(EDMAMUX_CHCFG_DIS, muxaddr + ch_off);
  95 }
  96 EXPORT_SYMBOL_GPL(fsl_edma_chan_mux);
  97
  98 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
  99 {
 100         switch (addr_width) {
 101         case 1:
 102                 return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT;
 103         case 2:
 104                 return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT;
 105         case 4:
 106                 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
 107         case 8:
 108                 return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT;
 109         default:
 110                 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
 111         }
 112 }
 113
 114 void fsl_edma_free_desc(struct virt_dma_desc *vdesc)
 115 {
 116         struct fsl_edma_desc *fsl_desc;
 117         int i;
 118
 119         fsl_desc = to_fsl_edma_desc(vdesc);
 120         for (i = 0; i < fsl_desc->n_tcds; i++)
 121                 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd,
 122                               fsl_desc->tcd[i].ptcd);
 123         kfree(fsl_desc);
 124 }
 125 EXPORT_SYMBOL_GPL(fsl_edma_free_desc);
 126
 127 int fsl_edma_terminate_all(struct dma_chan *chan)
 128 {
 129         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 130         unsigned long flags;
 131         LIST_HEAD(head);
 132
 133         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 134         fsl_edma_disable_request(fsl_chan);
 135         fsl_chan->edesc = NULL;
 136         fsl_chan->idle = true;
 137         vchan_get_all_descriptors(&fsl_chan->vchan, &head);
 138         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 139         vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
 140         return 0;
 141 }
 142 EXPORT_SYMBOL_GPL(fsl_edma_terminate_all);
 143
 144 int fsl_edma_pause(struct dma_chan *chan)
 145 {
 146         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 147         unsigned long flags;
 148
 149         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 150         if (fsl_chan->edesc) {
 151                 fsl_edma_disable_request(fsl_chan);
 152                 fsl_chan->status = DMA_PAUSED;
 153                 fsl_chan->idle = true;
 154         }
 155         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 156         return 0;
 157 }
 158 EXPORT_SYMBOL_GPL(fsl_edma_pause);
 159
 160 int fsl_edma_resume(struct dma_chan *chan)
 161 {
 162         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 163         unsigned long flags;
 164
 165         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 166         if (fsl_chan->edesc) {
 167                 fsl_edma_enable_request(fsl_chan);
 168                 fsl_chan->status = DMA_IN_PROGRESS;
 169                 fsl_chan->idle = false;
 170         }
 171         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 172         return 0;
 173 }
 174 EXPORT_SYMBOL_GPL(fsl_edma_resume);
 175
 176 int fsl_edma_slave_config(struct dma_chan *chan,
 177                                  struct dma_slave_config *cfg)
 178 {
 179         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 180
 181         memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg));
 182
 183         return 0;
 184 }
 185 EXPORT_SYMBOL_GPL(fsl_edma_slave_config);
 186
 187 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
 188                 struct virt_dma_desc *vdesc, bool in_progress)
 189 {
 190         struct fsl_edma_desc *edesc = fsl_chan->edesc;
 191         struct edma_regs *regs = &fsl_chan->edma->regs;
 192         u32 ch = fsl_chan->vchan.chan.chan_id;
 193         enum dma_transfer_direction dir = edesc->dirn;
 194         dma_addr_t cur_addr, dma_addr;
 195         size_t len, size;
 196         int i;
 197
 198         /* calculate the total size in this desc */
 199         for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++)
 200                 len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
 201                         * le16_to_cpu(edesc->tcd[i].vtcd->biter);
 202
 203         if (!in_progress)
 204                 return len;
 205
 206         if (dir == DMA_MEM_TO_DEV)
 207                 cur_addr = edma_readl(fsl_chan->edma, &regs->tcd[ch].saddr);
 208         else
 209                 cur_addr = edma_readl(fsl_chan->edma, &regs->tcd[ch].daddr);
 210
 211         /* figure out the finished and calculate the residue */
 212         for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
 213                 size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
 214                         * le16_to_cpu(edesc->tcd[i].vtcd->biter);
 215                 if (dir == DMA_MEM_TO_DEV)
 216                         dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr);
 217                 else
 218                         dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr);
 219
 220                 len -= size;
 221                 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) {
 222                         len += dma_addr + size - cur_addr;
 223                         break;
 224                 }
 225         }
 226
 227         return len;
 228 }
 229
 230 enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
 231                 dma_cookie_t cookie, struct dma_tx_state *txstate)
 232 {
 233         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 234         struct virt_dma_desc *vdesc;
 235         enum dma_status status;
 236         unsigned long flags;
 237
 238         status = dma_cookie_status(chan, cookie, txstate);
 239         if (status == DMA_COMPLETE)
 240                 return status;
 241
 242         if (!txstate)
 243                 return fsl_chan->status;
 244
 245         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 246         vdesc = vchan_find_desc(&fsl_chan->vchan, cookie);
 247         if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie)
 248                 txstate->residue =
 249                         fsl_edma_desc_residue(fsl_chan, vdesc, true);
 250         else if (vdesc)
 251                 txstate->residue =
 252                         fsl_edma_desc_residue(fsl_chan, vdesc, false);
 253         else
 254                 txstate->residue = 0;
 255
 256         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 257
 258         return fsl_chan->status;
 259 }
 260 EXPORT_SYMBOL_GPL(fsl_edma_tx_status);
 261
 262 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
 263                                   struct fsl_edma_hw_tcd *tcd)
 264 {
 265         struct fsl_edma_engine *edma = fsl_chan->edma;
 266         struct edma_regs *regs = &fsl_chan->edma->regs;
 267         u32 ch = fsl_chan->vchan.chan.chan_id;
 268
 269         /*
 270          * TCD parameters are stored in struct fsl_edma_hw_tcd in little
 271          * endian format. However, we need to load the TCD registers in
 272          * big- or little-endian obeying the eDMA engine model endian.
 273          */
 274         edma_writew(edma, 0,  &regs->tcd[ch].csr);
 275         edma_writel(edma, le32_to_cpu(tcd->saddr), &regs->tcd[ch].saddr);
 276         edma_writel(edma, le32_to_cpu(tcd->daddr), &regs->tcd[ch].daddr);
 277
 278         edma_writew(edma, le16_to_cpu(tcd->attr), &regs->tcd[ch].attr);
 279         edma_writew(edma, le16_to_cpu(tcd->soff), &regs->tcd[ch].soff);
 280
 281         edma_writel(edma, le32_to_cpu(tcd->nbytes), &regs->tcd[ch].nbytes);
 282         edma_writel(edma, le32_to_cpu(tcd->slast), &regs->tcd[ch].slast);
 283
 284         edma_writew(edma, le16_to_cpu(tcd->citer), &regs->tcd[ch].citer);
 285         edma_writew(edma, le16_to_cpu(tcd->biter), &regs->tcd[ch].biter);
 286         edma_writew(edma, le16_to_cpu(tcd->doff), &regs->tcd[ch].doff);
 287
 288         edma_writel(edma, le32_to_cpu(tcd->dlast_sga),
 289                         &regs->tcd[ch].dlast_sga);
 290
 291         edma_writew(edma, le16_to_cpu(tcd->csr), &regs->tcd[ch].csr);
 292 }
 293
 294 static inline
 295 void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
 296                        u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer,
 297                        u16 biter, u16 doff, u32 dlast_sga, bool major_int,
 298                        bool disable_req, bool enable_sg)
 299 {
 300         u16 csr = 0;
 301
 302         /*
 303          * eDMA hardware SGs require the TCDs to be stored in little
 304          * endian format irrespective of the register endian model.
 305          * So we put the value in little endian in memory, waiting
 306          * for fsl_edma_set_tcd_regs doing the swap.
 307          */
 308         tcd->saddr = cpu_to_le32(src);
 309         tcd->daddr = cpu_to_le32(dst);
 310
 311         tcd->attr = cpu_to_le16(attr);
 312
 313         tcd->soff = cpu_to_le16(soff);
 314
 315         tcd->nbytes = cpu_to_le32(nbytes);
 316         tcd->slast = cpu_to_le32(slast);
 317
 318         tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer));
 319         tcd->doff = cpu_to_le16(doff);
 320
 321         tcd->dlast_sga = cpu_to_le32(dlast_sga);
 322
 323         tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter));
 324         if (major_int)
 325                 csr |= EDMA_TCD_CSR_INT_MAJOR;
 326
 327         if (disable_req)
 328                 csr |= EDMA_TCD_CSR_D_REQ;
 329
 330         if (enable_sg)
 331                 csr |= EDMA_TCD_CSR_E_SG;
 332
 333         tcd->csr = cpu_to_le16(csr);
 334 }
 335
 336 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan,
 337                 int sg_len)
 338 {
 339         struct fsl_edma_desc *fsl_desc;
 340         int i;
 341
 342         fsl_desc = kzalloc(struct_size(fsl_desc, tcd, sg_len), GFP_NOWAIT);
 343         if (!fsl_desc)
 344                 return NULL;
 345
 346         fsl_desc->echan = fsl_chan;
 347         fsl_desc->n_tcds = sg_len;
 348         for (i = 0; i < sg_len; i++) {
 349                 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool,
 350                                         GFP_NOWAIT, &fsl_desc->tcd[i].ptcd);
 351                 if (!fsl_desc->tcd[i].vtcd)
 352                         goto err;
 353         }
 354         return fsl_desc;
 355
 356 err:
 357         while (--i >= 0)
 358                 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd,
 359                                 fsl_desc->tcd[i].ptcd);
 360         kfree(fsl_desc);
 361         return NULL;
 362 }
 363
 364 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
 365                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
 366                 size_t period_len, enum dma_transfer_direction direction,
 367                 unsigned long flags)
 368 {
 369         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 370         struct fsl_edma_desc *fsl_desc;
 371         dma_addr_t dma_buf_next;
 372         int sg_len, i;
 373         u32 src_addr, dst_addr, last_sg, nbytes;
 374         u16 soff, doff, iter;
 375
 376         if (!is_slave_direction(direction))
 377                 return NULL;
 378
 379         sg_len = buf_len / period_len;
 380         fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
 381         if (!fsl_desc)
 382                 return NULL;
 383         fsl_desc->iscyclic = true;
 384         fsl_desc->dirn = direction;
 385
 386         dma_buf_next = dma_addr;
 387         if (direction == DMA_MEM_TO_DEV) {
 388                 fsl_chan->attr =
 389                         fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
 390                 nbytes = fsl_chan->cfg.dst_addr_width *
 391                         fsl_chan->cfg.dst_maxburst;
 392         } else {
 393                 fsl_chan->attr =
 394                         fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
 395                 nbytes = fsl_chan->cfg.src_addr_width *
 396                         fsl_chan->cfg.src_maxburst;
 397         }
 398
 399         iter = period_len / nbytes;
 400
 401         for (i = 0; i < sg_len; i++) {
 402                 if (dma_buf_next >= dma_addr + buf_len)
 403                         dma_buf_next = dma_addr;
 404
 405                 /* get next sg's physical address */
 406                 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
 407
 408                 if (direction == DMA_MEM_TO_DEV) {
 409                         src_addr = dma_buf_next;
 410                         dst_addr = fsl_chan->cfg.dst_addr;
 411                         soff = fsl_chan->cfg.dst_addr_width;
 412                         doff = 0;
 413                 } else {
 414                         src_addr = fsl_chan->cfg.src_addr;
 415                         dst_addr = dma_buf_next;
 416                         soff = 0;
 417                         doff = fsl_chan->cfg.src_addr_width;
 418                 }
 419
 420                 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
 421                                   fsl_chan->attr, soff, nbytes, 0, iter,
 422                                   iter, doff, last_sg, true, false, true);
 423                 dma_buf_next += period_len;
 424         }
 425
 426         return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
 427 }
 428 EXPORT_SYMBOL_GPL(fsl_edma_prep_dma_cyclic);
 429
 430 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
 431                 struct dma_chan *chan, struct scatterlist *sgl,
 432                 unsigned int sg_len, enum dma_transfer_direction direction,
 433                 unsigned long flags, void *context)
 434 {
 435         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 436         struct fsl_edma_desc *fsl_desc;
 437         struct scatterlist *sg;
 438         u32 src_addr, dst_addr, last_sg, nbytes;
 439         u16 soff, doff, iter;
 440         int i;
 441
 442         if (!is_slave_direction(direction))
 443                 return NULL;
 444
 445         fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
 446         if (!fsl_desc)
 447                 return NULL;
 448         fsl_desc->iscyclic = false;
 449         fsl_desc->dirn = direction;
 450
 451         if (direction == DMA_MEM_TO_DEV) {
 452                 fsl_chan->attr =
 453                         fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
 454                 nbytes = fsl_chan->cfg.dst_addr_width *
 455                         fsl_chan->cfg.dst_maxburst;
 456         } else {
 457                 fsl_chan->attr =
 458                         fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
 459                 nbytes = fsl_chan->cfg.src_addr_width *
 460                         fsl_chan->cfg.src_maxburst;
 461         }
 462
 463         for_each_sg(sgl, sg, sg_len, i) {
 464                 /* get next sg's physical address */
 465                 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
 466
 467                 if (direction == DMA_MEM_TO_DEV) {
 468                         src_addr = sg_dma_address(sg);
 469                         dst_addr = fsl_chan->cfg.dst_addr;
 470                         soff = fsl_chan->cfg.dst_addr_width;
 471                         doff = 0;
 472                 } else {
 473                         src_addr = fsl_chan->cfg.src_addr;
 474                         dst_addr = sg_dma_address(sg);
 475                         soff = 0;
 476                         doff = fsl_chan->cfg.src_addr_width;
 477                 }
 478
 479                 iter = sg_dma_len(sg) / nbytes;
 480                 if (i < sg_len - 1) {
 481                         last_sg = fsl_desc->tcd[(i + 1)].ptcd;
 482                         fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
 483                                           dst_addr, fsl_chan->attr, soff,
 484                                           nbytes, 0, iter, iter, doff, last_sg,
 485                                           false, false, true);
 486                 } else {
 487                         last_sg = 0;
 488                         fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
 489                                           dst_addr, fsl_chan->attr, soff,
 490                                           nbytes, 0, iter, iter, doff, last_sg,
 491                                           true, true, false);
 492                 }
 493         }
 494
 495         return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
 496 }
 497 EXPORT_SYMBOL_GPL(fsl_edma_prep_slave_sg);
 498
 499 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
 500 {
 501         struct virt_dma_desc *vdesc;
 502
 503         vdesc = vchan_next_desc(&fsl_chan->vchan);
 504         if (!vdesc)
 505                 return;
 506         fsl_chan->edesc = to_fsl_edma_desc(vdesc);
 507         fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd);
 508         fsl_edma_enable_request(fsl_chan);
 509         fsl_chan->status = DMA_IN_PROGRESS;
 510         fsl_chan->idle = false;
 511 }
 512 EXPORT_SYMBOL_GPL(fsl_edma_xfer_desc);
 513
 514 void fsl_edma_issue_pending(struct dma_chan *chan)
 515 {
 516         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 517         unsigned long flags;
 518
 519         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 520
 521         if (unlikely(fsl_chan->pm_state != RUNNING)) {
 522                 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 523                 /* cannot submit due to suspend */
 524                 return;
 525         }
 526
 527         if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc)
 528                 fsl_edma_xfer_desc(fsl_chan);
 529
 530         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 531 }
 532 EXPORT_SYMBOL_GPL(fsl_edma_issue_pending);
 533
 534 int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
 535 {
 536         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 537
 538         fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
 539                                 sizeof(struct fsl_edma_hw_tcd),
 540                                 32, 0);
 541         return 0;
 542 }
 543 EXPORT_SYMBOL_GPL(fsl_edma_alloc_chan_resources);
 544
 545 void fsl_edma_free_chan_resources(struct dma_chan *chan)
 546 {
 547         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 548         unsigned long flags;
 549         LIST_HEAD(head);
 550
 551         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 552         fsl_edma_disable_request(fsl_chan);
 553         fsl_edma_chan_mux(fsl_chan, 0, false);
 554         fsl_chan->edesc = NULL;
 555         vchan_get_all_descriptors(&fsl_chan->vchan, &head);
 556         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 557
 558         vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
 559         dma_pool_destroy(fsl_chan->tcd_pool);
 560         fsl_chan->tcd_pool = NULL;
 561 }
 562 EXPORT_SYMBOL_GPL(fsl_edma_free_chan_resources);
 563
 564 void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
 565 {
 566         struct fsl_edma_chan *chan, *_chan;
 567
 568         list_for_each_entry_safe(chan, _chan,
 569                                 &dmadev->channels, vchan.chan.device_node) {
 570                 list_del(&chan->vchan.chan.device_node);
 571                 tasklet_kill(&chan->vchan.task);
 572         }
 573 }
 574 EXPORT_SYMBOL_GPL(fsl_edma_cleanup_vchan);
 575
 576 /*
 577  * On the 32 channels Vybrid/mpc577x edma version (here called "v1"),
 578  * register offsets are different compared to ColdFire mcf5441x 64 channels
 579  * edma (here called "v2").
 580  *
 581  * This function sets up register offsets as per proper declared version
 582  * so must be called in xxx_edma_probe() just after setting the
 583  * edma "version" and "membase" appropriately.
 584  */
 585 void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
 586 {
 587         edma->regs.cr = edma->membase + EDMA_CR;
 588         edma->regs.es = edma->membase + EDMA_ES;
 589         edma->regs.erql = edma->membase + EDMA_ERQ;
 590         edma->regs.eeil = edma->membase + EDMA_EEI;
 591
 592         edma->regs.serq = edma->membase + ((edma->version == v1) ?
 593                         EDMA_SERQ : EDMA64_SERQ);
 594         edma->regs.cerq = edma->membase + ((edma->version == v1) ?
 595                         EDMA_CERQ : EDMA64_CERQ);
 596         edma->regs.seei = edma->membase + ((edma->version == v1) ?
 597                         EDMA_SEEI : EDMA64_SEEI);
 598         edma->regs.ceei = edma->membase + ((edma->version == v1) ?
 599                         EDMA_CEEI : EDMA64_CEEI);
 600         edma->regs.cint = edma->membase + ((edma->version == v1) ?
 601                         EDMA_CINT : EDMA64_CINT);
 602         edma->regs.cerr = edma->membase + ((edma->version == v1) ?
 603                         EDMA_CERR : EDMA64_CERR);
 604         edma->regs.ssrt = edma->membase + ((edma->version == v1) ?
 605                         EDMA_SSRT : EDMA64_SSRT);
 606         edma->regs.cdne = edma->membase + ((edma->version == v1) ?
 607                         EDMA_CDNE : EDMA64_CDNE);
 608         edma->regs.intl = edma->membase + ((edma->version == v1) ?
 609                         EDMA_INTR : EDMA64_INTL);
 610         edma->regs.errl = edma->membase + ((edma->version == v1) ?
 611                         EDMA_ERR : EDMA64_ERRL);
 612
 613         if (edma->version == v2) {
 614                 edma->regs.erqh = edma->membase + EDMA64_ERQH;
 615                 edma->regs.eeih = edma->membase + EDMA64_EEIH;
 616                 edma->regs.errh = edma->membase + EDMA64_ERRH;
 617                 edma->regs.inth = edma->membase + EDMA64_INTH;
 618         }
 619
 620         edma->regs.tcd = edma->membase + EDMA_TCD;
 621 }
 622 EXPORT_SYMBOL_GPL(fsl_edma_setup_regs);
 623
 624 MODULE_LICENSE("GPL v2");