2 * Core driver for the Synopsys DesignWare DMA Controller
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
27 #include "dw_dmac_regs.h"
28 #include "dmaengine.h"
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
36 * The driver has currently been tested only with the Atmel AT32AP7000,
37 * which does not support descriptor writeback.
40 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
42 return slave ? slave->dst_master : 0;
45 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
47 return slave ? slave->src_master : 1;
53 static inline unsigned int dwc_get_master(struct dma_chan *chan, int master)
55 struct dw_dma *dw = to_dw_dma(chan->device);
56 struct dw_dma_slave *dws = chan->private;
59 if (master == SRC_MASTER)
64 return min_t(unsigned int, dw->nr_masters - 1, m);
67 #define DWC_DEFAULT_CTLLO(_chan) ({ \
68 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
69 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
70 bool _is_slave = is_slave_direction(_dwc->direction); \
71 int _dms = dwc_get_master(_chan, DST_MASTER); \
72 int _sms = dwc_get_master(_chan, SRC_MASTER); \
73 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
75 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
78 (DWC_CTLL_DST_MSIZE(_dmsize) \
79 | DWC_CTLL_SRC_MSIZE(_smsize) \
82 | DWC_CTLL_DMS(_dms) \
83 | DWC_CTLL_SMS(_sms)); \
87 * Number of descriptors to allocate for each channel. This should be
88 * made configurable somehow; preferably, the clients (at least the
89 * ones using slave transfers) should be able to give us a hint.
91 #define NR_DESCS_PER_CHANNEL 64
93 static inline unsigned int dwc_get_data_width(struct dma_chan *chan, int master)
95 struct dw_dma *dw = to_dw_dma(chan->device);
97 return dw->data_width[dwc_get_master(chan, master)];
100 /*----------------------------------------------------------------------*/
102 static struct device *chan2dev(struct dma_chan *chan)
104 return &chan->dev->device;
106 static struct device *chan2parent(struct dma_chan *chan)
108 return chan->dev->device.parent;
111 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
113 return to_dw_desc(dwc->active_list.next);
116 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
118 struct dw_desc *desc, *_desc;
119 struct dw_desc *ret = NULL;
123 spin_lock_irqsave(&dwc->lock, flags);
124 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
126 if (async_tx_test_ack(&desc->txd)) {
127 list_del(&desc->desc_node);
131 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
133 spin_unlock_irqrestore(&dwc->lock, flags);
135 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
141 * Move a descriptor, including any children, to the free list.
142 * `desc' must not be on any lists.
144 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
149 struct dw_desc *child;
151 spin_lock_irqsave(&dwc->lock, flags);
152 list_for_each_entry(child, &desc->tx_list, desc_node)
153 dev_vdbg(chan2dev(&dwc->chan),
154 "moving child desc %p to freelist\n",
156 list_splice_init(&desc->tx_list, &dwc->free_list);
157 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
158 list_add(&desc->desc_node, &dwc->free_list);
159 spin_unlock_irqrestore(&dwc->lock, flags);
163 static void dwc_initialize(struct dw_dma_chan *dwc)
165 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
166 struct dw_dma_slave *dws = dwc->chan.private;
167 u32 cfghi = DWC_CFGH_FIFO_MODE;
168 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
170 if (dwc->initialized == true)
175 * We need controller-specific data to set up slave
178 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
181 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
183 if (dwc->direction == DMA_MEM_TO_DEV)
184 cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
185 else if (dwc->direction == DMA_DEV_TO_MEM)
186 cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
189 channel_writel(dwc, CFG_LO, cfglo);
190 channel_writel(dwc, CFG_HI, cfghi);
192 /* Enable interrupts */
193 channel_set_bit(dw, MASK.XFER, dwc->mask);
194 channel_set_bit(dw, MASK.ERROR, dwc->mask);
196 dwc->initialized = true;
199 /*----------------------------------------------------------------------*/
201 static inline unsigned int dwc_fast_fls(unsigned long long v)
204 * We can be a lot more clever here, but this should take care
205 * of the most common optimization.
216 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
218 dev_err(chan2dev(&dwc->chan),
219 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
220 channel_readl(dwc, SAR),
221 channel_readl(dwc, DAR),
222 channel_readl(dwc, LLP),
223 channel_readl(dwc, CTL_HI),
224 channel_readl(dwc, CTL_LO));
227 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
229 channel_clear_bit(dw, CH_EN, dwc->mask);
230 while (dma_readl(dw, CH_EN) & dwc->mask)
234 /*----------------------------------------------------------------------*/
236 /* Perform single block transfer */
237 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
238 struct dw_desc *desc)
240 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
243 /* Software emulation of LLP mode relies on interrupts to continue
244 * multi block transfer. */
245 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
247 channel_writel(dwc, SAR, desc->lli.sar);
248 channel_writel(dwc, DAR, desc->lli.dar);
249 channel_writel(dwc, CTL_LO, ctllo);
250 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
251 channel_set_bit(dw, CH_EN, dwc->mask);
253 /* Move pointer to next descriptor */
254 dwc->tx_node_active = dwc->tx_node_active->next;
257 /* Called with dwc->lock held and bh disabled */
258 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
260 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
261 unsigned long was_soft_llp;
263 /* ASSERT: channel is idle */
264 if (dma_readl(dw, CH_EN) & dwc->mask) {
265 dev_err(chan2dev(&dwc->chan),
266 "BUG: Attempted to start non-idle channel\n");
267 dwc_dump_chan_regs(dwc);
269 /* The tasklet will hopefully advance the queue... */
274 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
277 dev_err(chan2dev(&dwc->chan),
278 "BUG: Attempted to start new LLP transfer "
279 "inside ongoing one\n");
285 dwc->residue = first->total_len;
286 dwc->tx_node_active = &first->tx_list;
288 /* Submit first block */
289 dwc_do_single_block(dwc, first);
296 channel_writel(dwc, LLP, first->txd.phys);
297 channel_writel(dwc, CTL_LO,
298 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
299 channel_writel(dwc, CTL_HI, 0);
300 channel_set_bit(dw, CH_EN, dwc->mask);
303 /*----------------------------------------------------------------------*/
306 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
307 bool callback_required)
309 dma_async_tx_callback callback = NULL;
311 struct dma_async_tx_descriptor *txd = &desc->txd;
312 struct dw_desc *child;
315 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
317 spin_lock_irqsave(&dwc->lock, flags);
318 dma_cookie_complete(txd);
319 if (callback_required) {
320 callback = txd->callback;
321 param = txd->callback_param;
325 list_for_each_entry(child, &desc->tx_list, desc_node)
326 async_tx_ack(&child->txd);
327 async_tx_ack(&desc->txd);
329 list_splice_init(&desc->tx_list, &dwc->free_list);
330 list_move(&desc->desc_node, &dwc->free_list);
332 if (!is_slave_direction(dwc->direction)) {
333 struct device *parent = chan2parent(&dwc->chan);
334 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
335 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
336 dma_unmap_single(parent, desc->lli.dar,
337 desc->total_len, DMA_FROM_DEVICE);
339 dma_unmap_page(parent, desc->lli.dar,
340 desc->total_len, DMA_FROM_DEVICE);
342 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
343 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
344 dma_unmap_single(parent, desc->lli.sar,
345 desc->total_len, DMA_TO_DEVICE);
347 dma_unmap_page(parent, desc->lli.sar,
348 desc->total_len, DMA_TO_DEVICE);
352 spin_unlock_irqrestore(&dwc->lock, flags);
358 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
360 struct dw_desc *desc, *_desc;
364 spin_lock_irqsave(&dwc->lock, flags);
365 if (dma_readl(dw, CH_EN) & dwc->mask) {
366 dev_err(chan2dev(&dwc->chan),
367 "BUG: XFER bit set, but channel not idle!\n");
369 /* Try to continue after resetting the channel... */
370 dwc_chan_disable(dw, dwc);
374 * Submit queued descriptors ASAP, i.e. before we go through
375 * the completed ones.
377 list_splice_init(&dwc->active_list, &list);
378 if (!list_empty(&dwc->queue)) {
379 list_move(dwc->queue.next, &dwc->active_list);
380 dwc_dostart(dwc, dwc_first_active(dwc));
383 spin_unlock_irqrestore(&dwc->lock, flags);
385 list_for_each_entry_safe(desc, _desc, &list, desc_node)
386 dwc_descriptor_complete(dwc, desc, true);
389 /* Returns how many bytes were already received from source */
390 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
392 u32 ctlhi = channel_readl(dwc, CTL_HI);
393 u32 ctllo = channel_readl(dwc, CTL_LO);
395 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
398 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
401 struct dw_desc *desc, *_desc;
402 struct dw_desc *child;
406 spin_lock_irqsave(&dwc->lock, flags);
407 llp = channel_readl(dwc, LLP);
408 status_xfer = dma_readl(dw, RAW.XFER);
410 if (status_xfer & dwc->mask) {
411 /* Everything we've submitted is done */
412 dma_writel(dw, CLEAR.XFER, dwc->mask);
414 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
415 struct list_head *head, *active = dwc->tx_node_active;
418 * We are inside first active descriptor.
419 * Otherwise something is really wrong.
421 desc = dwc_first_active(dwc);
423 head = &desc->tx_list;
424 if (active != head) {
425 /* Update desc to reflect last sent one */
426 if (active != head->next)
427 desc = to_dw_desc(active->prev);
429 dwc->residue -= desc->len;
431 child = to_dw_desc(active);
433 /* Submit next block */
434 dwc_do_single_block(dwc, child);
436 spin_unlock_irqrestore(&dwc->lock, flags);
440 /* We are done here */
441 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
446 spin_unlock_irqrestore(&dwc->lock, flags);
448 dwc_complete_all(dw, dwc);
452 if (list_empty(&dwc->active_list)) {
454 spin_unlock_irqrestore(&dwc->lock, flags);
458 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
459 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
460 spin_unlock_irqrestore(&dwc->lock, flags);
464 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
465 (unsigned long long)llp);
467 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
468 /* initial residue value */
469 dwc->residue = desc->total_len;
471 /* check first descriptors addr */
472 if (desc->txd.phys == llp) {
473 spin_unlock_irqrestore(&dwc->lock, flags);
477 /* check first descriptors llp */
478 if (desc->lli.llp == llp) {
479 /* This one is currently in progress */
480 dwc->residue -= dwc_get_sent(dwc);
481 spin_unlock_irqrestore(&dwc->lock, flags);
485 dwc->residue -= desc->len;
486 list_for_each_entry(child, &desc->tx_list, desc_node) {
487 if (child->lli.llp == llp) {
488 /* Currently in progress */
489 dwc->residue -= dwc_get_sent(dwc);
490 spin_unlock_irqrestore(&dwc->lock, flags);
493 dwc->residue -= child->len;
497 * No descriptors so far seem to be in progress, i.e.
498 * this one must be done.
500 spin_unlock_irqrestore(&dwc->lock, flags);
501 dwc_descriptor_complete(dwc, desc, true);
502 spin_lock_irqsave(&dwc->lock, flags);
505 dev_err(chan2dev(&dwc->chan),
506 "BUG: All descriptors done, but channel not idle!\n");
508 /* Try to continue after resetting the channel... */
509 dwc_chan_disable(dw, dwc);
511 if (!list_empty(&dwc->queue)) {
512 list_move(dwc->queue.next, &dwc->active_list);
513 dwc_dostart(dwc, dwc_first_active(dwc));
515 spin_unlock_irqrestore(&dwc->lock, flags);
518 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
520 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
521 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
524 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
526 struct dw_desc *bad_desc;
527 struct dw_desc *child;
530 dwc_scan_descriptors(dw, dwc);
532 spin_lock_irqsave(&dwc->lock, flags);
535 * The descriptor currently at the head of the active list is
536 * borked. Since we don't have any way to report errors, we'll
537 * just have to scream loudly and try to carry on.
539 bad_desc = dwc_first_active(dwc);
540 list_del_init(&bad_desc->desc_node);
541 list_move(dwc->queue.next, dwc->active_list.prev);
543 /* Clear the error flag and try to restart the controller */
544 dma_writel(dw, CLEAR.ERROR, dwc->mask);
545 if (!list_empty(&dwc->active_list))
546 dwc_dostart(dwc, dwc_first_active(dwc));
549 * WARN may seem harsh, but since this only happens
550 * when someone submits a bad physical address in a
551 * descriptor, we should consider ourselves lucky that the
552 * controller flagged an error instead of scribbling over
553 * random memory locations.
555 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
556 " cookie: %d\n", bad_desc->txd.cookie);
557 dwc_dump_lli(dwc, &bad_desc->lli);
558 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
559 dwc_dump_lli(dwc, &child->lli);
561 spin_unlock_irqrestore(&dwc->lock, flags);
563 /* Pretend the descriptor completed successfully */
564 dwc_descriptor_complete(dwc, bad_desc, true);
567 /* --------------------- Cyclic DMA API extensions -------------------- */
569 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
571 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
572 return channel_readl(dwc, SAR);
574 EXPORT_SYMBOL(dw_dma_get_src_addr);
576 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
578 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
579 return channel_readl(dwc, DAR);
581 EXPORT_SYMBOL(dw_dma_get_dst_addr);
583 /* called with dwc->lock held and all DMAC interrupts disabled */
584 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
585 u32 status_err, u32 status_xfer)
590 void (*callback)(void *param);
591 void *callback_param;
593 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
594 channel_readl(dwc, LLP));
596 callback = dwc->cdesc->period_callback;
597 callback_param = dwc->cdesc->period_callback_param;
600 callback(callback_param);
604 * Error and transfer complete are highly unlikely, and will most
605 * likely be due to a configuration error by the user.
607 if (unlikely(status_err & dwc->mask) ||
608 unlikely(status_xfer & dwc->mask)) {
611 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
612 "interrupt, stopping DMA transfer\n",
613 status_xfer ? "xfer" : "error");
615 spin_lock_irqsave(&dwc->lock, flags);
617 dwc_dump_chan_regs(dwc);
619 dwc_chan_disable(dw, dwc);
621 /* make sure DMA does not restart by loading a new list */
622 channel_writel(dwc, LLP, 0);
623 channel_writel(dwc, CTL_LO, 0);
624 channel_writel(dwc, CTL_HI, 0);
626 dma_writel(dw, CLEAR.ERROR, dwc->mask);
627 dma_writel(dw, CLEAR.XFER, dwc->mask);
629 for (i = 0; i < dwc->cdesc->periods; i++)
630 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
632 spin_unlock_irqrestore(&dwc->lock, flags);
636 /* ------------------------------------------------------------------------- */
638 static void dw_dma_tasklet(unsigned long data)
640 struct dw_dma *dw = (struct dw_dma *)data;
641 struct dw_dma_chan *dwc;
646 status_xfer = dma_readl(dw, RAW.XFER);
647 status_err = dma_readl(dw, RAW.ERROR);
649 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
651 for (i = 0; i < dw->dma.chancnt; i++) {
653 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
654 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
655 else if (status_err & (1 << i))
656 dwc_handle_error(dw, dwc);
657 else if (status_xfer & (1 << i))
658 dwc_scan_descriptors(dw, dwc);
662 * Re-enable interrupts.
664 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
665 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
668 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
670 struct dw_dma *dw = dev_id;
673 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
674 dma_readl(dw, STATUS_INT));
677 * Just disable the interrupts. We'll turn them back on in the
680 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
681 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
683 status = dma_readl(dw, STATUS_INT);
686 "BUG: Unexpected interrupts pending: 0x%x\n",
690 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
691 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
692 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
693 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
696 tasklet_schedule(&dw->tasklet);
701 /*----------------------------------------------------------------------*/
703 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
705 struct dw_desc *desc = txd_to_dw_desc(tx);
706 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
710 spin_lock_irqsave(&dwc->lock, flags);
711 cookie = dma_cookie_assign(tx);
714 * REVISIT: We should attempt to chain as many descriptors as
715 * possible, perhaps even appending to those already submitted
716 * for DMA. But this is hard to do in a race-free manner.
718 if (list_empty(&dwc->active_list)) {
719 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
721 list_add_tail(&desc->desc_node, &dwc->active_list);
722 dwc_dostart(dwc, dwc_first_active(dwc));
724 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
727 list_add_tail(&desc->desc_node, &dwc->queue);
730 spin_unlock_irqrestore(&dwc->lock, flags);
735 static struct dma_async_tx_descriptor *
736 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
737 size_t len, unsigned long flags)
739 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
740 struct dw_desc *desc;
741 struct dw_desc *first;
742 struct dw_desc *prev;
745 unsigned int src_width;
746 unsigned int dst_width;
747 unsigned int data_width;
750 dev_vdbg(chan2dev(chan),
751 "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
752 (unsigned long long)dest, (unsigned long long)src,
755 if (unlikely(!len)) {
756 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
760 dwc->direction = DMA_MEM_TO_MEM;
762 data_width = min_t(unsigned int, dwc_get_data_width(chan, SRC_MASTER),
763 dwc_get_data_width(chan, DST_MASTER));
765 src_width = dst_width = min_t(unsigned int, data_width,
766 dwc_fast_fls(src | dest | len));
768 ctllo = DWC_DEFAULT_CTLLO(chan)
769 | DWC_CTLL_DST_WIDTH(dst_width)
770 | DWC_CTLL_SRC_WIDTH(src_width)
776 for (offset = 0; offset < len; offset += xfer_count << src_width) {
777 xfer_count = min_t(size_t, (len - offset) >> src_width,
780 desc = dwc_desc_get(dwc);
784 desc->lli.sar = src + offset;
785 desc->lli.dar = dest + offset;
786 desc->lli.ctllo = ctllo;
787 desc->lli.ctlhi = xfer_count;
788 desc->len = xfer_count << src_width;
793 prev->lli.llp = desc->txd.phys;
794 list_add_tail(&desc->desc_node,
800 if (flags & DMA_PREP_INTERRUPT)
801 /* Trigger interrupt after last block */
802 prev->lli.ctllo |= DWC_CTLL_INT_EN;
805 first->txd.flags = flags;
806 first->total_len = len;
811 dwc_desc_put(dwc, first);
815 static struct dma_async_tx_descriptor *
816 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
817 unsigned int sg_len, enum dma_transfer_direction direction,
818 unsigned long flags, void *context)
820 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
821 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
822 struct dw_desc *prev;
823 struct dw_desc *first;
826 unsigned int reg_width;
827 unsigned int mem_width;
828 unsigned int data_width;
830 struct scatterlist *sg;
831 size_t total_len = 0;
833 dev_vdbg(chan2dev(chan), "%s\n", __func__);
835 if (unlikely(!is_slave_direction(direction) || !sg_len))
838 dwc->direction = direction;
844 reg_width = __fls(sconfig->dst_addr_width);
845 reg = sconfig->dst_addr;
846 ctllo = (DWC_DEFAULT_CTLLO(chan)
847 | DWC_CTLL_DST_WIDTH(reg_width)
851 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
852 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
854 data_width = dwc_get_data_width(chan, SRC_MASTER);
856 for_each_sg(sgl, sg, sg_len, i) {
857 struct dw_desc *desc;
860 mem = sg_dma_address(sg);
861 len = sg_dma_len(sg);
863 mem_width = min_t(unsigned int,
864 data_width, dwc_fast_fls(mem | len));
866 slave_sg_todev_fill_desc:
867 desc = dwc_desc_get(dwc);
869 dev_err(chan2dev(chan),
870 "not enough descriptors available\n");
876 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
877 if ((len >> mem_width) > dwc->block_size) {
878 dlen = dwc->block_size << mem_width;
886 desc->lli.ctlhi = dlen >> mem_width;
892 prev->lli.llp = desc->txd.phys;
893 list_add_tail(&desc->desc_node,
900 goto slave_sg_todev_fill_desc;
904 reg_width = __fls(sconfig->src_addr_width);
905 reg = sconfig->src_addr;
906 ctllo = (DWC_DEFAULT_CTLLO(chan)
907 | DWC_CTLL_SRC_WIDTH(reg_width)
911 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
912 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
914 data_width = dwc_get_data_width(chan, DST_MASTER);
916 for_each_sg(sgl, sg, sg_len, i) {
917 struct dw_desc *desc;
920 mem = sg_dma_address(sg);
921 len = sg_dma_len(sg);
923 mem_width = min_t(unsigned int,
924 data_width, dwc_fast_fls(mem | len));
926 slave_sg_fromdev_fill_desc:
927 desc = dwc_desc_get(dwc);
929 dev_err(chan2dev(chan),
930 "not enough descriptors available\n");
936 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
937 if ((len >> reg_width) > dwc->block_size) {
938 dlen = dwc->block_size << reg_width;
945 desc->lli.ctlhi = dlen >> reg_width;
951 prev->lli.llp = desc->txd.phys;
952 list_add_tail(&desc->desc_node,
959 goto slave_sg_fromdev_fill_desc;
966 if (flags & DMA_PREP_INTERRUPT)
967 /* Trigger interrupt after last block */
968 prev->lli.ctllo |= DWC_CTLL_INT_EN;
971 first->total_len = total_len;
976 dwc_desc_put(dwc, first);
981 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
982 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
984 * NOTE: burst size 2 is not supported by controller.
986 * This can be done by finding least significant bit set: n & (n - 1)
988 static inline void convert_burst(u32 *maxburst)
991 *maxburst = fls(*maxburst) - 2;
997 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
999 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1001 /* Check if chan will be configured for slave transfers */
1002 if (!is_slave_direction(sconfig->direction))
1005 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
1006 dwc->direction = sconfig->direction;
1008 convert_burst(&dwc->dma_sconfig.src_maxburst);
1009 convert_burst(&dwc->dma_sconfig.dst_maxburst);
1014 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
1016 u32 cfglo = channel_readl(dwc, CFG_LO);
1018 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
1019 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
1025 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1027 u32 cfglo = channel_readl(dwc, CFG_LO);
1029 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1031 dwc->paused = false;
1034 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1037 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1038 struct dw_dma *dw = to_dw_dma(chan->device);
1039 struct dw_desc *desc, *_desc;
1040 unsigned long flags;
1043 if (cmd == DMA_PAUSE) {
1044 spin_lock_irqsave(&dwc->lock, flags);
1046 dwc_chan_pause(dwc);
1048 spin_unlock_irqrestore(&dwc->lock, flags);
1049 } else if (cmd == DMA_RESUME) {
1053 spin_lock_irqsave(&dwc->lock, flags);
1055 dwc_chan_resume(dwc);
1057 spin_unlock_irqrestore(&dwc->lock, flags);
1058 } else if (cmd == DMA_TERMINATE_ALL) {
1059 spin_lock_irqsave(&dwc->lock, flags);
1061 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1063 dwc_chan_disable(dw, dwc);
1065 dwc_chan_resume(dwc);
1067 /* active_list entries will end up before queued entries */
1068 list_splice_init(&dwc->queue, &list);
1069 list_splice_init(&dwc->active_list, &list);
1071 spin_unlock_irqrestore(&dwc->lock, flags);
1073 /* Flush all pending and queued descriptors */
1074 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1075 dwc_descriptor_complete(dwc, desc, false);
1076 } else if (cmd == DMA_SLAVE_CONFIG) {
1077 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1085 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1087 unsigned long flags;
1090 spin_lock_irqsave(&dwc->lock, flags);
1092 residue = dwc->residue;
1093 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1094 residue -= dwc_get_sent(dwc);
1096 spin_unlock_irqrestore(&dwc->lock, flags);
1100 static enum dma_status
1101 dwc_tx_status(struct dma_chan *chan,
1102 dma_cookie_t cookie,
1103 struct dma_tx_state *txstate)
1105 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1106 enum dma_status ret;
1108 ret = dma_cookie_status(chan, cookie, txstate);
1109 if (ret != DMA_SUCCESS) {
1110 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1112 ret = dma_cookie_status(chan, cookie, txstate);
1115 if (ret != DMA_SUCCESS)
1116 dma_set_residue(txstate, dwc_get_residue(dwc));
1124 static void dwc_issue_pending(struct dma_chan *chan)
1126 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1128 if (!list_empty(&dwc->queue))
1129 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1132 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1134 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1135 struct dw_dma *dw = to_dw_dma(chan->device);
1136 struct dw_desc *desc;
1138 unsigned long flags;
1140 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1142 /* ASSERT: channel is idle */
1143 if (dma_readl(dw, CH_EN) & dwc->mask) {
1144 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1148 dma_cookie_init(chan);
1151 * NOTE: some controllers may have additional features that we
1152 * need to initialize here, like "scatter-gather" (which
1153 * doesn't mean what you think it means), and status writeback.
1156 spin_lock_irqsave(&dwc->lock, flags);
1157 i = dwc->descs_allocated;
1158 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1161 spin_unlock_irqrestore(&dwc->lock, flags);
1163 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1165 goto err_desc_alloc;
1167 memset(desc, 0, sizeof(struct dw_desc));
1169 INIT_LIST_HEAD(&desc->tx_list);
1170 dma_async_tx_descriptor_init(&desc->txd, chan);
1171 desc->txd.tx_submit = dwc_tx_submit;
1172 desc->txd.flags = DMA_CTRL_ACK;
1173 desc->txd.phys = phys;
1175 dwc_desc_put(dwc, desc);
1177 spin_lock_irqsave(&dwc->lock, flags);
1178 i = ++dwc->descs_allocated;
1181 spin_unlock_irqrestore(&dwc->lock, flags);
1183 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1188 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1193 static void dwc_free_chan_resources(struct dma_chan *chan)
1195 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1196 struct dw_dma *dw = to_dw_dma(chan->device);
1197 struct dw_desc *desc, *_desc;
1198 unsigned long flags;
1201 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1202 dwc->descs_allocated);
1204 /* ASSERT: channel is idle */
1205 BUG_ON(!list_empty(&dwc->active_list));
1206 BUG_ON(!list_empty(&dwc->queue));
1207 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1209 spin_lock_irqsave(&dwc->lock, flags);
1210 list_splice_init(&dwc->free_list, &list);
1211 dwc->descs_allocated = 0;
1212 dwc->initialized = false;
1214 /* Disable interrupts */
1215 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1216 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1218 spin_unlock_irqrestore(&dwc->lock, flags);
1220 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1221 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1222 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1225 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1228 bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
1230 struct dw_dma *dw = to_dw_dma(chan->device);
1231 static struct dw_dma *last_dw;
1232 static char *last_bus_id;
1236 * dmaengine framework calls this routine for all channels of all dma
1237 * controller, until true is returned. If 'param' bus_id is not
1238 * registered with a dma controller (dw), then there is no need of
1239 * running below function for all channels of dw.
1241 * This block of code does this by saving the parameters of last
1242 * failure. If dw and param are same, i.e. trying on same dw with
1243 * different channel, return false.
1245 if ((last_dw == dw) && (last_bus_id == param))
1249 * - If dw_dma's platform data is not filled with slave info, then all
1250 * dma controllers are fine for transfer.
1251 * - Or if param is NULL
1253 if (!dw->sd || !param)
1256 while (++i < dw->sd_count) {
1257 if (!strcmp(dw->sd[i].bus_id, param)) {
1258 chan->private = &dw->sd[i];
1267 last_bus_id = param;
1270 EXPORT_SYMBOL(dw_dma_generic_filter);
1272 /* --------------------- Cyclic DMA API extensions -------------------- */
1275 * dw_dma_cyclic_start - start the cyclic DMA transfer
1276 * @chan: the DMA channel to start
1278 * Must be called with soft interrupts disabled. Returns zero on success or
1279 * -errno on failure.
1281 int dw_dma_cyclic_start(struct dma_chan *chan)
1283 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1284 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1285 unsigned long flags;
1287 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1288 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1292 spin_lock_irqsave(&dwc->lock, flags);
1294 /* assert channel is idle */
1295 if (dma_readl(dw, CH_EN) & dwc->mask) {
1296 dev_err(chan2dev(&dwc->chan),
1297 "BUG: Attempted to start non-idle channel\n");
1298 dwc_dump_chan_regs(dwc);
1299 spin_unlock_irqrestore(&dwc->lock, flags);
1303 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1304 dma_writel(dw, CLEAR.XFER, dwc->mask);
1306 /* setup DMAC channel registers */
1307 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1308 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1309 channel_writel(dwc, CTL_HI, 0);
1311 channel_set_bit(dw, CH_EN, dwc->mask);
1313 spin_unlock_irqrestore(&dwc->lock, flags);
1317 EXPORT_SYMBOL(dw_dma_cyclic_start);
1320 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1321 * @chan: the DMA channel to stop
1323 * Must be called with soft interrupts disabled.
1325 void dw_dma_cyclic_stop(struct dma_chan *chan)
1327 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1328 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1329 unsigned long flags;
1331 spin_lock_irqsave(&dwc->lock, flags);
1333 dwc_chan_disable(dw, dwc);
1335 spin_unlock_irqrestore(&dwc->lock, flags);
1337 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1340 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1341 * @chan: the DMA channel to prepare
1342 * @buf_addr: physical DMA address where the buffer starts
1343 * @buf_len: total number of bytes for the entire buffer
1344 * @period_len: number of bytes for each period
1345 * @direction: transfer direction, to or from device
1347 * Must be called before trying to start the transfer. Returns a valid struct
1348 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1350 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1351 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1352 enum dma_transfer_direction direction)
1354 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1355 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1356 struct dw_cyclic_desc *cdesc;
1357 struct dw_cyclic_desc *retval = NULL;
1358 struct dw_desc *desc;
1359 struct dw_desc *last = NULL;
1360 unsigned long was_cyclic;
1361 unsigned int reg_width;
1362 unsigned int periods;
1364 unsigned long flags;
1366 spin_lock_irqsave(&dwc->lock, flags);
1368 spin_unlock_irqrestore(&dwc->lock, flags);
1369 dev_dbg(chan2dev(&dwc->chan),
1370 "channel doesn't support LLP transfers\n");
1371 return ERR_PTR(-EINVAL);
1374 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1375 spin_unlock_irqrestore(&dwc->lock, flags);
1376 dev_dbg(chan2dev(&dwc->chan),
1377 "queue and/or active list are not empty\n");
1378 return ERR_PTR(-EBUSY);
1381 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1382 spin_unlock_irqrestore(&dwc->lock, flags);
1384 dev_dbg(chan2dev(&dwc->chan),
1385 "channel already prepared for cyclic DMA\n");
1386 return ERR_PTR(-EBUSY);
1389 retval = ERR_PTR(-EINVAL);
1391 if (unlikely(!is_slave_direction(direction)))
1394 dwc->direction = direction;
1396 if (direction == DMA_MEM_TO_DEV)
1397 reg_width = __ffs(sconfig->dst_addr_width);
1399 reg_width = __ffs(sconfig->src_addr_width);
1401 periods = buf_len / period_len;
1403 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1404 if (period_len > (dwc->block_size << reg_width))
1406 if (unlikely(period_len & ((1 << reg_width) - 1)))
1408 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1411 retval = ERR_PTR(-ENOMEM);
1413 if (periods > NR_DESCS_PER_CHANNEL)
1416 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1420 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1424 for (i = 0; i < periods; i++) {
1425 desc = dwc_desc_get(dwc);
1427 goto out_err_desc_get;
1429 switch (direction) {
1430 case DMA_MEM_TO_DEV:
1431 desc->lli.dar = sconfig->dst_addr;
1432 desc->lli.sar = buf_addr + (period_len * i);
1433 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1434 | DWC_CTLL_DST_WIDTH(reg_width)
1435 | DWC_CTLL_SRC_WIDTH(reg_width)
1440 desc->lli.ctllo |= sconfig->device_fc ?
1441 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1442 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1445 case DMA_DEV_TO_MEM:
1446 desc->lli.dar = buf_addr + (period_len * i);
1447 desc->lli.sar = sconfig->src_addr;
1448 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1449 | DWC_CTLL_SRC_WIDTH(reg_width)
1450 | DWC_CTLL_DST_WIDTH(reg_width)
1455 desc->lli.ctllo |= sconfig->device_fc ?
1456 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1457 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1464 desc->lli.ctlhi = (period_len >> reg_width);
1465 cdesc->desc[i] = desc;
1468 last->lli.llp = desc->txd.phys;
1473 /* lets make a cyclic list */
1474 last->lli.llp = cdesc->desc[0]->txd.phys;
1476 dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1477 "period %zu periods %d\n", (unsigned long long)buf_addr,
1478 buf_len, period_len, periods);
1480 cdesc->periods = periods;
1487 dwc_desc_put(dwc, cdesc->desc[i]);
1491 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1492 return (struct dw_cyclic_desc *)retval;
1494 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1497 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1498 * @chan: the DMA channel to free
1500 void dw_dma_cyclic_free(struct dma_chan *chan)
1502 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1503 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1504 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1506 unsigned long flags;
1508 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1513 spin_lock_irqsave(&dwc->lock, flags);
1515 dwc_chan_disable(dw, dwc);
1517 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1518 dma_writel(dw, CLEAR.XFER, dwc->mask);
1520 spin_unlock_irqrestore(&dwc->lock, flags);
1522 for (i = 0; i < cdesc->periods; i++)
1523 dwc_desc_put(dwc, cdesc->desc[i]);
1528 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1530 EXPORT_SYMBOL(dw_dma_cyclic_free);
1532 /*----------------------------------------------------------------------*/
1534 static void dw_dma_off(struct dw_dma *dw)
1538 dma_writel(dw, CFG, 0);
1540 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1541 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1542 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1543 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1545 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1548 for (i = 0; i < dw->dma.chancnt; i++)
1549 dw->chan[i].initialized = false;
1553 static struct dw_dma_platform_data *
1554 dw_dma_parse_dt(struct platform_device *pdev)
1556 struct device_node *sn, *cn, *np = pdev->dev.of_node;
1557 struct dw_dma_platform_data *pdata;
1558 struct dw_dma_slave *sd;
1562 dev_err(&pdev->dev, "Missing DT data\n");
1566 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1570 if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
1573 if (of_property_read_bool(np, "is_private"))
1574 pdata->is_private = true;
1576 if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
1577 pdata->chan_allocation_order = (unsigned char)tmp;
1579 if (!of_property_read_u32(np, "chan_priority", &tmp))
1580 pdata->chan_priority = tmp;
1582 if (!of_property_read_u32(np, "block_size", &tmp))
1583 pdata->block_size = tmp;
1585 if (!of_property_read_u32(np, "nr_masters", &tmp)) {
1589 pdata->nr_masters = tmp;
1592 if (!of_property_read_u32_array(np, "data_width", arr,
1594 for (tmp = 0; tmp < pdata->nr_masters; tmp++)
1595 pdata->data_width[tmp] = arr[tmp];
1597 /* parse slave data */
1598 sn = of_find_node_by_name(np, "slave_info");
1602 /* calculate number of slaves */
1603 tmp = of_get_child_count(sn);
1607 sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
1612 pdata->sd_count = tmp;
1614 for_each_child_of_node(sn, cn) {
1615 sd->dma_dev = &pdev->dev;
1616 of_property_read_string(cn, "bus_id", &sd->bus_id);
1617 of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
1618 of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
1619 if (!of_property_read_u32(cn, "src_master", &tmp))
1620 sd->src_master = tmp;
1622 if (!of_property_read_u32(cn, "dst_master", &tmp))
1623 sd->dst_master = tmp;
1630 static inline struct dw_dma_platform_data *
1631 dw_dma_parse_dt(struct platform_device *pdev)
1637 static int dw_probe(struct platform_device *pdev)
1639 struct dw_dma_platform_data *pdata;
1640 struct resource *io;
1645 unsigned int dw_params;
1646 unsigned int nr_channels;
1647 unsigned int max_blk_size = 0;
1652 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1656 irq = platform_get_irq(pdev, 0);
1660 regs = devm_request_and_ioremap(&pdev->dev, io);
1664 dw_params = dma_read_byaddr(regs, DW_PARAMS);
1665 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1667 dev_dbg(&pdev->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1669 pdata = dev_get_platdata(&pdev->dev);
1671 pdata = dw_dma_parse_dt(pdev);
1673 if (!pdata && autocfg) {
1674 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1678 /* Fill platform data with the default values */
1679 pdata->is_private = true;
1680 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1681 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1682 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1686 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1688 nr_channels = pdata->nr_channels;
1690 size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1691 dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1695 dw->clk = devm_clk_get(&pdev->dev, "hclk");
1696 if (IS_ERR(dw->clk))
1697 return PTR_ERR(dw->clk);
1698 clk_prepare_enable(dw->clk);
1702 dw->sd_count = pdata->sd_count;
1704 /* get hardware configuration parameters */
1706 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1708 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1709 for (i = 0; i < dw->nr_masters; i++) {
1711 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1714 dw->nr_masters = pdata->nr_masters;
1715 memcpy(dw->data_width, pdata->data_width, 4);
1718 /* Calculate all channel mask before DMA setup */
1719 dw->all_chan_mask = (1 << nr_channels) - 1;
1721 /* force dma off, just in case */
1724 /* disable BLOCK interrupts as well */
1725 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1727 err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1732 platform_set_drvdata(pdev, dw);
1734 /* create a pool of consistent memory blocks for hardware descriptors */
1735 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev,
1736 sizeof(struct dw_desc), 4, 0);
1737 if (!dw->desc_pool) {
1738 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1742 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1744 INIT_LIST_HEAD(&dw->dma.channels);
1745 for (i = 0; i < nr_channels; i++) {
1746 struct dw_dma_chan *dwc = &dw->chan[i];
1747 int r = nr_channels - i - 1;
1749 dwc->chan.device = &dw->dma;
1750 dma_cookie_init(&dwc->chan);
1751 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1752 list_add_tail(&dwc->chan.device_node,
1755 list_add(&dwc->chan.device_node, &dw->dma.channels);
1757 /* 7 is highest priority & 0 is lowest. */
1758 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1763 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1764 spin_lock_init(&dwc->lock);
1767 INIT_LIST_HEAD(&dwc->active_list);
1768 INIT_LIST_HEAD(&dwc->queue);
1769 INIT_LIST_HEAD(&dwc->free_list);
1771 channel_clear_bit(dw, CH_EN, dwc->mask);
1773 dwc->direction = DMA_TRANS_NONE;
1775 /* hardware configuration */
1777 unsigned int dwc_params;
1779 dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1782 dev_dbg(&pdev->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1785 /* Decode maximum block size for given channel. The
1786 * stored 4 bit value represents blocks from 0x00 for 3
1787 * up to 0x0a for 4095. */
1789 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1791 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1793 dwc->block_size = pdata->block_size;
1795 /* Check if channel supports multi block transfer */
1796 channel_writel(dwc, LLP, 0xfffffffc);
1798 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1799 channel_writel(dwc, LLP, 0);
1803 /* Clear all interrupts on all channels. */
1804 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1805 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1806 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1807 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1808 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1810 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1811 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1812 if (pdata->is_private)
1813 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1814 dw->dma.dev = &pdev->dev;
1815 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1816 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1818 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1820 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1821 dw->dma.device_control = dwc_control;
1823 dw->dma.device_tx_status = dwc_tx_status;
1824 dw->dma.device_issue_pending = dwc_issue_pending;
1826 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1828 dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n",
1831 dma_async_device_register(&dw->dma);
1836 static int __devexit dw_remove(struct platform_device *pdev)
1838 struct dw_dma *dw = platform_get_drvdata(pdev);
1839 struct dw_dma_chan *dwc, *_dwc;
1842 dma_async_device_unregister(&dw->dma);
1844 tasklet_kill(&dw->tasklet);
1846 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1848 list_del(&dwc->chan.device_node);
1849 channel_clear_bit(dw, CH_EN, dwc->mask);
1855 static void dw_shutdown(struct platform_device *pdev)
1857 struct dw_dma *dw = platform_get_drvdata(pdev);
1860 clk_disable_unprepare(dw->clk);
1863 static int dw_suspend_noirq(struct device *dev)
1865 struct platform_device *pdev = to_platform_device(dev);
1866 struct dw_dma *dw = platform_get_drvdata(pdev);
1869 clk_disable_unprepare(dw->clk);
1874 static int dw_resume_noirq(struct device *dev)
1876 struct platform_device *pdev = to_platform_device(dev);
1877 struct dw_dma *dw = platform_get_drvdata(pdev);
1879 clk_prepare_enable(dw->clk);
1880 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1885 static const struct dev_pm_ops dw_dev_pm_ops = {
1886 .suspend_noirq = dw_suspend_noirq,
1887 .resume_noirq = dw_resume_noirq,
1888 .freeze_noirq = dw_suspend_noirq,
1889 .thaw_noirq = dw_resume_noirq,
1890 .restore_noirq = dw_resume_noirq,
1891 .poweroff_noirq = dw_suspend_noirq,
1895 static const struct of_device_id dw_dma_id_table[] = {
1896 { .compatible = "snps,dma-spear1340" },
1899 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1902 static struct platform_driver dw_driver = {
1904 .remove = dw_remove,
1905 .shutdown = dw_shutdown,
1908 .pm = &dw_dev_pm_ops,
1909 .of_match_table = of_match_ptr(dw_dma_id_table),
1913 static int __init dw_init(void)
1915 return platform_driver_register(&dw_driver);
1917 subsys_initcall(dw_init);
1919 static void __exit dw_exit(void)
1921 platform_driver_unregister(&dw_driver);
1923 module_exit(dw_exit);
1925 MODULE_LICENSE("GPL v2");
1926 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1927 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1928 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");