1 // SPDX-License-Identifier: GPL-2.0-only
3 * DMA Engine test module
5 * Copyright (C) 2007 Atmel Corporation
6 * Copyright (C) 2013 Intel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/freezer.h>
14 #include <linux/init.h>
15 #include <linux/kthread.h>
16 #include <linux/sched/task.h>
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/random.h>
20 #include <linux/slab.h>
21 #include <linux/wait.h>
23 static unsigned int test_buf_size = 16384;
24 module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
25 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
27 static char test_device[32];
28 module_param_string(device, test_device, sizeof(test_device),
30 MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
32 static unsigned int threads_per_chan = 1;
33 module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(threads_per_chan,
35 "Number of threads to start per channel (default: 1)");
37 static unsigned int max_channels;
38 module_param(max_channels, uint, S_IRUGO | S_IWUSR);
39 MODULE_PARM_DESC(max_channels,
40 "Maximum number of channels to use (default: all)");
42 static unsigned int iterations;
43 module_param(iterations, uint, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(iterations,
45 "Iterations before stopping test (default: infinite)");
47 static unsigned int dmatest;
48 module_param(dmatest, uint, S_IRUGO | S_IWUSR);
49 MODULE_PARM_DESC(dmatest,
50 "dmatest 0-memcpy 1-memset (default: 0)");
52 static unsigned int xor_sources = 3;
53 module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
54 MODULE_PARM_DESC(xor_sources,
55 "Number of xor source buffers (default: 3)");
57 static unsigned int pq_sources = 3;
58 module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
59 MODULE_PARM_DESC(pq_sources,
60 "Number of p+q source buffers (default: 3)");
62 static int timeout = 3000;
63 module_param(timeout, int, S_IRUGO | S_IWUSR);
64 MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
65 "Pass -1 for infinite timeout");
68 module_param(noverify, bool, S_IRUGO | S_IWUSR);
69 MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
72 module_param(norandom, bool, 0644);
73 MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
76 module_param(verbose, bool, S_IRUGO | S_IWUSR);
77 MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
79 static int alignment = -1;
80 module_param(alignment, int, 0644);
81 MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))");
83 static unsigned int transfer_size;
84 module_param(transfer_size, uint, 0644);
85 MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
88 module_param(polled, bool, S_IRUGO | S_IWUSR);
89 MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
92 * struct dmatest_params - test parameters.
93 * @buf_size: size of the memcpy test buffer
94 * @channel: bus ID of the channel to test
95 * @device: bus ID of the DMA Engine to test
96 * @threads_per_chan: number of threads to start per channel
97 * @max_channels: maximum number of channels to use
98 * @iterations: iterations before stopping test
99 * @xor_sources: number of xor source buffers
100 * @pq_sources: number of p+q source buffers
101 * @timeout: transfer timeout in msec, -1 for infinite timeout
102 * @noverify: disable data verification
103 * @norandom: disable random offset setup
104 * @alignment: custom data address alignment taken as 2^alignment
105 * @transfer_size: custom transfer size in bytes
106 * @polled: use polling for completion instead of interrupts
108 struct dmatest_params {
109 unsigned int buf_size;
112 unsigned int threads_per_chan;
113 unsigned int max_channels;
114 unsigned int iterations;
115 unsigned int xor_sources;
116 unsigned int pq_sources;
121 unsigned int transfer_size;
126 * struct dmatest_info - test information.
127 * @params: test parameters
128 * @channels: channels under test
129 * @nr_channels: number of channels under test
130 * @lock: access protection to the fields of this structure
131 * @did_init: module has been initialized completely
133 static struct dmatest_info {
134 /* Test parameters */
135 struct dmatest_params params;
138 struct list_head channels;
139 unsigned int nr_channels;
143 .channels = LIST_HEAD_INIT(test_info.channels),
144 .lock = __MUTEX_INITIALIZER(test_info.lock),
147 static int dmatest_run_set(const char *val, const struct kernel_param *kp);
148 static int dmatest_run_get(char *val, const struct kernel_param *kp);
149 static const struct kernel_param_ops run_ops = {
150 .set = dmatest_run_set,
151 .get = dmatest_run_get,
153 static bool dmatest_run;
154 module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
155 MODULE_PARM_DESC(run, "Run the test (default: false)");
157 static int dmatest_chan_set(const char *val, const struct kernel_param *kp);
158 static int dmatest_chan_get(char *val, const struct kernel_param *kp);
159 static const struct kernel_param_ops multi_chan_ops = {
160 .set = dmatest_chan_set,
161 .get = dmatest_chan_get,
164 static char test_channel[20];
165 static struct kparam_string newchan_kps = {
166 .string = test_channel,
169 module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644);
170 MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
172 static int dmatest_test_list_get(char *val, const struct kernel_param *kp);
173 static const struct kernel_param_ops test_list_ops = {
174 .get = dmatest_test_list_get,
176 module_param_cb(test_list, &test_list_ops, NULL, 0444);
177 MODULE_PARM_DESC(test_list, "Print current test list");
179 /* Maximum amount of mismatched bytes in buffer to print */
180 #define MAX_ERROR_COUNT 32
183 * Initialization patterns. All bytes in the source buffer has bit 7
184 * set, all bytes in the destination buffer has bit 7 cleared.
186 * Bit 6 is set for all bytes which are to be copied by the DMA
187 * engine. Bit 5 is set for all bytes which are to be overwritten by
190 * The remaining bits are the inverse of a counter which increments by
191 * one for each byte address.
193 #define PATTERN_SRC 0x80
194 #define PATTERN_DST 0x00
195 #define PATTERN_COPY 0x40
196 #define PATTERN_OVERWRITE 0x20
197 #define PATTERN_COUNT_MASK 0x1f
198 #define PATTERN_MEMSET_IDX 0x01
200 /* Fixed point arithmetic ops */
201 #define FIXPT_SHIFT 8
202 #define FIXPNT_MASK 0xFF
203 #define FIXPT_TO_INT(a) ((a) >> FIXPT_SHIFT)
204 #define INT_TO_FIXPT(a) ((a) << FIXPT_SHIFT)
205 #define FIXPT_GET_FRAC(a) ((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT)
207 /* poor man's completion - we want to use wait_event_freezable() on it */
208 struct dmatest_done {
210 wait_queue_head_t *wait;
213 struct dmatest_data {
220 struct dmatest_thread {
221 struct list_head node;
222 struct dmatest_info *info;
223 struct task_struct *task;
224 struct dma_chan *chan;
225 struct dmatest_data src;
226 struct dmatest_data dst;
227 enum dma_transaction_type type;
228 wait_queue_head_t done_wait;
229 struct dmatest_done test_done;
234 struct dmatest_chan {
235 struct list_head node;
236 struct dma_chan *chan;
237 struct list_head threads;
240 static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
243 static bool is_threaded_test_run(struct dmatest_info *info)
245 struct dmatest_chan *dtc;
247 list_for_each_entry(dtc, &info->channels, node) {
248 struct dmatest_thread *thread;
250 list_for_each_entry(thread, &dtc->threads, node) {
251 if (!thread->done && !thread->pending)
259 static bool is_threaded_test_pending(struct dmatest_info *info)
261 struct dmatest_chan *dtc;
263 list_for_each_entry(dtc, &info->channels, node) {
264 struct dmatest_thread *thread;
266 list_for_each_entry(thread, &dtc->threads, node) {
275 static int dmatest_wait_get(char *val, const struct kernel_param *kp)
277 struct dmatest_info *info = &test_info;
278 struct dmatest_params *params = &info->params;
280 if (params->iterations)
281 wait_event(thread_wait, !is_threaded_test_run(info));
283 return param_get_bool(val, kp);
286 static const struct kernel_param_ops wait_ops = {
287 .get = dmatest_wait_get,
288 .set = param_set_bool,
290 module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
291 MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
293 static bool dmatest_match_channel(struct dmatest_params *params,
294 struct dma_chan *chan)
296 if (params->channel[0] == '\0')
298 return strcmp(dma_chan_name(chan), params->channel) == 0;
301 static bool dmatest_match_device(struct dmatest_params *params,
302 struct dma_device *device)
304 if (params->device[0] == '\0')
306 return strcmp(dev_name(device->dev), params->device) == 0;
309 static unsigned long dmatest_random(void)
313 prandom_bytes(&buf, sizeof(buf));
317 static inline u8 gen_inv_idx(u8 index, bool is_memset)
319 u8 val = is_memset ? PATTERN_MEMSET_IDX : index;
321 return ~val & PATTERN_COUNT_MASK;
324 static inline u8 gen_src_value(u8 index, bool is_memset)
326 return PATTERN_SRC | gen_inv_idx(index, is_memset);
329 static inline u8 gen_dst_value(u8 index, bool is_memset)
331 return PATTERN_DST | gen_inv_idx(index, is_memset);
334 static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
335 unsigned int buf_size, bool is_memset)
340 for (; (buf = *bufs); bufs++) {
341 for (i = 0; i < start; i++)
342 buf[i] = gen_src_value(i, is_memset);
343 for ( ; i < start + len; i++)
344 buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY;
345 for ( ; i < buf_size; i++)
346 buf[i] = gen_src_value(i, is_memset);
351 static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
352 unsigned int buf_size, bool is_memset)
357 for (; (buf = *bufs); bufs++) {
358 for (i = 0; i < start; i++)
359 buf[i] = gen_dst_value(i, is_memset);
360 for ( ; i < start + len; i++)
361 buf[i] = gen_dst_value(i, is_memset) |
363 for ( ; i < buf_size; i++)
364 buf[i] = gen_dst_value(i, is_memset);
368 static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
369 unsigned int counter, bool is_srcbuf, bool is_memset)
371 u8 diff = actual ^ pattern;
372 u8 expected = pattern | gen_inv_idx(counter, is_memset);
373 const char *thread_name = current->comm;
376 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
377 thread_name, index, expected, actual);
378 else if ((pattern & PATTERN_COPY)
379 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
380 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
381 thread_name, index, expected, actual);
382 else if (diff & PATTERN_SRC)
383 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
384 thread_name, index, expected, actual);
386 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
387 thread_name, index, expected, actual);
390 static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
391 unsigned int end, unsigned int counter, u8 pattern,
392 bool is_srcbuf, bool is_memset)
395 unsigned int error_count = 0;
399 unsigned int counter_orig = counter;
401 for (; (buf = *bufs); bufs++) {
402 counter = counter_orig;
403 for (i = start; i < end; i++) {
405 expected = pattern | gen_inv_idx(counter, is_memset);
406 if (actual != expected) {
407 if (error_count < MAX_ERROR_COUNT)
408 dmatest_mismatch(actual, pattern, i,
417 if (error_count > MAX_ERROR_COUNT)
418 pr_warn("%s: %u errors suppressed\n",
419 current->comm, error_count - MAX_ERROR_COUNT);
425 static void dmatest_callback(void *arg)
427 struct dmatest_done *done = arg;
428 struct dmatest_thread *thread =
429 container_of(done, struct dmatest_thread, test_done);
432 wake_up_all(done->wait);
435 * If thread->done, it means that this callback occurred
436 * after the parent thread has cleaned up. This can
437 * happen in the case that driver doesn't implement
438 * the terminate_all() functionality and a dma operation
439 * did not occur within the timeout period
441 WARN(1, "dmatest: Kernel memory may be corrupted!!\n");
445 static unsigned int min_odd(unsigned int x, unsigned int y)
447 unsigned int val = min(x, y);
449 return val % 2 ? val : val - 1;
452 static void result(const char *err, unsigned int n, unsigned int src_off,
453 unsigned int dst_off, unsigned int len, unsigned long data)
455 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
456 current->comm, n, err, src_off, dst_off, len, data);
459 static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
460 unsigned int dst_off, unsigned int len,
463 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
464 current->comm, n, err, src_off, dst_off, len, data);
467 #define verbose_result(err, n, src_off, dst_off, len, data) ({ \
469 result(err, n, src_off, dst_off, len, data); \
471 dbg_result(err, n, src_off, dst_off, len, data);\
474 static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
476 unsigned long long per_sec = 1000000;
481 /* drop precision until runtime is 32-bits */
482 while (runtime > UINT_MAX) {
488 per_sec = INT_TO_FIXPT(per_sec);
489 do_div(per_sec, runtime);
494 static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
496 return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10));
499 static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt)
503 for (i = 0; i < cnt; i++)
510 static void dmatest_free_test_data(struct dmatest_data *d)
512 __dmatest_free_test_data(d, d->cnt);
515 static int dmatest_alloc_test_data(struct dmatest_data *d,
516 unsigned int buf_size, u8 align)
520 d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
524 d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
528 for (i = 0; i < d->cnt; i++) {
529 d->raw[i] = kmalloc(buf_size + align, GFP_KERNEL);
533 /* align to alignment restriction */
535 d->aligned[i] = PTR_ALIGN(d->raw[i], align);
537 d->aligned[i] = d->raw[i];
542 __dmatest_free_test_data(d, i);
547 * This function repeatedly tests DMA transfers of various lengths and
548 * offsets for a given operation type until it is told to exit by
549 * kthread_stop(). There may be multiple threads running this function
550 * in parallel for a single channel, and there may be multiple channels
551 * being tested in parallel.
553 * Before each test, the source and destination buffer is initialized
554 * with a known pattern. This pattern is different depending on
555 * whether it's in an area which is supposed to be copied or
556 * overwritten, and different in the source and destination buffers.
557 * So if the DMA engine doesn't copy exactly what we tell it to copy,
560 static int dmatest_func(void *data)
562 struct dmatest_thread *thread = data;
563 struct dmatest_done *done = &thread->test_done;
564 struct dmatest_info *info;
565 struct dmatest_params *params;
566 struct dma_chan *chan;
567 struct dma_device *dev;
568 unsigned int error_count;
569 unsigned int failed_tests = 0;
570 unsigned int total_tests = 0;
572 enum dma_status status;
573 enum dma_ctrl_flags flags;
576 unsigned int buf_size;
577 struct dmatest_data *src;
578 struct dmatest_data *dst;
580 ktime_t ktime, start, diff;
581 ktime_t filltime = 0;
582 ktime_t comparetime = 0;
584 unsigned long long total_len = 0;
585 unsigned long long iops = 0;
587 bool is_memset = false;
596 thread->pending = false;
598 params = &info->params;
603 if (thread->type == DMA_MEMCPY) {
604 align = params->alignment < 0 ? dev->copy_align :
606 src->cnt = dst->cnt = 1;
607 } else if (thread->type == DMA_MEMSET) {
608 align = params->alignment < 0 ? dev->fill_align :
610 src->cnt = dst->cnt = 1;
612 } else if (thread->type == DMA_XOR) {
613 /* force odd to ensure dst = src */
614 src->cnt = min_odd(params->xor_sources | 1, dev->max_xor);
616 align = params->alignment < 0 ? dev->xor_align :
618 } else if (thread->type == DMA_PQ) {
619 /* force odd to ensure dst = src */
620 src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
622 align = params->alignment < 0 ? dev->pq_align :
625 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
627 goto err_thread_type;
629 for (i = 0; i < src->cnt; i++)
632 goto err_thread_type;
634 /* Check if buffer count fits into map count variable (u8) */
635 if ((src->cnt + dst->cnt) >= 255) {
636 pr_err("too many buffers (%d of 255 supported)\n",
637 src->cnt + dst->cnt);
641 buf_size = params->buf_size;
642 if (1 << align > buf_size) {
643 pr_err("%u-byte buffer too small for %d-byte alignment\n",
644 buf_size, 1 << align);
648 if (dmatest_alloc_test_data(src, buf_size, align) < 0)
651 if (dmatest_alloc_test_data(dst, buf_size, align) < 0)
654 set_user_nice(current, 10);
656 srcs = kcalloc(src->cnt, sizeof(dma_addr_t), GFP_KERNEL);
660 dma_pq = kcalloc(dst->cnt, sizeof(dma_addr_t), GFP_KERNEL);
665 * src and dst buffers are freed by ourselves below
668 flags = DMA_CTRL_ACK;
670 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
673 while (!(kthread_should_stop() ||
674 (params->iterations && total_tests >= params->iterations))) {
675 struct dma_async_tx_descriptor *tx = NULL;
676 struct dmaengine_unmap_data *um;
682 if (params->transfer_size) {
683 if (params->transfer_size >= buf_size) {
684 pr_err("%u-byte transfer size must be lower than %u-buffer size\n",
685 params->transfer_size, buf_size);
688 len = params->transfer_size;
689 } else if (params->norandom) {
692 len = dmatest_random() % buf_size + 1;
695 /* Do not alter transfer size explicitly defined by user */
696 if (!params->transfer_size) {
697 len = (len >> align) << align;
703 if (params->norandom) {
707 src->off = dmatest_random() % (buf_size - len + 1);
708 dst->off = dmatest_random() % (buf_size - len + 1);
710 src->off = (src->off >> align) << align;
711 dst->off = (dst->off >> align) << align;
714 if (!params->noverify) {
716 dmatest_init_srcs(src->aligned, src->off, len,
717 buf_size, is_memset);
718 dmatest_init_dsts(dst->aligned, dst->off, len,
719 buf_size, is_memset);
721 diff = ktime_sub(ktime_get(), start);
722 filltime = ktime_add(filltime, diff);
725 um = dmaengine_get_unmap_data(dev->dev, src->cnt + dst->cnt,
729 result("unmap data NULL", total_tests,
730 src->off, dst->off, len, ret);
735 for (i = 0; i < src->cnt; i++) {
736 void *buf = src->aligned[i];
737 struct page *pg = virt_to_page(buf);
738 unsigned long pg_off = offset_in_page(buf);
740 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
741 um->len, DMA_TO_DEVICE);
742 srcs[i] = um->addr[i] + src->off;
743 ret = dma_mapping_error(dev->dev, um->addr[i]);
745 result("src mapping error", total_tests,
746 src->off, dst->off, len, ret);
747 goto error_unmap_continue;
751 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
752 dsts = &um->addr[src->cnt];
753 for (i = 0; i < dst->cnt; i++) {
754 void *buf = dst->aligned[i];
755 struct page *pg = virt_to_page(buf);
756 unsigned long pg_off = offset_in_page(buf);
758 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
760 ret = dma_mapping_error(dev->dev, dsts[i]);
762 result("dst mapping error", total_tests,
763 src->off, dst->off, len, ret);
764 goto error_unmap_continue;
769 if (thread->type == DMA_MEMCPY)
770 tx = dev->device_prep_dma_memcpy(chan,
772 srcs[0], len, flags);
773 else if (thread->type == DMA_MEMSET)
774 tx = dev->device_prep_dma_memset(chan,
776 *(src->aligned[0] + src->off),
778 else if (thread->type == DMA_XOR)
779 tx = dev->device_prep_dma_xor(chan,
783 else if (thread->type == DMA_PQ) {
784 for (i = 0; i < dst->cnt; i++)
785 dma_pq[i] = dsts[i] + dst->off;
786 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
792 result("prep error", total_tests, src->off,
795 goto error_unmap_continue;
799 if (!params->polled) {
800 tx->callback = dmatest_callback;
801 tx->callback_param = done;
803 cookie = tx->tx_submit(tx);
805 if (dma_submit_error(cookie)) {
806 result("submit error", total_tests, src->off,
809 goto error_unmap_continue;
812 if (params->polled) {
813 status = dma_sync_wait(chan, cookie);
814 dmaengine_terminate_sync(chan);
815 if (status == DMA_COMPLETE)
818 dma_async_issue_pending(chan);
820 wait_event_freezable_timeout(thread->done_wait,
822 msecs_to_jiffies(params->timeout));
824 status = dma_async_is_tx_complete(chan, cookie, NULL,
829 result("test timed out", total_tests, src->off, dst->off,
831 goto error_unmap_continue;
832 } else if (status != DMA_COMPLETE) {
833 result(status == DMA_ERROR ?
834 "completion error status" :
835 "completion busy status", total_tests, src->off,
837 goto error_unmap_continue;
840 dmaengine_unmap_put(um);
842 if (params->noverify) {
843 verbose_result("test passed", total_tests, src->off,
849 pr_debug("%s: verifying source buffer...\n", current->comm);
850 error_count = dmatest_verify(src->aligned, 0, src->off,
851 0, PATTERN_SRC, true, is_memset);
852 error_count += dmatest_verify(src->aligned, src->off,
853 src->off + len, src->off,
854 PATTERN_SRC | PATTERN_COPY, true, is_memset);
855 error_count += dmatest_verify(src->aligned, src->off + len,
856 buf_size, src->off + len,
857 PATTERN_SRC, true, is_memset);
859 pr_debug("%s: verifying dest buffer...\n", current->comm);
860 error_count += dmatest_verify(dst->aligned, 0, dst->off,
861 0, PATTERN_DST, false, is_memset);
863 error_count += dmatest_verify(dst->aligned, dst->off,
864 dst->off + len, src->off,
865 PATTERN_SRC | PATTERN_COPY, false, is_memset);
867 error_count += dmatest_verify(dst->aligned, dst->off + len,
868 buf_size, dst->off + len,
869 PATTERN_DST, false, is_memset);
871 diff = ktime_sub(ktime_get(), start);
872 comparetime = ktime_add(comparetime, diff);
875 result("data error", total_tests, src->off, dst->off,
879 verbose_result("test passed", total_tests, src->off,
885 error_unmap_continue:
886 dmaengine_unmap_put(um);
889 ktime = ktime_sub(ktime_get(), ktime);
890 ktime = ktime_sub(ktime, comparetime);
891 ktime = ktime_sub(ktime, filltime);
892 runtime = ktime_to_us(ktime);
899 dmatest_free_test_data(dst);
901 dmatest_free_test_data(src);
905 iops = dmatest_persec(runtime, total_tests);
906 pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n",
907 current->comm, total_tests, failed_tests,
908 FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops),
909 dmatest_KBs(runtime, total_len), ret);
911 /* terminate all transfers on specified channels */
912 if (ret || failed_tests)
913 dmaengine_terminate_sync(chan);
916 wake_up(&thread_wait);
921 static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
923 struct dmatest_thread *thread;
924 struct dmatest_thread *_thread;
927 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
928 ret = kthread_stop(thread->task);
929 pr_debug("thread %s exited with status %d\n",
930 thread->task->comm, ret);
931 list_del(&thread->node);
932 put_task_struct(thread->task);
936 /* terminate all transfers on specified channels */
937 dmaengine_terminate_sync(dtc->chan);
942 static int dmatest_add_threads(struct dmatest_info *info,
943 struct dmatest_chan *dtc, enum dma_transaction_type type)
945 struct dmatest_params *params = &info->params;
946 struct dmatest_thread *thread;
947 struct dma_chan *chan = dtc->chan;
951 if (type == DMA_MEMCPY)
953 else if (type == DMA_MEMSET)
955 else if (type == DMA_XOR)
957 else if (type == DMA_PQ)
962 for (i = 0; i < params->threads_per_chan; i++) {
963 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
965 pr_warn("No memory for %s-%s%u\n",
966 dma_chan_name(chan), op, i);
970 thread->chan = dtc->chan;
972 thread->test_done.wait = &thread->done_wait;
973 init_waitqueue_head(&thread->done_wait);
975 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
976 dma_chan_name(chan), op, i);
977 if (IS_ERR(thread->task)) {
978 pr_warn("Failed to create thread %s-%s%u\n",
979 dma_chan_name(chan), op, i);
984 /* srcbuf and dstbuf are allocated by the thread itself */
985 get_task_struct(thread->task);
986 list_add_tail(&thread->node, &dtc->threads);
987 thread->pending = true;
993 static int dmatest_add_channel(struct dmatest_info *info,
994 struct dma_chan *chan)
996 struct dmatest_chan *dtc;
997 struct dma_device *dma_dev = chan->device;
998 unsigned int thread_count = 0;
1001 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
1003 pr_warn("No memory for %s\n", dma_chan_name(chan));
1008 INIT_LIST_HEAD(&dtc->threads);
1010 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1012 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
1013 thread_count += cnt > 0 ? cnt : 0;
1017 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1019 cnt = dmatest_add_threads(info, dtc, DMA_MEMSET);
1020 thread_count += cnt > 0 ? cnt : 0;
1024 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1025 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
1026 thread_count += cnt > 0 ? cnt : 0;
1028 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1029 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
1030 thread_count += cnt > 0 ? cnt : 0;
1033 pr_info("Added %u threads using %s\n",
1034 thread_count, dma_chan_name(chan));
1036 list_add_tail(&dtc->node, &info->channels);
1037 info->nr_channels++;
1042 static bool filter(struct dma_chan *chan, void *param)
1044 struct dmatest_params *params = param;
1046 if (!dmatest_match_channel(params, chan) ||
1047 !dmatest_match_device(params, chan->device))
1053 static void request_channels(struct dmatest_info *info,
1054 enum dma_transaction_type type)
1056 dma_cap_mask_t mask;
1059 dma_cap_set(type, mask);
1061 struct dmatest_params *params = &info->params;
1062 struct dma_chan *chan;
1064 chan = dma_request_channel(mask, filter, params);
1066 if (dmatest_add_channel(info, chan)) {
1067 dma_release_channel(chan);
1068 break; /* add_channel failed, punt */
1071 break; /* no more channels available */
1072 if (params->max_channels &&
1073 info->nr_channels >= params->max_channels)
1074 break; /* we have all we need */
1078 static void add_threaded_test(struct dmatest_info *info)
1080 struct dmatest_params *params = &info->params;
1082 /* Copy test parameters */
1083 params->buf_size = test_buf_size;
1084 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
1085 strlcpy(params->device, strim(test_device), sizeof(params->device));
1086 params->threads_per_chan = threads_per_chan;
1087 params->max_channels = max_channels;
1088 params->iterations = iterations;
1089 params->xor_sources = xor_sources;
1090 params->pq_sources = pq_sources;
1091 params->timeout = timeout;
1092 params->noverify = noverify;
1093 params->norandom = norandom;
1094 params->alignment = alignment;
1095 params->transfer_size = transfer_size;
1096 params->polled = polled;
1098 request_channels(info, DMA_MEMCPY);
1099 request_channels(info, DMA_MEMSET);
1100 request_channels(info, DMA_XOR);
1101 request_channels(info, DMA_PQ);
1104 static void run_pending_tests(struct dmatest_info *info)
1106 struct dmatest_chan *dtc;
1107 unsigned int thread_count = 0;
1109 list_for_each_entry(dtc, &info->channels, node) {
1110 struct dmatest_thread *thread;
1113 list_for_each_entry(thread, &dtc->threads, node) {
1114 wake_up_process(thread->task);
1117 pr_info("Started %u threads using %s\n",
1118 thread_count, dma_chan_name(dtc->chan));
1122 static void stop_threaded_test(struct dmatest_info *info)
1124 struct dmatest_chan *dtc, *_dtc;
1125 struct dma_chan *chan;
1127 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
1128 list_del(&dtc->node);
1130 dmatest_cleanup_channel(dtc);
1131 pr_debug("dropped channel %s\n", dma_chan_name(chan));
1132 dma_release_channel(chan);
1135 info->nr_channels = 0;
1138 static void start_threaded_tests(struct dmatest_info *info)
1140 /* we might be called early to set run=, defer running until all
1141 * parameters have been evaluated
1143 if (!info->did_init)
1146 run_pending_tests(info);
1149 static int dmatest_run_get(char *val, const struct kernel_param *kp)
1151 struct dmatest_info *info = &test_info;
1153 mutex_lock(&info->lock);
1154 if (is_threaded_test_run(info)) {
1157 if (!is_threaded_test_pending(info))
1158 stop_threaded_test(info);
1159 dmatest_run = false;
1161 mutex_unlock(&info->lock);
1163 return param_get_bool(val, kp);
1166 static int dmatest_run_set(const char *val, const struct kernel_param *kp)
1168 struct dmatest_info *info = &test_info;
1171 mutex_lock(&info->lock);
1172 ret = param_set_bool(val, kp);
1174 mutex_unlock(&info->lock);
1176 } else if (dmatest_run) {
1177 if (!is_threaded_test_pending(info)) {
1178 pr_info("No channels configured, continue with any\n");
1179 add_threaded_test(info);
1181 start_threaded_tests(info);
1183 stop_threaded_test(info);
1186 mutex_unlock(&info->lock);
1191 static int dmatest_chan_set(const char *val, const struct kernel_param *kp)
1193 struct dmatest_info *info = &test_info;
1194 struct dmatest_chan *dtc;
1195 char chan_reset_val[20];
1198 mutex_lock(&info->lock);
1199 ret = param_set_copystring(val, kp);
1201 mutex_unlock(&info->lock);
1204 /*Clear any previously run threads */
1205 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info))
1206 stop_threaded_test(info);
1207 /* Reject channels that are already registered */
1208 if (is_threaded_test_pending(info)) {
1209 list_for_each_entry(dtc, &info->channels, node) {
1210 if (strcmp(dma_chan_name(dtc->chan),
1211 strim(test_channel)) == 0) {
1212 dtc = list_last_entry(&info->channels,
1213 struct dmatest_chan,
1215 strlcpy(chan_reset_val,
1216 dma_chan_name(dtc->chan),
1217 sizeof(chan_reset_val));
1224 add_threaded_test(info);
1226 /* Check if channel was added successfully */
1227 dtc = list_last_entry(&info->channels, struct dmatest_chan, node);
1231 * if new channel was not successfully added, revert the
1232 * "test_channel" string to the name of the last successfully
1233 * added channel. exception for when users issues empty string
1234 * to channel parameter.
1236 if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0)
1237 && (strcmp("", strim(test_channel)) != 0)) {
1239 strlcpy(chan_reset_val, dma_chan_name(dtc->chan),
1240 sizeof(chan_reset_val));
1245 /* Clear test_channel if no channels were added successfully */
1246 strlcpy(chan_reset_val, "", sizeof(chan_reset_val));
1251 mutex_unlock(&info->lock);
1256 param_set_copystring(chan_reset_val, kp);
1257 mutex_unlock(&info->lock);
1262 static int dmatest_chan_get(char *val, const struct kernel_param *kp)
1264 struct dmatest_info *info = &test_info;
1266 mutex_lock(&info->lock);
1267 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) {
1268 stop_threaded_test(info);
1269 strlcpy(test_channel, "", sizeof(test_channel));
1271 mutex_unlock(&info->lock);
1273 return param_get_string(val, kp);
1276 static int dmatest_test_list_get(char *val, const struct kernel_param *kp)
1278 struct dmatest_info *info = &test_info;
1279 struct dmatest_chan *dtc;
1280 unsigned int thread_count = 0;
1282 list_for_each_entry(dtc, &info->channels, node) {
1283 struct dmatest_thread *thread;
1286 list_for_each_entry(thread, &dtc->threads, node) {
1289 pr_info("%u threads using %s\n",
1290 thread_count, dma_chan_name(dtc->chan));
1296 static int __init dmatest_init(void)
1298 struct dmatest_info *info = &test_info;
1299 struct dmatest_params *params = &info->params;
1302 mutex_lock(&info->lock);
1303 add_threaded_test(info);
1304 run_pending_tests(info);
1305 mutex_unlock(&info->lock);
1308 if (params->iterations && wait)
1309 wait_event(thread_wait, !is_threaded_test_run(info));
1311 /* module parameters are stable, inittime tests are started,
1312 * let userspace take over 'run' control
1314 info->did_init = true;
1318 /* when compiled-in wait for drivers to load first */
1319 late_initcall(dmatest_init);
1321 static void __exit dmatest_exit(void)
1323 struct dmatest_info *info = &test_info;
1325 mutex_lock(&info->lock);
1326 stop_threaded_test(info);
1327 mutex_unlock(&info->lock);
1329 module_exit(dmatest_exit);
1331 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1332 MODULE_LICENSE("GPL v2");