1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
5 * Copyright (C) 2014 Atmel Corporation
7 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
10 #include <asm/barrier.h>
11 #include <dt-bindings/dma/at91.h>
12 #include <linux/clk.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dmapool.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/module.h>
20 #include <linux/of_dma.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
25 #include "dmaengine.h"
27 /* Global registers */
28 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
29 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
30 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
31 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
32 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
33 #define AT_XDMAC_WRHP(i) (((i) & 0xF) << 4)
34 #define AT_XDMAC_WRMP(i) (((i) & 0xF) << 8)
35 #define AT_XDMAC_WRLP(i) (((i) & 0xF) << 12)
36 #define AT_XDMAC_RDHP(i) (((i) & 0xF) << 16)
37 #define AT_XDMAC_RDMP(i) (((i) & 0xF) << 20)
38 #define AT_XDMAC_RDLP(i) (((i) & 0xF) << 24)
39 #define AT_XDMAC_RDSG(i) (((i) & 0xF) << 28)
40 #define AT_XDMAC_GCFG_M2M (AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF))
41 #define AT_XDMAC_GCFG_P2M (AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \
43 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
44 #define AT_XDMAC_PW0(i) (((i) & 0xF) << 0)
45 #define AT_XDMAC_PW1(i) (((i) & 0xF) << 4)
46 #define AT_XDMAC_PW2(i) (((i) & 0xF) << 8)
47 #define AT_XDMAC_PW3(i) (((i) & 0xF) << 12)
48 #define AT_XDMAC_GWAC_M2M 0
49 #define AT_XDMAC_GWAC_P2M (AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF))
51 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
52 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
53 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
54 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
55 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
56 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
57 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
58 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
60 /* Channel relative registers offsets */
61 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
62 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
63 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
64 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
65 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
66 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
67 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
68 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
69 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
70 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
71 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
72 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
73 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
74 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
75 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
76 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
77 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
78 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
79 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
80 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
81 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
82 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
83 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
84 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
85 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
86 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
87 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
88 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
89 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
90 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
91 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
92 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
93 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
94 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
95 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
96 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
97 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
98 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
99 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
100 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
101 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
102 #define AT_XDMAC_CNDC_NDVIEW_MASK GENMASK(28, 27)
103 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131 #define AT_XDMAC_CC_DWIDTH_OFFSET 11
132 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136 #define AT_XDMAC_CC_DWIDTH_WORD 0x2
137 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159 #define AT_XDMAC_CC_PERID(i) ((0x7f & (i)) << 24) /* Channel Peripheral Identifier */
160 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
164 /* Microblock control members */
165 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
166 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
167 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
168 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
169 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
170 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
171 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
172 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
174 #define AT_XDMAC_MAX_CHAN 0x20
175 #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */
176 #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */
177 #define AT_XDMAC_RESIDUE_MAX_RETRIES 5
179 #define AT_XDMAC_DMA_BUSWIDTHS\
180 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
181 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
182 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
183 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
184 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
187 AT_XDMAC_CHAN_IS_CYCLIC = 0,
188 AT_XDMAC_CHAN_IS_PAUSED,
191 struct at_xdmac_layout {
192 /* Global Channel Read Suspend Register */
194 /* Global Write Suspend Register */
196 /* Global Channel Read Write Suspend Register */
198 /* Global Channel Read Write Resume Register */
200 /* Global Channel Software Request Register */
202 /* Global channel Software Request Status Register */
204 /* Global Channel Software Flush Request Register */
206 /* Channel reg base */
208 /* Source/Destination Interface must be specified or not */
210 /* AXI queue priority configuration supported */
214 /* ----- Channels ----- */
215 struct at_xdmac_chan {
216 struct dma_chan chan;
217 void __iomem *ch_regs;
218 u32 mask; /* Channel Mask */
219 u32 cfg; /* Channel Configuration Register */
220 u8 perid; /* Peripheral ID */
221 u8 perif; /* Peripheral Interface */
222 u8 memif; /* Memory Interface */
228 unsigned long status;
229 struct tasklet_struct tasklet;
230 struct dma_slave_config sconfig;
234 struct list_head xfers_list;
235 struct list_head free_descs_list;
239 /* ----- Controller ----- */
241 struct dma_device dma;
246 struct dma_pool *at_xdmac_desc_pool;
247 const struct at_xdmac_layout *layout;
248 struct at_xdmac_chan chan[];
252 /* ----- Descriptors ----- */
254 /* Linked List Descriptor */
255 struct at_xdmac_lld {
256 u32 mbr_nda; /* Next Descriptor Member */
257 u32 mbr_ubc; /* Microblock Control Member */
258 u32 mbr_sa; /* Source Address Member */
259 u32 mbr_da; /* Destination Address Member */
260 u32 mbr_cfg; /* Configuration Register */
261 u32 mbr_bc; /* Block Control Register */
262 u32 mbr_ds; /* Data Stride Register */
263 u32 mbr_sus; /* Source Microblock Stride Register */
264 u32 mbr_dus; /* Destination Microblock Stride Register */
267 /* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */
268 struct at_xdmac_desc {
269 struct at_xdmac_lld lld;
270 enum dma_transfer_direction direction;
271 struct dma_async_tx_descriptor tx_dma_desc;
272 struct list_head desc_node;
273 /* Following members are only used by the first descriptor */
275 unsigned int xfer_size;
276 struct list_head descs_list;
277 struct list_head xfer_node;
278 } __aligned(sizeof(u64));
280 static const struct at_xdmac_layout at_xdmac_sama5d4_layout = {
288 .chan_cc_reg_base = 0x50,
293 static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {
301 .chan_cc_reg_base = 0x60,
306 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
308 return atxdmac->regs + (atxdmac->layout->chan_cc_reg_base + chan_nb * 0x40);
311 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
312 #define at_xdmac_write(atxdmac, reg, value) \
313 writel_relaxed((value), (atxdmac)->regs + (reg))
315 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
316 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
318 static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
320 return container_of(dchan, struct at_xdmac_chan, chan);
323 static struct device *chan2dev(struct dma_chan *chan)
325 return &chan->dev->device;
328 static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
330 return container_of(ddev, struct at_xdmac, dma);
333 static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
335 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
338 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
340 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
343 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
345 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
348 static inline bool at_xdmac_chan_is_peripheral_xfer(u32 cfg)
350 return cfg & AT_XDMAC_CC_TYPE_PER_TRAN;
353 static inline u8 at_xdmac_get_dwidth(u32 cfg)
355 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
358 static unsigned int init_nr_desc_per_channel = 64;
359 module_param(init_nr_desc_per_channel, uint, 0644);
360 MODULE_PARM_DESC(init_nr_desc_per_channel,
361 "initial descriptors per channel (default: 64)");
364 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
366 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
369 static void at_xdmac_off(struct at_xdmac *atxdmac)
371 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
373 /* Wait that all chans are disabled. */
374 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
377 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
380 /* Call with lock hold. */
381 static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
382 struct at_xdmac_desc *first)
384 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
387 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
389 /* Set transfer as active to not try to start it again. */
390 first->active_xfer = true;
392 /* Tell xdmac where to get the first descriptor. */
393 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys);
394 if (atxdmac->layout->sdif)
395 reg |= AT_XDMAC_CNDA_NDAIF(atchan->memif);
397 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
400 * When doing non cyclic transfer we need to use the next
401 * descriptor view 2 since some fields of the configuration register
402 * depend on transfer size and src/dest addresses.
404 if (at_xdmac_chan_is_cyclic(atchan))
405 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
406 else if ((first->lld.mbr_ubc &
407 AT_XDMAC_CNDC_NDVIEW_MASK) == AT_XDMAC_MBR_UBC_NDV3)
408 reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
410 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
412 * Even if the register will be updated from the configuration in the
413 * descriptor when using view 2 or higher, the PROT bit won't be set
414 * properly. This bit can be modified only by using the channel
415 * configuration register.
417 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
419 reg |= AT_XDMAC_CNDC_NDDUP
420 | AT_XDMAC_CNDC_NDSUP
422 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
424 dev_vdbg(chan2dev(&atchan->chan),
425 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
426 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
427 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
428 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
429 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
430 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
431 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
433 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
434 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE;
436 * Request Overflow Error is only for peripheral synchronized transfers
438 if (at_xdmac_chan_is_peripheral_xfer(first->lld.mbr_cfg))
439 reg |= AT_XDMAC_CIE_ROIE;
442 * There is no end of list when doing cyclic dma, we need to get
443 * an interrupt after each periods.
445 if (at_xdmac_chan_is_cyclic(atchan))
446 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
447 reg | AT_XDMAC_CIE_BIE);
449 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
450 reg | AT_XDMAC_CIE_LIE);
451 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
452 dev_vdbg(chan2dev(&atchan->chan),
453 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
455 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
457 dev_vdbg(chan2dev(&atchan->chan),
458 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
459 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
460 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
461 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
462 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
463 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
464 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
468 static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
470 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
471 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
473 unsigned long irqflags;
475 spin_lock_irqsave(&atchan->lock, irqflags);
476 cookie = dma_cookie_assign(tx);
478 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
479 spin_unlock_irqrestore(&atchan->lock, irqflags);
481 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
482 __func__, atchan, desc);
487 static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
490 struct at_xdmac_desc *desc;
491 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
494 desc = dma_pool_zalloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
496 INIT_LIST_HEAD(&desc->descs_list);
497 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
498 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
499 desc->tx_dma_desc.phys = phys;
505 static void at_xdmac_init_used_desc(struct at_xdmac_desc *desc)
507 memset(&desc->lld, 0, sizeof(desc->lld));
508 INIT_LIST_HEAD(&desc->descs_list);
509 desc->direction = DMA_TRANS_NONE;
511 desc->active_xfer = false;
514 /* Call must be protected by lock. */
515 static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
517 struct at_xdmac_desc *desc;
519 if (list_empty(&atchan->free_descs_list)) {
520 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
522 desc = list_first_entry(&atchan->free_descs_list,
523 struct at_xdmac_desc, desc_node);
524 list_del(&desc->desc_node);
525 at_xdmac_init_used_desc(desc);
531 static void at_xdmac_queue_desc(struct dma_chan *chan,
532 struct at_xdmac_desc *prev,
533 struct at_xdmac_desc *desc)
538 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
539 prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE;
541 dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
542 __func__, prev, &prev->lld.mbr_nda);
545 static inline void at_xdmac_increment_block_count(struct dma_chan *chan,
546 struct at_xdmac_desc *desc)
553 dev_dbg(chan2dev(chan),
554 "%s: incrementing the block count of the desc 0x%p\n",
558 static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
559 struct of_dma *of_dma)
561 struct at_xdmac *atxdmac = of_dma->of_dma_data;
562 struct at_xdmac_chan *atchan;
563 struct dma_chan *chan;
564 struct device *dev = atxdmac->dma.dev;
566 if (dma_spec->args_count != 1) {
567 dev_err(dev, "dma phandler args: bad number of args\n");
571 chan = dma_get_any_slave_channel(&atxdmac->dma);
573 dev_err(dev, "can't get a dma channel\n");
577 atchan = to_at_xdmac_chan(chan);
578 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
579 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
580 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
581 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
582 atchan->memif, atchan->perif, atchan->perid);
587 static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
588 enum dma_transfer_direction direction)
590 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
591 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
594 if (direction == DMA_DEV_TO_MEM) {
596 AT91_XDMAC_DT_PERID(atchan->perid)
597 | AT_XDMAC_CC_DAM_INCREMENTED_AM
598 | AT_XDMAC_CC_SAM_FIXED_AM
599 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
600 | AT_XDMAC_CC_DSYNC_PER2MEM
601 | AT_XDMAC_CC_MBSIZE_SIXTEEN
602 | AT_XDMAC_CC_TYPE_PER_TRAN;
603 if (atxdmac->layout->sdif)
604 atchan->cfg |= AT_XDMAC_CC_DIF(atchan->memif) |
605 AT_XDMAC_CC_SIF(atchan->perif);
607 csize = ffs(atchan->sconfig.src_maxburst) - 1;
609 dev_err(chan2dev(chan), "invalid src maxburst value\n");
612 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
613 dwidth = ffs(atchan->sconfig.src_addr_width) - 1;
615 dev_err(chan2dev(chan), "invalid src addr width value\n");
618 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
619 } else if (direction == DMA_MEM_TO_DEV) {
621 AT91_XDMAC_DT_PERID(atchan->perid)
622 | AT_XDMAC_CC_DAM_FIXED_AM
623 | AT_XDMAC_CC_SAM_INCREMENTED_AM
624 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
625 | AT_XDMAC_CC_DSYNC_MEM2PER
626 | AT_XDMAC_CC_MBSIZE_SIXTEEN
627 | AT_XDMAC_CC_TYPE_PER_TRAN;
628 if (atxdmac->layout->sdif)
629 atchan->cfg |= AT_XDMAC_CC_DIF(atchan->perif) |
630 AT_XDMAC_CC_SIF(atchan->memif);
632 csize = ffs(atchan->sconfig.dst_maxburst) - 1;
634 dev_err(chan2dev(chan), "invalid src maxburst value\n");
637 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
638 dwidth = ffs(atchan->sconfig.dst_addr_width) - 1;
640 dev_err(chan2dev(chan), "invalid dst addr width value\n");
643 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
646 dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg);
652 * Only check that maxburst and addr width values are supported by the
653 * the controller but not that the configuration is good to perform the
654 * transfer since we don't know the direction at this stage.
656 static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig)
658 if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE)
659 || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE))
662 if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH)
663 || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH))
669 static int at_xdmac_set_slave_config(struct dma_chan *chan,
670 struct dma_slave_config *sconfig)
672 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
674 if (at_xdmac_check_slave_config(sconfig)) {
675 dev_err(chan2dev(chan), "invalid slave configuration\n");
679 memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig));
684 static struct dma_async_tx_descriptor *
685 at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
686 unsigned int sg_len, enum dma_transfer_direction direction,
687 unsigned long flags, void *context)
689 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
690 struct at_xdmac_desc *first = NULL, *prev = NULL;
691 struct scatterlist *sg;
693 unsigned int xfer_size = 0;
694 unsigned long irqflags;
695 struct dma_async_tx_descriptor *ret = NULL;
700 if (!is_slave_direction(direction)) {
701 dev_err(chan2dev(chan), "invalid DMA direction\n");
705 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
707 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
710 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
711 spin_lock_irqsave(&atchan->lock, irqflags);
713 if (at_xdmac_compute_chan_conf(chan, direction))
716 /* Prepare descriptors. */
717 for_each_sg(sgl, sg, sg_len, i) {
718 struct at_xdmac_desc *desc = NULL;
719 u32 len, mem, dwidth, fixed_dwidth;
721 len = sg_dma_len(sg);
722 mem = sg_dma_address(sg);
723 if (unlikely(!len)) {
724 dev_err(chan2dev(chan), "sg data length is zero\n");
727 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
728 __func__, i, len, mem);
730 desc = at_xdmac_get_desc(atchan);
732 dev_err(chan2dev(chan), "can't get descriptor\n");
734 list_splice_tail_init(&first->descs_list,
735 &atchan->free_descs_list);
739 /* Linked list descriptor setup. */
740 if (direction == DMA_DEV_TO_MEM) {
741 desc->lld.mbr_sa = atchan->sconfig.src_addr;
742 desc->lld.mbr_da = mem;
744 desc->lld.mbr_sa = mem;
745 desc->lld.mbr_da = atchan->sconfig.dst_addr;
747 dwidth = at_xdmac_get_dwidth(atchan->cfg);
748 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
750 : AT_XDMAC_CC_DWIDTH_BYTE;
751 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
752 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
753 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
754 | (len >> fixed_dwidth); /* microblock length */
755 desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
756 AT_XDMAC_CC_DWIDTH(fixed_dwidth);
757 dev_dbg(chan2dev(chan),
758 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
759 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
763 at_xdmac_queue_desc(chan, prev, desc);
769 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
770 __func__, desc, first);
771 list_add_tail(&desc->desc_node, &first->descs_list);
776 first->tx_dma_desc.flags = flags;
777 first->xfer_size = xfer_size;
778 first->direction = direction;
779 ret = &first->tx_dma_desc;
782 spin_unlock_irqrestore(&atchan->lock, irqflags);
786 static struct dma_async_tx_descriptor *
787 at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
788 size_t buf_len, size_t period_len,
789 enum dma_transfer_direction direction,
792 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
793 struct at_xdmac_desc *first = NULL, *prev = NULL;
794 unsigned int periods = buf_len / period_len;
796 unsigned long irqflags;
798 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
799 __func__, &buf_addr, buf_len, period_len,
800 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
802 if (!is_slave_direction(direction)) {
803 dev_err(chan2dev(chan), "invalid DMA direction\n");
807 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
808 dev_err(chan2dev(chan), "channel currently used\n");
812 if (at_xdmac_compute_chan_conf(chan, direction))
815 for (i = 0; i < periods; i++) {
816 struct at_xdmac_desc *desc = NULL;
818 spin_lock_irqsave(&atchan->lock, irqflags);
819 desc = at_xdmac_get_desc(atchan);
821 dev_err(chan2dev(chan), "can't get descriptor\n");
823 list_splice_tail_init(&first->descs_list,
824 &atchan->free_descs_list);
825 spin_unlock_irqrestore(&atchan->lock, irqflags);
828 spin_unlock_irqrestore(&atchan->lock, irqflags);
829 dev_dbg(chan2dev(chan),
830 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
831 __func__, desc, &desc->tx_dma_desc.phys);
833 if (direction == DMA_DEV_TO_MEM) {
834 desc->lld.mbr_sa = atchan->sconfig.src_addr;
835 desc->lld.mbr_da = buf_addr + i * period_len;
837 desc->lld.mbr_sa = buf_addr + i * period_len;
838 desc->lld.mbr_da = atchan->sconfig.dst_addr;
840 desc->lld.mbr_cfg = atchan->cfg;
841 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
842 | AT_XDMAC_MBR_UBC_NDEN
843 | AT_XDMAC_MBR_UBC_NSEN
844 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
846 dev_dbg(chan2dev(chan),
847 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
848 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
852 at_xdmac_queue_desc(chan, prev, desc);
858 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
859 __func__, desc, first);
860 list_add_tail(&desc->desc_node, &first->descs_list);
863 at_xdmac_queue_desc(chan, prev, first);
864 first->tx_dma_desc.flags = flags;
865 first->xfer_size = buf_len;
866 first->direction = direction;
868 return &first->tx_dma_desc;
871 static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr)
876 * Check address alignment to select the greater data width we
879 * Some XDMAC implementations don't provide dword transfer, in
880 * this case selecting dword has the same behavior as
881 * selecting word transfers.
884 width = AT_XDMAC_CC_DWIDTH_DWORD;
885 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
886 } else if (!(addr & 3)) {
887 width = AT_XDMAC_CC_DWIDTH_WORD;
888 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
889 } else if (!(addr & 1)) {
890 width = AT_XDMAC_CC_DWIDTH_HALFWORD;
891 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
893 width = AT_XDMAC_CC_DWIDTH_BYTE;
894 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
900 static struct at_xdmac_desc *
901 at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
902 struct at_xdmac_chan *atchan,
903 struct at_xdmac_desc *prev,
904 dma_addr_t src, dma_addr_t dst,
905 struct dma_interleaved_template *xt,
906 struct data_chunk *chunk)
908 struct at_xdmac_desc *desc;
913 * WARNING: The channel configuration is set here since there is no
914 * dmaengine_slave_config call in this case. Moreover we don't know the
915 * direction, it involves we can't dynamically set the source and dest
916 * interface so we have to use the same one. Only interface 0 allows EBI
917 * access. Hopefully we can access DDR through both ports (at least on
918 * SAMA5D4x), so we can use the same interface for source and dest,
919 * that solves the fact we don't know the direction.
920 * ERRATA: Even if useless for memory transfers, the PERID has to not
921 * match the one of another channel. If not, it could lead to spurious
923 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
924 * Thus, no need to have the SIF/DIF interfaces here.
925 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
928 u32 chan_cc = AT_XDMAC_CC_PERID(0x7f)
929 | AT_XDMAC_CC_MBSIZE_SIXTEEN
930 | AT_XDMAC_CC_TYPE_MEM_TRAN;
932 dwidth = at_xdmac_align_width(chan, src | dst | chunk->size);
933 if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
934 dev_dbg(chan2dev(chan),
935 "%s: chunk too big (%zu, max size %lu)...\n",
936 __func__, chunk->size,
937 AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth);
942 dev_dbg(chan2dev(chan),
943 "Adding items at the end of desc 0x%p\n", prev);
947 chan_cc |= AT_XDMAC_CC_SAM_UBS_AM;
949 chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM;
954 chan_cc |= AT_XDMAC_CC_DAM_UBS_AM;
956 chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM;
959 spin_lock_irqsave(&atchan->lock, flags);
960 desc = at_xdmac_get_desc(atchan);
961 spin_unlock_irqrestore(&atchan->lock, flags);
963 dev_err(chan2dev(chan), "can't get descriptor\n");
967 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
969 ublen = chunk->size >> dwidth;
971 desc->lld.mbr_sa = src;
972 desc->lld.mbr_da = dst;
973 desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk);
974 desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk);
976 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
977 | AT_XDMAC_MBR_UBC_NDEN
978 | AT_XDMAC_MBR_UBC_NSEN
980 desc->lld.mbr_cfg = chan_cc;
982 dev_dbg(chan2dev(chan),
983 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
984 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da,
985 desc->lld.mbr_ubc, desc->lld.mbr_cfg);
989 at_xdmac_queue_desc(chan, prev, desc);
994 static struct dma_async_tx_descriptor *
995 at_xdmac_prep_interleaved(struct dma_chan *chan,
996 struct dma_interleaved_template *xt,
999 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1000 struct at_xdmac_desc *prev = NULL, *first = NULL;
1001 dma_addr_t dst_addr, src_addr;
1002 size_t src_skip = 0, dst_skip = 0, len = 0;
1003 struct data_chunk *chunk;
1006 if (!xt || !xt->numf || (xt->dir != DMA_MEM_TO_MEM))
1010 * TODO: Handle the case where we have to repeat a chain of
1013 if ((xt->numf > 1) && (xt->frame_size > 1))
1016 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, numf=%zu, frame_size=%zu, flags=0x%lx\n",
1017 __func__, &xt->src_start, &xt->dst_start, xt->numf,
1018 xt->frame_size, flags);
1020 src_addr = xt->src_start;
1021 dst_addr = xt->dst_start;
1024 first = at_xdmac_interleaved_queue_desc(chan, atchan,
1029 /* Length of the block is (BLEN+1) microblocks. */
1030 for (i = 0; i < xt->numf - 1; i++)
1031 at_xdmac_increment_block_count(chan, first);
1033 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1034 __func__, first, first);
1035 list_add_tail(&first->desc_node, &first->descs_list);
1037 for (i = 0; i < xt->frame_size; i++) {
1038 size_t src_icg = 0, dst_icg = 0;
1039 struct at_xdmac_desc *desc;
1041 chunk = xt->sgl + i;
1043 dst_icg = dmaengine_get_dst_icg(xt, chunk);
1044 src_icg = dmaengine_get_src_icg(xt, chunk);
1046 src_skip = chunk->size + src_icg;
1047 dst_skip = chunk->size + dst_icg;
1049 dev_dbg(chan2dev(chan),
1050 "%s: chunk size=%zu, src icg=%zu, dst icg=%zu\n",
1051 __func__, chunk->size, src_icg, dst_icg);
1053 desc = at_xdmac_interleaved_queue_desc(chan, atchan,
1058 list_splice_tail_init(&first->descs_list,
1059 &atchan->free_descs_list);
1066 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1067 __func__, desc, first);
1068 list_add_tail(&desc->desc_node, &first->descs_list);
1071 src_addr += src_skip;
1074 dst_addr += dst_skip;
1081 first->tx_dma_desc.cookie = -EBUSY;
1082 first->tx_dma_desc.flags = flags;
1083 first->xfer_size = len;
1085 return &first->tx_dma_desc;
1088 static struct dma_async_tx_descriptor *
1089 at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1090 size_t len, unsigned long flags)
1092 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1093 struct at_xdmac_desc *first = NULL, *prev = NULL;
1094 size_t remaining_size = len, xfer_size = 0, ublen;
1095 dma_addr_t src_addr = src, dst_addr = dest;
1098 * WARNING: We don't know the direction, it involves we can't
1099 * dynamically set the source and dest interface so we have to use the
1100 * same one. Only interface 0 allows EBI access. Hopefully we can
1101 * access DDR through both ports (at least on SAMA5D4x), so we can use
1102 * the same interface for source and dest, that solves the fact we
1103 * don't know the direction.
1104 * ERRATA: Even if useless for memory transfers, the PERID has to not
1105 * match the one of another channel. If not, it could lead to spurious
1107 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
1108 * Thus, no need to have the SIF/DIF interfaces here.
1109 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
1112 u32 chan_cc = AT_XDMAC_CC_PERID(0x7f)
1113 | AT_XDMAC_CC_DAM_INCREMENTED_AM
1114 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1115 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1116 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1117 unsigned long irqflags;
1119 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
1120 __func__, &src, &dest, len, flags);
1125 dwidth = at_xdmac_align_width(chan, src_addr | dst_addr);
1127 /* Prepare descriptors. */
1128 while (remaining_size) {
1129 struct at_xdmac_desc *desc = NULL;
1131 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
1133 spin_lock_irqsave(&atchan->lock, irqflags);
1134 desc = at_xdmac_get_desc(atchan);
1135 spin_unlock_irqrestore(&atchan->lock, irqflags);
1137 dev_err(chan2dev(chan), "can't get descriptor\n");
1139 list_splice_tail_init(&first->descs_list,
1140 &atchan->free_descs_list);
1144 /* Update src and dest addresses. */
1145 src_addr += xfer_size;
1146 dst_addr += xfer_size;
1148 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
1149 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
1151 xfer_size = remaining_size;
1153 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
1155 /* Check remaining length and change data width if needed. */
1156 dwidth = at_xdmac_align_width(chan,
1157 src_addr | dst_addr | xfer_size);
1158 chan_cc &= ~AT_XDMAC_CC_DWIDTH_MASK;
1159 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1161 ublen = xfer_size >> dwidth;
1162 remaining_size -= xfer_size;
1164 desc->lld.mbr_sa = src_addr;
1165 desc->lld.mbr_da = dst_addr;
1166 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
1167 | AT_XDMAC_MBR_UBC_NDEN
1168 | AT_XDMAC_MBR_UBC_NSEN
1170 desc->lld.mbr_cfg = chan_cc;
1172 dev_dbg(chan2dev(chan),
1173 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1174 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
1178 at_xdmac_queue_desc(chan, prev, desc);
1184 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1185 __func__, desc, first);
1186 list_add_tail(&desc->desc_node, &first->descs_list);
1189 first->tx_dma_desc.flags = flags;
1190 first->xfer_size = len;
1192 return &first->tx_dma_desc;
1195 static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
1196 struct at_xdmac_chan *atchan,
1197 dma_addr_t dst_addr,
1201 struct at_xdmac_desc *desc;
1202 unsigned long flags;
1206 * WARNING: The channel configuration is set here since there is no
1207 * dmaengine_slave_config call in this case. Moreover we don't know the
1208 * direction, it involves we can't dynamically set the source and dest
1209 * interface so we have to use the same one. Only interface 0 allows EBI
1210 * access. Hopefully we can access DDR through both ports (at least on
1211 * SAMA5D4x), so we can use the same interface for source and dest,
1212 * that solves the fact we don't know the direction.
1213 * ERRATA: Even if useless for memory transfers, the PERID has to not
1214 * match the one of another channel. If not, it could lead to spurious
1216 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
1217 * Thus, no need to have the SIF/DIF interfaces here.
1218 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
1221 u32 chan_cc = AT_XDMAC_CC_PERID(0x7f)
1222 | AT_XDMAC_CC_DAM_UBS_AM
1223 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1224 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1225 | AT_XDMAC_CC_MEMSET_HW_MODE
1226 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1228 dwidth = at_xdmac_align_width(chan, dst_addr);
1230 if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
1231 dev_err(chan2dev(chan),
1232 "%s: Transfer too large, aborting...\n",
1237 spin_lock_irqsave(&atchan->lock, flags);
1238 desc = at_xdmac_get_desc(atchan);
1239 spin_unlock_irqrestore(&atchan->lock, flags);
1241 dev_err(chan2dev(chan), "can't get descriptor\n");
1245 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1247 ublen = len >> dwidth;
1249 desc->lld.mbr_da = dst_addr;
1250 desc->lld.mbr_ds = value;
1251 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
1252 | AT_XDMAC_MBR_UBC_NDEN
1253 | AT_XDMAC_MBR_UBC_NSEN
1255 desc->lld.mbr_cfg = chan_cc;
1257 dev_dbg(chan2dev(chan),
1258 "%s: lld: mbr_da=%pad, mbr_ds=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1259 __func__, &desc->lld.mbr_da, desc->lld.mbr_ds, desc->lld.mbr_ubc,
1265 static struct dma_async_tx_descriptor *
1266 at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
1267 size_t len, unsigned long flags)
1269 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1270 struct at_xdmac_desc *desc;
1272 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%zu, pattern=0x%x, flags=0x%lx\n",
1273 __func__, &dest, len, value, flags);
1278 desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value);
1279 list_add_tail(&desc->desc_node, &desc->descs_list);
1281 desc->tx_dma_desc.cookie = -EBUSY;
1282 desc->tx_dma_desc.flags = flags;
1283 desc->xfer_size = len;
1285 return &desc->tx_dma_desc;
1288 static struct dma_async_tx_descriptor *
1289 at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl,
1290 unsigned int sg_len, int value,
1291 unsigned long flags)
1293 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1294 struct at_xdmac_desc *desc, *pdesc = NULL,
1295 *ppdesc = NULL, *first = NULL;
1296 struct scatterlist *sg, *psg = NULL, *ppsg = NULL;
1297 size_t stride = 0, pstride = 0, len = 0;
1303 dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n",
1304 __func__, sg_len, value, flags);
1306 /* Prepare descriptors. */
1307 for_each_sg(sgl, sg, sg_len, i) {
1308 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n",
1309 __func__, &sg_dma_address(sg), sg_dma_len(sg),
1311 desc = at_xdmac_memset_create_desc(chan, atchan,
1316 list_splice_tail_init(&first->descs_list,
1317 &atchan->free_descs_list);
1322 /* Update our strides */
1325 stride = sg_dma_address(sg) -
1326 (sg_dma_address(psg) + sg_dma_len(psg));
1329 * The scatterlist API gives us only the address and
1330 * length of each elements.
1332 * Unfortunately, we don't have the stride, which we
1333 * will need to compute.
1335 * That make us end up in a situation like this one:
1336 * len stride len stride len
1337 * +-------+ +-------+ +-------+
1338 * | N-2 | | N-1 | | N |
1339 * +-------+ +-------+ +-------+
1341 * We need all these three elements (N-2, N-1 and N)
1342 * to actually take the decision on whether we need to
1343 * queue N-1 or reuse N-2.
1345 * We will only consider N if it is the last element.
1347 if (ppdesc && pdesc) {
1348 if ((stride == pstride) &&
1349 (sg_dma_len(ppsg) == sg_dma_len(psg))) {
1350 dev_dbg(chan2dev(chan),
1351 "%s: desc 0x%p can be merged with desc 0x%p\n",
1352 __func__, pdesc, ppdesc);
1355 * Increment the block count of the
1358 at_xdmac_increment_block_count(chan, ppdesc);
1359 ppdesc->lld.mbr_dus = stride;
1362 * Put back the N-1 descriptor in the
1363 * free descriptor list
1365 list_add_tail(&pdesc->desc_node,
1366 &atchan->free_descs_list);
1369 * Make our N-1 descriptor pointer
1370 * point to the N-2 since they were
1376 * Rule out the case where we don't have
1377 * pstride computed yet (our second sg
1380 * We also want to catch the case where there
1381 * would be a negative stride,
1383 } else if (pstride ||
1384 sg_dma_address(sg) < sg_dma_address(psg)) {
1386 * Queue the N-1 descriptor after the
1389 at_xdmac_queue_desc(chan, ppdesc, pdesc);
1392 * Add the N-1 descriptor to the list
1393 * of the descriptors used for this
1396 list_add_tail(&desc->desc_node,
1397 &first->descs_list);
1398 dev_dbg(chan2dev(chan),
1399 "%s: add desc 0x%p to descs_list 0x%p\n",
1400 __func__, desc, first);
1405 * If we are the last element, just see if we have the
1406 * same size than the previous element.
1408 * If so, we can merge it with the previous descriptor
1409 * since we don't care about the stride anymore.
1411 if ((i == (sg_len - 1)) &&
1412 sg_dma_len(psg) == sg_dma_len(sg)) {
1413 dev_dbg(chan2dev(chan),
1414 "%s: desc 0x%p can be merged with desc 0x%p\n",
1415 __func__, desc, pdesc);
1418 * Increment the block count of the N-1
1421 at_xdmac_increment_block_count(chan, pdesc);
1422 pdesc->lld.mbr_dus = stride;
1425 * Put back the N descriptor in the free
1428 list_add_tail(&desc->desc_node,
1429 &atchan->free_descs_list);
1432 /* Update our descriptors */
1436 /* Update our scatter pointers */
1440 len += sg_dma_len(sg);
1443 first->tx_dma_desc.cookie = -EBUSY;
1444 first->tx_dma_desc.flags = flags;
1445 first->xfer_size = len;
1447 return &first->tx_dma_desc;
1450 static enum dma_status
1451 at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1452 struct dma_tx_state *txstate)
1454 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1455 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1456 struct at_xdmac_desc *desc, *_desc, *iter;
1457 struct list_head *descs_list;
1458 enum dma_status ret;
1460 u32 cur_nda, check_nda, cur_ubc, mask, value;
1462 unsigned long flags;
1465 ret = dma_cookie_status(chan, cookie, txstate);
1466 if (ret == DMA_COMPLETE)
1472 spin_lock_irqsave(&atchan->lock, flags);
1474 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1477 * If the transfer has not been started yet, don't need to compute the
1478 * residue, it's the transfer length.
1480 if (!desc->active_xfer) {
1481 dma_set_residue(txstate, desc->xfer_size);
1485 residue = desc->xfer_size;
1487 * Flush FIFO: only relevant when the transfer is source peripheral
1488 * synchronized. Flush is needed before reading CUBC because data in
1489 * the FIFO are not reported by CUBC. Reporting a residue of the
1490 * transfer length while we have data in FIFO can cause issue.
1491 * Usecase: atmel USART has a timeout which means I have received
1492 * characters but there is no more character received for a while. On
1493 * timeout, it requests the residue. If the data are in the DMA FIFO,
1494 * we will return a residue of the transfer length. It means no data
1495 * received. If an application is waiting for these data, it will hang
1496 * since we won't have another USART timeout without receiving new
1499 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
1500 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
1501 if ((desc->lld.mbr_cfg & mask) == value) {
1502 at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);
1503 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1508 * The easiest way to compute the residue should be to pause the DMA
1509 * but doing this can lead to miss some data as some devices don't
1511 * We need to read several registers because:
1512 * - DMA is running therefore a descriptor change is possible while
1513 * reading these registers
1514 * - When the block transfer is done, the value of the CUBC register
1515 * is set to its initial value until the fetch of the next descriptor.
1516 * This value will corrupt the residue calculation so we have to skip
1519 * INITD -------- ------------
1520 * |____________________|
1521 * _______________________ _______________
1522 * NDA @desc2 \/ @desc3
1523 * _______________________/\_______________
1524 * __________ ___________ _______________
1525 * CUBC 0 \/ MAX desc1 \/ MAX desc2
1526 * __________/\___________/\_______________
1528 * Since descriptors are aligned on 64 bits, we can assume that
1529 * the update of NDA and CUBC is atomic.
1530 * Memory barriers are used to ensure the read order of the registers.
1531 * A max number of retries is set because unlikely it could never ends.
1533 for (retry = 0; retry < AT_XDMAC_RESIDUE_MAX_RETRIES; retry++) {
1534 check_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1536 cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC);
1538 initd = !!(at_xdmac_chan_read(atchan, AT_XDMAC_CC) & AT_XDMAC_CC_INITD);
1540 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1543 if ((check_nda == cur_nda) && initd)
1547 if (unlikely(retry >= AT_XDMAC_RESIDUE_MAX_RETRIES)) {
1553 * Flush FIFO: only relevant when the transfer is source peripheral
1554 * synchronized. Another flush is needed here because CUBC is updated
1555 * when the controller sends the data write command. It can lead to
1556 * report data that are not written in the memory or the device. The
1557 * FIFO flush ensures that data are really written.
1559 if ((desc->lld.mbr_cfg & mask) == value) {
1560 at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);
1561 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1566 * Remove size of all microblocks already transferred and the current
1567 * one. Then add the remaining size to transfer of the current
1570 descs_list = &desc->descs_list;
1571 list_for_each_entry_safe(iter, _desc, descs_list, desc_node) {
1572 dwidth = at_xdmac_get_dwidth(iter->lld.mbr_cfg);
1573 residue -= (iter->lld.mbr_ubc & 0xffffff) << dwidth;
1574 if ((iter->lld.mbr_nda & 0xfffffffc) == cur_nda) {
1579 residue += cur_ubc << dwidth;
1581 dma_set_residue(txstate, residue);
1583 dev_dbg(chan2dev(chan),
1584 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
1585 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
1588 spin_unlock_irqrestore(&atchan->lock, flags);
1592 static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
1594 struct at_xdmac_desc *desc;
1597 * If channel is enabled, do nothing, advance_work will be triggered
1598 * after the interruption.
1600 if (at_xdmac_chan_is_enabled(atchan) || list_empty(&atchan->xfers_list))
1603 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc,
1605 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1606 if (!desc->active_xfer)
1607 at_xdmac_start_xfer(atchan, desc);
1610 static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
1612 struct at_xdmac_desc *desc;
1613 struct dma_async_tx_descriptor *txd;
1615 spin_lock_irq(&atchan->lock);
1616 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08x\n",
1617 __func__, atchan->irq_status);
1618 if (list_empty(&atchan->xfers_list)) {
1619 spin_unlock_irq(&atchan->lock);
1622 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc,
1624 spin_unlock_irq(&atchan->lock);
1625 txd = &desc->tx_dma_desc;
1626 if (txd->flags & DMA_PREP_INTERRUPT)
1627 dmaengine_desc_get_callback_invoke(txd, NULL);
1630 /* Called with atchan->lock held. */
1631 static void at_xdmac_handle_error(struct at_xdmac_chan *atchan)
1633 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1634 struct at_xdmac_desc *bad_desc;
1637 * The descriptor currently at the head of the active list is
1638 * broken. Since we don't have any way to report errors, we'll
1639 * just have to scream loudly and try to continue with other
1640 * descriptors queued (if any).
1642 if (atchan->irq_status & AT_XDMAC_CIS_RBEIS)
1643 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1644 if (atchan->irq_status & AT_XDMAC_CIS_WBEIS)
1645 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1646 if (atchan->irq_status & AT_XDMAC_CIS_ROIS)
1647 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1649 /* Channel must be disabled first as it's not done automatically */
1650 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1651 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1654 bad_desc = list_first_entry(&atchan->xfers_list,
1655 struct at_xdmac_desc,
1658 /* Print bad descriptor's details if needed */
1659 dev_dbg(chan2dev(&atchan->chan),
1660 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
1661 __func__, &bad_desc->lld.mbr_sa, &bad_desc->lld.mbr_da,
1662 bad_desc->lld.mbr_ubc);
1664 /* Then continue with usual descriptor management */
1667 static void at_xdmac_tasklet(struct tasklet_struct *t)
1669 struct at_xdmac_chan *atchan = from_tasklet(atchan, t, tasklet);
1670 struct at_xdmac_desc *desc;
1671 struct dma_async_tx_descriptor *txd;
1674 if (at_xdmac_chan_is_cyclic(atchan))
1675 return at_xdmac_handle_cyclic(atchan);
1677 error_mask = AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS |
1680 spin_lock_irq(&atchan->lock);
1682 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08x\n",
1683 __func__, atchan->irq_status);
1685 if (!(atchan->irq_status & AT_XDMAC_CIS_LIS) &&
1686 !(atchan->irq_status & error_mask)) {
1687 spin_unlock_irq(&atchan->lock);
1691 if (atchan->irq_status & error_mask)
1692 at_xdmac_handle_error(atchan);
1694 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc,
1696 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1697 if (!desc->active_xfer) {
1698 dev_err(chan2dev(&atchan->chan), "Xfer not active: exiting");
1699 spin_unlock_irq(&atchan->lock);
1703 txd = &desc->tx_dma_desc;
1704 dma_cookie_complete(txd);
1705 /* Remove the transfer from the transfer list. */
1706 list_del(&desc->xfer_node);
1707 spin_unlock_irq(&atchan->lock);
1709 if (txd->flags & DMA_PREP_INTERRUPT)
1710 dmaengine_desc_get_callback_invoke(txd, NULL);
1712 dma_run_dependencies(txd);
1714 spin_lock_irq(&atchan->lock);
1715 /* Move the xfer descriptors into the free descriptors list. */
1716 list_splice_tail_init(&desc->descs_list, &atchan->free_descs_list);
1717 at_xdmac_advance_work(atchan);
1718 spin_unlock_irq(&atchan->lock);
1721 static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1723 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1724 struct at_xdmac_chan *atchan;
1725 u32 imr, status, pending;
1726 u32 chan_imr, chan_status;
1727 int i, ret = IRQ_NONE;
1730 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1731 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1732 pending = status & imr;
1734 dev_vdbg(atxdmac->dma.dev,
1735 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1736 __func__, status, imr, pending);
1741 /* We have to find which channel has generated the interrupt. */
1742 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1743 if (!((1 << i) & pending))
1746 atchan = &atxdmac->chan[i];
1747 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1748 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1749 atchan->irq_status = chan_status & chan_imr;
1750 dev_vdbg(atxdmac->dma.dev,
1751 "%s: chan%d: imr=0x%x, status=0x%x\n",
1752 __func__, i, chan_imr, chan_status);
1753 dev_vdbg(chan2dev(&atchan->chan),
1754 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1756 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1757 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1758 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1759 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1760 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1761 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1763 if (atchan->irq_status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1764 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1766 tasklet_schedule(&atchan->tasklet);
1775 static void at_xdmac_issue_pending(struct dma_chan *chan)
1777 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1778 unsigned long flags;
1780 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1782 spin_lock_irqsave(&atchan->lock, flags);
1783 at_xdmac_advance_work(atchan);
1784 spin_unlock_irqrestore(&atchan->lock, flags);
1789 static int at_xdmac_device_config(struct dma_chan *chan,
1790 struct dma_slave_config *config)
1792 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1794 unsigned long flags;
1796 dev_dbg(chan2dev(chan), "%s\n", __func__);
1798 spin_lock_irqsave(&atchan->lock, flags);
1799 ret = at_xdmac_set_slave_config(chan, config);
1800 spin_unlock_irqrestore(&atchan->lock, flags);
1805 static int at_xdmac_device_pause(struct dma_chan *chan)
1807 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1808 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1809 unsigned long flags;
1811 dev_dbg(chan2dev(chan), "%s\n", __func__);
1813 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1816 spin_lock_irqsave(&atchan->lock, flags);
1817 at_xdmac_write(atxdmac, atxdmac->layout->grws, atchan->mask);
1818 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1819 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1821 spin_unlock_irqrestore(&atchan->lock, flags);
1826 static int at_xdmac_device_resume(struct dma_chan *chan)
1828 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1829 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1830 unsigned long flags;
1832 dev_dbg(chan2dev(chan), "%s\n", __func__);
1834 spin_lock_irqsave(&atchan->lock, flags);
1835 if (!at_xdmac_chan_is_paused(atchan)) {
1836 spin_unlock_irqrestore(&atchan->lock, flags);
1840 at_xdmac_write(atxdmac, atxdmac->layout->grwr, atchan->mask);
1841 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1842 spin_unlock_irqrestore(&atchan->lock, flags);
1847 static int at_xdmac_device_terminate_all(struct dma_chan *chan)
1849 struct at_xdmac_desc *desc, *_desc;
1850 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1851 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1852 unsigned long flags;
1854 dev_dbg(chan2dev(chan), "%s\n", __func__);
1856 spin_lock_irqsave(&atchan->lock, flags);
1857 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1858 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1861 /* Cancel all pending transfers. */
1862 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) {
1863 list_del(&desc->xfer_node);
1864 list_splice_tail_init(&desc->descs_list,
1865 &atchan->free_descs_list);
1868 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1869 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
1870 spin_unlock_irqrestore(&atchan->lock, flags);
1875 static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1877 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1878 struct at_xdmac_desc *desc;
1881 if (at_xdmac_chan_is_enabled(atchan)) {
1882 dev_err(chan2dev(chan),
1883 "can't allocate channel resources (channel enabled)\n");
1887 if (!list_empty(&atchan->free_descs_list)) {
1888 dev_err(chan2dev(chan),
1889 "can't allocate channel resources (channel not free from a previous use)\n");
1893 for (i = 0; i < init_nr_desc_per_channel; i++) {
1894 desc = at_xdmac_alloc_desc(chan, GFP_KERNEL);
1896 dev_warn(chan2dev(chan),
1897 "only %d descriptors have been allocated\n", i);
1900 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1903 dma_cookie_init(chan);
1905 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1910 static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1912 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1913 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1914 struct at_xdmac_desc *desc, *_desc;
1916 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1917 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1918 list_del(&desc->desc_node);
1919 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1925 static void at_xdmac_axi_config(struct platform_device *pdev)
1927 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
1928 bool dev_m2m = false;
1931 if (!atxdmac->layout->axi_config)
1932 return; /* Not supported */
1934 if (!of_property_read_u32(pdev->dev.of_node, "dma-requests",
1936 dev_info(&pdev->dev, "controller in mem2mem mode.\n");
1941 at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M);
1942 at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M);
1944 at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M);
1945 at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M);
1949 static int __maybe_unused atmel_xdmac_prepare(struct device *dev)
1951 struct at_xdmac *atxdmac = dev_get_drvdata(dev);
1952 struct dma_chan *chan, *_chan;
1954 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1955 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1957 /* Wait for transfer completion, except in cyclic case. */
1958 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1964 static int __maybe_unused atmel_xdmac_suspend(struct device *dev)
1966 struct at_xdmac *atxdmac = dev_get_drvdata(dev);
1967 struct dma_chan *chan, *_chan;
1969 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1970 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1972 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
1973 if (at_xdmac_chan_is_cyclic(atchan)) {
1974 if (!at_xdmac_chan_is_paused(atchan))
1975 at_xdmac_device_pause(chan);
1976 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1977 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1978 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1981 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1983 at_xdmac_off(atxdmac);
1984 clk_disable_unprepare(atxdmac->clk);
1988 static int __maybe_unused atmel_xdmac_resume(struct device *dev)
1990 struct at_xdmac *atxdmac = dev_get_drvdata(dev);
1991 struct at_xdmac_chan *atchan;
1992 struct dma_chan *chan, *_chan;
1993 struct platform_device *pdev = container_of(dev, struct platform_device, dev);
1997 ret = clk_prepare_enable(atxdmac->clk);
2001 at_xdmac_axi_config(pdev);
2003 /* Clear pending interrupts. */
2004 for (i = 0; i < atxdmac->dma.chancnt; i++) {
2005 atchan = &atxdmac->chan[i];
2006 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
2010 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
2011 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2012 atchan = to_at_xdmac_chan(chan);
2013 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
2014 if (at_xdmac_chan_is_cyclic(atchan)) {
2015 if (at_xdmac_chan_is_paused(atchan))
2016 at_xdmac_device_resume(chan);
2017 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
2018 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
2019 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
2021 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
2027 static int at_xdmac_probe(struct platform_device *pdev)
2029 struct at_xdmac *atxdmac;
2030 int irq, nr_channels, i, ret;
2034 irq = platform_get_irq(pdev, 0);
2038 base = devm_platform_ioremap_resource(pdev, 0);
2040 return PTR_ERR(base);
2043 * Read number of xdmac channels, read helper function can't be used
2044 * since atxdmac is not yet allocated and we need to know the number
2045 * of channels to do the allocation.
2047 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
2048 nr_channels = AT_XDMAC_NB_CH(reg);
2049 if (nr_channels > AT_XDMAC_MAX_CHAN) {
2050 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
2055 atxdmac = devm_kzalloc(&pdev->dev,
2056 struct_size(atxdmac, chan, nr_channels),
2059 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
2063 atxdmac->regs = base;
2066 atxdmac->layout = of_device_get_match_data(&pdev->dev);
2067 if (!atxdmac->layout)
2070 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
2071 if (IS_ERR(atxdmac->clk)) {
2072 dev_err(&pdev->dev, "can't get dma_clk\n");
2073 return PTR_ERR(atxdmac->clk);
2076 /* Do not use dev res to prevent races with tasklet */
2077 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
2079 dev_err(&pdev->dev, "can't request irq\n");
2083 ret = clk_prepare_enable(atxdmac->clk);
2085 dev_err(&pdev->dev, "can't prepare or enable clock\n");
2089 atxdmac->at_xdmac_desc_pool =
2090 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
2091 sizeof(struct at_xdmac_desc), 4, 0);
2092 if (!atxdmac->at_xdmac_desc_pool) {
2093 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
2095 goto err_clk_disable;
2098 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
2099 dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
2100 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
2101 dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask);
2102 dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask);
2103 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
2105 * Without DMA_PRIVATE the driver is not able to allocate more than
2106 * one channel, second allocation fails in private_candidate.
2108 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
2109 atxdmac->dma.dev = &pdev->dev;
2110 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
2111 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
2112 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
2113 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
2114 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
2115 atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
2116 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
2117 atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset;
2118 atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg;
2119 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
2120 atxdmac->dma.device_config = at_xdmac_device_config;
2121 atxdmac->dma.device_pause = at_xdmac_device_pause;
2122 atxdmac->dma.device_resume = at_xdmac_device_resume;
2123 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
2124 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
2125 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
2126 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2127 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2129 /* Disable all chans and interrupts. */
2130 at_xdmac_off(atxdmac);
2132 /* Init channels. */
2133 INIT_LIST_HEAD(&atxdmac->dma.channels);
2134 for (i = 0; i < nr_channels; i++) {
2135 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2137 atchan->chan.device = &atxdmac->dma;
2138 list_add_tail(&atchan->chan.device_node,
2139 &atxdmac->dma.channels);
2141 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
2142 atchan->mask = 1 << i;
2144 spin_lock_init(&atchan->lock);
2145 INIT_LIST_HEAD(&atchan->xfers_list);
2146 INIT_LIST_HEAD(&atchan->free_descs_list);
2147 tasklet_setup(&atchan->tasklet, at_xdmac_tasklet);
2149 /* Clear pending interrupts. */
2150 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
2153 platform_set_drvdata(pdev, atxdmac);
2155 ret = dma_async_device_register(&atxdmac->dma);
2157 dev_err(&pdev->dev, "fail to register DMA engine device\n");
2158 goto err_clk_disable;
2161 ret = of_dma_controller_register(pdev->dev.of_node,
2162 at_xdmac_xlate, atxdmac);
2164 dev_err(&pdev->dev, "could not register of dma controller\n");
2165 goto err_dma_unregister;
2168 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
2169 nr_channels, atxdmac->regs);
2171 at_xdmac_axi_config(pdev);
2176 dma_async_device_unregister(&atxdmac->dma);
2178 clk_disable_unprepare(atxdmac->clk);
2180 free_irq(atxdmac->irq, atxdmac);
2184 static int at_xdmac_remove(struct platform_device *pdev)
2186 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
2189 at_xdmac_off(atxdmac);
2190 of_dma_controller_free(pdev->dev.of_node);
2191 dma_async_device_unregister(&atxdmac->dma);
2192 clk_disable_unprepare(atxdmac->clk);
2194 free_irq(atxdmac->irq, atxdmac);
2196 for (i = 0; i < atxdmac->dma.chancnt; i++) {
2197 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2199 tasklet_kill(&atchan->tasklet);
2200 at_xdmac_free_chan_resources(&atchan->chan);
2206 static const struct dev_pm_ops __maybe_unused atmel_xdmac_dev_pm_ops = {
2207 .prepare = atmel_xdmac_prepare,
2208 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
2211 static const struct of_device_id atmel_xdmac_dt_ids[] = {
2213 .compatible = "atmel,sama5d4-dma",
2214 .data = &at_xdmac_sama5d4_layout,
2216 .compatible = "microchip,sama7g5-dma",
2217 .data = &at_xdmac_sama7g5_layout,
2222 MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
2224 static struct platform_driver at_xdmac_driver = {
2225 .probe = at_xdmac_probe,
2226 .remove = at_xdmac_remove,
2229 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
2230 .pm = pm_ptr(&atmel_xdmac_dev_pm_ops),
2234 static int __init at_xdmac_init(void)
2236 return platform_driver_register(&at_xdmac_driver);
2238 subsys_initcall(at_xdmac_init);
2240 static void __exit at_xdmac_exit(void)
2242 platform_driver_unregister(&at_xdmac_driver);
2244 module_exit(at_xdmac_exit);
2246 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
2247 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
2248 MODULE_LICENSE("GPL");