2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the
23 * file called COPYING.
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
75 * - Break out common code from arch/arm/mach-s3c64xx and share
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/dmapool.h>
83 #include <linux/dmaengine.h>
84 #include <linux/amba/bus.h>
85 #include <linux/amba/pl08x.h>
86 #include <linux/debugfs.h>
87 #include <linux/seq_file.h>
89 #include <asm/hardware/pl080.h>
91 #define DRIVER_NAME "pl08xdmac"
94 * struct vendor_data - vendor-specific config parameters
95 * for PL08x derivatives
96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters
106 * PL08X private data structures
107 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
108 * start & end do not - their bus bit info is in cctl.
118 * struct pl08x_driver_data - the local state holder for the PL08x
119 * @slave: slave engine for this instance
120 * @memcpy: memcpy engine for this instance
121 * @base: virtual memory base (remapped) for the PL08x
122 * @adev: the corresponding AMBA (PrimeCell) bus entry
123 * @vd: vendor data for this PL08x variant
124 * @pd: platform data passed in from the platform/machine
125 * @phy_chans: array of data for the physical channels
126 * @pool: a pool for the LLI descriptors
127 * @pool_ctr: counter of LLIs in the pool
128 * @lock: a spinlock for this struct
130 struct pl08x_driver_data {
131 struct dma_device slave;
132 struct dma_device memcpy;
134 struct amba_device *adev;
135 const struct vendor_data *vd;
136 struct pl08x_platform_data *pd;
137 struct pl08x_phy_chan *phy_chans;
138 struct dma_pool *pool;
144 * PL08X specific defines
148 * Memory boundaries: the manual for PL08x says that the controller
149 * cannot read past a 1KiB boundary, so these defines are used to
150 * create transfer LLIs that do not cross such boundaries.
152 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
153 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
155 /* Minimum period between work queue runs */
156 #define PL08X_WQ_PERIODMIN 20
158 /* Size (bytes) of each LLI buffer allocated for one transfer */
159 # define PL08X_LLI_TSFR_SIZE 0x2000
161 /* Maximum times we call dma_pool_alloc on this pool without freeing */
162 #define PL08X_MAX_ALLOCS 0x40
163 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct lli))
164 #define PL08X_ALIGN 8
166 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
168 return container_of(chan, struct pl08x_dma_chan, chan);
172 * Physical channel handling
175 /* Whether a certain channel is busy or not */
176 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
180 val = readl(ch->base + PL080_CH_CONFIG);
181 return val & PL080_CONFIG_ACTIVE;
185 * Set the initial DMA register values i.e. those for the first LLI
186 * The next LLI pointer and the configuration interrupt bit have
187 * been set when the LLIs were constructed
189 static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
190 struct pl08x_phy_chan *ch)
192 /* Wait for channel inactive */
193 while (pl08x_phy_channel_busy(ch))
196 dev_vdbg(&pl08x->adev->dev,
197 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
198 "cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n",
206 writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
207 writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
208 writel(ch->clli, ch->base + PL080_CH_LLI);
209 writel(ch->cctl, ch->base + PL080_CH_CONTROL);
210 writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
213 static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
215 struct pl08x_channel_data *cd = plchan->cd;
216 struct pl08x_phy_chan *phychan = plchan->phychan;
217 struct pl08x_txd *txd = plchan->at;
219 /* Copy the basic control register calculated at transfer config */
220 phychan->csrc = txd->csrc;
221 phychan->cdst = txd->cdst;
222 phychan->clli = txd->clli;
223 phychan->cctl = txd->cctl;
225 /* Assign the signal to the proper control registers */
226 phychan->ccfg = cd->ccfg;
227 phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
228 phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
229 /* If it wasn't set from AMBA, ignore it */
230 if (txd->direction == DMA_TO_DEVICE)
231 /* Select signal as destination */
233 (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
234 else if (txd->direction == DMA_FROM_DEVICE)
235 /* Select signal as source */
237 (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
238 /* Always enable error interrupts */
239 phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
240 /* Always enable terminal interrupts */
241 phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
245 * Enable the DMA channel
246 * Assumes all other configuration bits have been set
247 * as desired before this code is called
249 static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
250 struct pl08x_phy_chan *ch)
255 * Do not access config register until channel shows as disabled
257 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
261 * Do not access config register until channel shows as inactive
263 val = readl(ch->base + PL080_CH_CONFIG);
264 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
265 val = readl(ch->base + PL080_CH_CONFIG);
267 writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
271 * Overall DMAC remains enabled always.
273 * Disabling individual channels could lose data.
275 * Disable the peripheral DMA after disabling the DMAC
276 * in order to allow the DMAC FIFO to drain, and
277 * hence allow the channel to show inactive
280 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
284 /* Set the HALT bit and wait for the FIFO to drain */
285 val = readl(ch->base + PL080_CH_CONFIG);
286 val |= PL080_CONFIG_HALT;
287 writel(val, ch->base + PL080_CH_CONFIG);
289 /* Wait for channel inactive */
290 while (pl08x_phy_channel_busy(ch))
294 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
298 /* Clear the HALT bit */
299 val = readl(ch->base + PL080_CH_CONFIG);
300 val &= ~PL080_CONFIG_HALT;
301 writel(val, ch->base + PL080_CH_CONFIG);
305 /* Stops the channel */
306 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
310 pl08x_pause_phy_chan(ch);
312 /* Disable channel */
313 val = readl(ch->base + PL080_CH_CONFIG);
314 val &= ~PL080_CONFIG_ENABLE;
315 val &= ~PL080_CONFIG_ERR_IRQ_MASK;
316 val &= ~PL080_CONFIG_TC_IRQ_MASK;
317 writel(val, ch->base + PL080_CH_CONFIG);
320 static inline u32 get_bytes_in_cctl(u32 cctl)
322 /* The source width defines the number of bytes */
323 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
325 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
326 case PL080_WIDTH_8BIT:
328 case PL080_WIDTH_16BIT:
331 case PL080_WIDTH_32BIT:
338 /* The channel should be paused when calling this */
339 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
341 struct pl08x_phy_chan *ch;
342 struct pl08x_txd *txdi = NULL;
343 struct pl08x_txd *txd;
347 spin_lock_irqsave(&plchan->lock, flags);
349 ch = plchan->phychan;
353 * Next follow the LLIs to get the number of pending bytes in the
354 * currently active transaction.
357 struct lli *llis_va = txd->llis_va;
358 struct lli *llis_bus = (struct lli *) txd->llis_bus;
359 u32 clli = readl(ch->base + PL080_CH_LLI);
361 /* First get the bytes in the current active LLI */
362 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
367 /* Forward to the LLI pointed to by clli */
368 while ((clli != (u32) &(llis_bus[i])) &&
369 (i < MAX_NUM_TSFR_LLIS))
373 bytes += get_bytes_in_cctl(llis_va[i].cctl);
375 * A LLI pointer of 0 terminates the LLI list
377 clli = llis_va[i].next;
383 /* Sum up all queued transactions */
384 if (!list_empty(&plchan->desc_list)) {
385 list_for_each_entry(txdi, &plchan->desc_list, node) {
391 spin_unlock_irqrestore(&plchan->lock, flags);
397 * Allocate a physical channel for a virtual channel
399 static struct pl08x_phy_chan *
400 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
401 struct pl08x_dma_chan *virt_chan)
403 struct pl08x_phy_chan *ch = NULL;
408 * Try to locate a physical channel to be used for
409 * this transfer. If all are taken return NULL and
410 * the requester will have to cope by using some fallback
411 * PIO mode or retrying later.
413 for (i = 0; i < pl08x->vd->channels; i++) {
414 ch = &pl08x->phy_chans[i];
416 spin_lock_irqsave(&ch->lock, flags);
419 ch->serving = virt_chan;
421 spin_unlock_irqrestore(&ch->lock, flags);
425 spin_unlock_irqrestore(&ch->lock, flags);
428 if (i == pl08x->vd->channels) {
429 /* No physical channel available, cope with it */
436 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
437 struct pl08x_phy_chan *ch)
441 /* Stop the channel and clear its interrupts */
442 pl08x_stop_phy_chan(ch);
443 writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
444 writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
446 /* Mark it as free */
447 spin_lock_irqsave(&ch->lock, flags);
449 spin_unlock_irqrestore(&ch->lock, flags);
456 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
459 case PL080_WIDTH_8BIT:
461 case PL080_WIDTH_16BIT:
463 case PL080_WIDTH_32BIT:
472 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
477 /* Remove all src, dst and transfer size bits */
478 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
479 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
480 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
482 /* Then set the bits according to the parameters */
485 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
488 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
491 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
500 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
503 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
506 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
513 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
518 * Autoselect a master bus to use for the transfer
519 * this prefers the destination bus if both available
520 * if fixed address on one bus the other will be chosen
522 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
523 struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
524 struct pl08x_bus_data **sbus, u32 cctl)
526 if (!(cctl & PL080_CONTROL_DST_INCR)) {
529 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
533 if (dst_bus->buswidth == 4) {
536 } else if (src_bus->buswidth == 4) {
539 } else if (dst_bus->buswidth == 2) {
542 } else if (src_bus->buswidth == 2) {
546 /* src_bus->buswidth == 1 */
554 * Fills in one LLI for a certain transfer descriptor
555 * and advance the counter
557 static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
558 struct pl08x_txd *txd, int num_llis, int len,
559 u32 cctl, u32 *remainder)
561 struct lli *llis_va = txd->llis_va;
562 struct lli *llis_bus = (struct lli *) txd->llis_bus;
564 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
566 llis_va[num_llis].cctl = cctl;
567 llis_va[num_llis].src = txd->srcbus.addr;
568 llis_va[num_llis].dst = txd->dstbus.addr;
571 * On versions with dual masters, you can optionally AND on
572 * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
573 * in new LLIs with that controller, but we always try to
574 * choose AHB1 to point into memory. The idea is to have AHB2
575 * fixed on the peripheral and AHB1 messing around in the
576 * memory. So we don't manipulate this bit currently.
579 llis_va[num_llis].next =
580 (dma_addr_t)((u32) &(llis_bus[num_llis + 1]));
582 if (cctl & PL080_CONTROL_SRC_INCR)
583 txd->srcbus.addr += len;
584 if (cctl & PL080_CONTROL_DST_INCR)
585 txd->dstbus.addr += len;
593 * Return number of bytes to fill to boundary, or len
595 static inline u32 pl08x_pre_boundary(u32 addr, u32 len)
599 boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
600 << PL08X_BOUNDARY_SHIFT;
602 if (boundary < addr + len)
603 return boundary - addr;
609 * This fills in the table of LLIs for the transfer descriptor
610 * Note that we assume we never have to change the burst sizes
613 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
614 struct pl08x_txd *txd)
616 struct pl08x_channel_data *cd = txd->cd;
617 struct pl08x_bus_data *mbus, *sbus;
621 int max_bytes_per_lli;
624 struct lli *llis_bus;
626 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
629 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
636 * Initialize bus values for this transfer
637 * from the passed optimal values
640 dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
644 /* Get the default CCTL from the platform data */
648 * On the PL080 we have two bus masters and we
649 * should select one for source and one for
650 * destination. We try to use AHB2 for the
651 * bus which does not increment (typically the
652 * peripheral) else we just choose something.
654 cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
655 if (pl08x->vd->dualmaster) {
656 if (cctl & PL080_CONTROL_SRC_INCR)
657 /* Source increments, use AHB2 for destination */
658 cctl |= PL080_CONTROL_DST_AHB2;
659 else if (cctl & PL080_CONTROL_DST_INCR)
660 /* Destination increments, use AHB2 for source */
661 cctl |= PL080_CONTROL_SRC_AHB2;
663 /* Just pick something, source AHB1 dest AHB2 */
664 cctl |= PL080_CONTROL_DST_AHB2;
667 /* Find maximum width of the source bus */
668 txd->srcbus.maxwidth =
669 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
670 PL080_CONTROL_SWIDTH_SHIFT);
672 /* Find maximum width of the destination bus */
673 txd->dstbus.maxwidth =
674 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
675 PL080_CONTROL_DWIDTH_SHIFT);
677 /* Set up the bus widths to the maximum */
678 txd->srcbus.buswidth = txd->srcbus.maxwidth;
679 txd->dstbus.buswidth = txd->dstbus.maxwidth;
680 dev_vdbg(&pl08x->adev->dev,
681 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
682 __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
686 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
688 max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
689 PL080_CONTROL_TRANSFER_SIZE_MASK;
690 dev_vdbg(&pl08x->adev->dev,
691 "%s max bytes per lli = %d\n",
692 __func__, max_bytes_per_lli);
694 /* We need to count this down to zero */
695 remainder = txd->len;
696 dev_vdbg(&pl08x->adev->dev,
697 "%s remainder = %d\n",
698 __func__, remainder);
701 * Choose bus to align to
702 * - prefers destination bus if both available
703 * - if fixed address on one bus chooses other
704 * - modifies cctl to choose an appropriate master
706 pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
711 * The lowest bit of the LLI register
712 * is also used to indicate which master to
713 * use for reading the LLIs.
716 if (txd->len < mbus->buswidth) {
718 * Less than a bus width available
719 * - send as single bytes
722 dev_vdbg(&pl08x->adev->dev,
723 "%s single byte LLIs for a transfer of "
724 "less than a bus width (remain 0x%08x)\n",
725 __func__, remainder);
726 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
728 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
734 * Make one byte LLIs until master bus is aligned
735 * - slave will then be aligned also
737 while ((mbus->addr) % (mbus->buswidth)) {
738 dev_vdbg(&pl08x->adev->dev,
739 "%s adjustment lli for less than bus width "
741 __func__, remainder);
742 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
743 num_llis = pl08x_fill_lli_for_desc
744 (pl08x, txd, num_llis, 1, cctl, &remainder);
750 * - if slave is not then we must set its width down
752 if (sbus->addr % sbus->buswidth) {
753 dev_dbg(&pl08x->adev->dev,
754 "%s set down bus width to one byte\n",
761 * Make largest possible LLIs until less than one bus
764 while (remainder > (mbus->buswidth - 1)) {
765 int lli_len, target_len;
770 * If enough left try to send max possible,
771 * otherwise try to send the remainder
773 target_len = remainder;
774 if (remainder > max_bytes_per_lli)
775 target_len = max_bytes_per_lli;
778 * Set bus lengths for incrementing buses
779 * to number of bytes which fill to next memory
782 if (cctl & PL080_CONTROL_SRC_INCR)
783 txd->srcbus.fill_bytes =
788 txd->srcbus.fill_bytes =
791 if (cctl & PL080_CONTROL_DST_INCR)
792 txd->dstbus.fill_bytes =
797 txd->dstbus.fill_bytes =
803 lli_len = min(txd->srcbus.fill_bytes,
804 txd->dstbus.fill_bytes);
806 BUG_ON(lli_len > remainder);
809 dev_err(&pl08x->adev->dev,
810 "%s lli_len is %d, <= 0\n",
815 if (lli_len == target_len) {
817 * Can send what we wanted
822 lli_len = (lli_len/mbus->buswidth) *
827 * So now we know how many bytes to transfer
828 * to get to the nearest boundary
829 * The next LLI will past the boundary
830 * - however we may be working to a boundary
832 * We need to ensure the master stays aligned
834 odd_bytes = lli_len % mbus->buswidth;
836 * - and that we are working in multiples
839 lli_len -= odd_bytes;
845 * Check against minimum bus alignment:
846 * Calculate actual transfer size in relation
847 * to bus width an get a maximum remainder of
848 * the smallest bus width - 1
850 /* FIXME: use round_down()? */
851 tsize = lli_len / min(mbus->buswidth,
853 lli_len = tsize * min(mbus->buswidth,
856 if (target_len != lli_len) {
857 dev_vdbg(&pl08x->adev->dev,
858 "%s can't send what we want. Desired 0x%08x, lli of 0x%08x bytes in txd of 0x%08x\n",
859 __func__, target_len, lli_len, txd->len);
862 cctl = pl08x_cctl_bits(cctl,
863 txd->srcbus.buswidth,
864 txd->dstbus.buswidth,
867 dev_vdbg(&pl08x->adev->dev,
868 "%s fill lli with single lli chunk of size 0x%08x (remainder 0x%08x)\n",
869 __func__, lli_len, remainder);
870 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
871 num_llis, lli_len, cctl,
873 total_bytes += lli_len;
879 * Creep past the boundary,
880 * maintaining master alignment
883 for (j = 0; (j < mbus->buswidth)
884 && (remainder); j++) {
885 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
886 dev_vdbg(&pl08x->adev->dev,
887 "%s align with boundary, single byte (remain 0x%08x)\n",
888 __func__, remainder);
890 pl08x_fill_lli_for_desc(pl08x,
902 dev_err(&pl08x->adev->dev, "%s remainder not fitted 0x%08x bytes\n",
903 __func__, remainder);
908 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
909 dev_vdbg(&pl08x->adev->dev,
910 "%s align with boundary, single odd byte (remain %d)\n",
911 __func__, remainder);
912 num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
913 1, cctl, &remainder);
917 if (total_bytes != txd->len) {
918 dev_err(&pl08x->adev->dev,
919 "%s size of encoded lli:s don't match total txd, transferred 0x%08x from size 0x%08x\n",
920 __func__, total_bytes, txd->len);
924 if (num_llis >= MAX_NUM_TSFR_LLIS) {
925 dev_err(&pl08x->adev->dev,
926 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
927 __func__, (u32) MAX_NUM_TSFR_LLIS);
931 llis_va = txd->llis_va;
933 * The final LLI terminates the LLI.
935 llis_va[num_llis - 1].next = 0;
937 * The final LLI element shall also fire an interrupt
939 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
941 /* Now store the channel register values */
942 txd->csrc = llis_va[0].src;
943 txd->cdst = llis_va[0].dst;
944 txd->clli = llis_va[0].next;
945 txd->cctl = llis_va[0].cctl;
946 /* ccfg will be set at physical channel allocation time */
952 for (i = 0; i < num_llis; i++) {
953 dev_vdbg(&pl08x->adev->dev,
954 "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
969 /* You should call this with the struct pl08x lock held */
970 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
971 struct pl08x_txd *txd)
974 dma_pool_free(pl08x->pool, txd->llis_va,
982 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
983 struct pl08x_dma_chan *plchan)
985 struct pl08x_txd *txdi = NULL;
986 struct pl08x_txd *next;
988 if (!list_empty(&plchan->desc_list)) {
989 list_for_each_entry_safe(txdi,
990 next, &plchan->desc_list, node) {
991 list_del(&txdi->node);
992 pl08x_free_txd(pl08x, txdi);
1001 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
1006 static void pl08x_free_chan_resources(struct dma_chan *chan)
1011 * This should be called with the channel plchan->lock held
1013 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
1014 struct pl08x_txd *txd)
1016 struct pl08x_driver_data *pl08x = plchan->host;
1017 struct pl08x_phy_chan *ch;
1020 /* Check if we already have a channel */
1021 if (plchan->phychan)
1024 ch = pl08x_get_phy_channel(pl08x, plchan);
1026 /* No physical channel available, cope with it */
1027 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1032 * OK we have a physical channel: for memcpy() this is all we
1033 * need, but for slaves the physical signals may be muxed!
1034 * Can the platform allow us to use this channel?
1036 if (plchan->slave &&
1038 pl08x->pd->get_signal) {
1039 ret = pl08x->pd->get_signal(plchan);
1041 dev_dbg(&pl08x->adev->dev,
1042 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1043 ch->id, plchan->name);
1044 /* Release physical channel & return */
1045 pl08x_put_phy_channel(pl08x, ch);
1051 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1056 plchan->phychan = ch;
1061 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1063 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1065 plchan->chan.cookie += 1;
1066 if (plchan->chan.cookie < 0)
1067 plchan->chan.cookie = 1;
1068 tx->cookie = plchan->chan.cookie;
1069 /* This unlock follows the lock in the prep() function */
1070 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1075 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1076 struct dma_chan *chan, unsigned long flags)
1078 struct dma_async_tx_descriptor *retval = NULL;
1084 * Code accessing dma_async_is_complete() in a tight loop
1085 * may give problems - could schedule where indicated.
1086 * If slaves are relying on interrupts to signal completion this
1087 * function must not be called with interrupts disabled
1089 static enum dma_status
1090 pl08x_dma_tx_status(struct dma_chan *chan,
1091 dma_cookie_t cookie,
1092 struct dma_tx_state *txstate)
1094 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1095 dma_cookie_t last_used;
1096 dma_cookie_t last_complete;
1097 enum dma_status ret;
1100 last_used = plchan->chan.cookie;
1101 last_complete = plchan->lc;
1103 ret = dma_async_is_complete(cookie, last_complete, last_used);
1104 if (ret == DMA_SUCCESS) {
1105 dma_set_tx_state(txstate, last_complete, last_used, 0);
1110 * schedule(); could be inserted here
1114 * This cookie not complete yet
1116 last_used = plchan->chan.cookie;
1117 last_complete = plchan->lc;
1119 /* Get number of bytes left in the active transactions and queue */
1120 bytesleft = pl08x_getbytes_chan(plchan);
1122 dma_set_tx_state(txstate, last_complete, last_used,
1125 if (plchan->state == PL08X_CHAN_PAUSED)
1128 /* Whether waiting or running, we're in progress */
1129 return DMA_IN_PROGRESS;
1132 /* PrimeCell DMA extension */
1133 struct burst_table {
1138 static const struct burst_table burst_sizes[] = {
1141 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1142 (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1146 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1147 (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1151 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1152 (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1156 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1157 (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1161 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1162 (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1166 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1167 (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1171 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1172 (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1176 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1177 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1181 static void dma_set_runtime_config(struct dma_chan *chan,
1182 struct dma_slave_config *config)
1184 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1185 struct pl08x_driver_data *pl08x = plchan->host;
1186 struct pl08x_channel_data *cd = plchan->cd;
1187 enum dma_slave_buswidth addr_width;
1190 /* Mask out all except src and dst channel */
1191 u32 ccfg = cd->ccfg & 0x000003DEU;
1194 /* Transfer direction */
1195 plchan->runtime_direction = config->direction;
1196 if (config->direction == DMA_TO_DEVICE) {
1197 plchan->runtime_addr = config->dst_addr;
1198 cctl |= PL080_CONTROL_SRC_INCR;
1199 ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1200 addr_width = config->dst_addr_width;
1201 maxburst = config->dst_maxburst;
1202 } else if (config->direction == DMA_FROM_DEVICE) {
1203 plchan->runtime_addr = config->src_addr;
1204 cctl |= PL080_CONTROL_DST_INCR;
1205 ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1206 addr_width = config->src_addr_width;
1207 maxburst = config->src_maxburst;
1209 dev_err(&pl08x->adev->dev,
1210 "bad runtime_config: alien transfer direction\n");
1214 switch (addr_width) {
1215 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1216 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1217 (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1219 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1220 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1221 (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1223 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1224 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1225 (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1228 dev_err(&pl08x->adev->dev,
1229 "bad runtime_config: alien address width\n");
1234 * Now decide on a maxburst:
1235 * If this channel will only request single transfers, set this
1236 * down to ONE element. Also select one element if no maxburst
1239 if (plchan->cd->single || maxburst == 0) {
1240 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1241 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1243 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1244 if (burst_sizes[i].burstwords <= maxburst)
1246 cctl |= burst_sizes[i].reg;
1249 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1250 cctl &= ~PL080_CONTROL_PROT_MASK;
1251 cctl |= PL080_CONTROL_PROT_SYS;
1253 /* Modify the default channel data to fit PrimeCell request */
1257 dev_dbg(&pl08x->adev->dev,
1258 "configured channel %s (%s) for %s, data width %d, "
1259 "maxburst %d words, LE, CCTL=0x%08x, CCFG=0x%08x\n",
1260 dma_chan_name(chan), plchan->name,
1261 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1268 * Slave transactions callback to the slave device to allow
1269 * synchronization of slave DMA signals with the DMAC enable
1271 static void pl08x_issue_pending(struct dma_chan *chan)
1273 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1274 struct pl08x_driver_data *pl08x = plchan->host;
1275 unsigned long flags;
1277 spin_lock_irqsave(&plchan->lock, flags);
1278 /* Something is already active, or we're waiting for a channel... */
1279 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1280 spin_unlock_irqrestore(&plchan->lock, flags);
1284 /* Take the first element in the queue and execute it */
1285 if (!list_empty(&plchan->desc_list)) {
1286 struct pl08x_txd *next;
1288 next = list_first_entry(&plchan->desc_list,
1291 list_del(&next->node);
1293 plchan->state = PL08X_CHAN_RUNNING;
1295 /* Configure the physical channel for the active txd */
1296 pl08x_config_phychan_for_txd(plchan);
1297 pl08x_set_cregs(pl08x, plchan->phychan);
1298 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1301 spin_unlock_irqrestore(&plchan->lock, flags);
1304 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1305 struct pl08x_txd *txd)
1308 struct pl08x_driver_data *pl08x = plchan->host;
1311 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1317 spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1319 list_add_tail(&txd->node, &plchan->desc_list);
1322 * See if we already have a physical channel allocated,
1323 * else this is the time to try to get one.
1325 ret = prep_phy_channel(plchan, txd);
1328 * No physical channel available, we will
1329 * stack up the memcpy channels until there is a channel
1330 * available to handle it whereas slave transfers may
1331 * have been denied due to platform channel muxing restrictions
1332 * and since there is no guarantee that this will ever be
1333 * resolved, and since the signal must be acquired AFTER
1334 * acquiring the physical channel, we will let them be NACK:ed
1335 * with -EBUSY here. The drivers can alway retry the prep()
1336 * call if they are eager on doing this using DMA.
1338 if (plchan->slave) {
1339 pl08x_free_txd_list(pl08x, plchan);
1340 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1343 /* Do this memcpy whenever there is a channel ready */
1344 plchan->state = PL08X_CHAN_WAITING;
1345 plchan->waiting = txd;
1348 * Else we're all set, paused and ready to roll,
1349 * status will switch to PL08X_CHAN_RUNNING when
1350 * we call issue_pending(). If there is something
1351 * running on the channel already we don't change
1354 if (plchan->state == PL08X_CHAN_IDLE)
1355 plchan->state = PL08X_CHAN_PAUSED;
1358 * Notice that we leave plchan->lock locked on purpose:
1359 * it will be unlocked in the subsequent tx_submit()
1360 * call. This is a consequence of the current API.
1367 * Initialize a descriptor to be used by memcpy submit
1369 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1370 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1371 size_t len, unsigned long flags)
1373 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1374 struct pl08x_driver_data *pl08x = plchan->host;
1375 struct pl08x_txd *txd;
1378 txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1380 dev_err(&pl08x->adev->dev,
1381 "%s no memory for descriptor\n", __func__);
1385 dma_async_tx_descriptor_init(&txd->tx, chan);
1386 txd->direction = DMA_NONE;
1387 txd->srcbus.addr = src;
1388 txd->dstbus.addr = dest;
1390 /* Set platform data for m2m */
1391 txd->cd = &pl08x->pd->memcpy_channel;
1392 /* Both to be incremented or the code will break */
1393 txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1394 txd->tx.tx_submit = pl08x_tx_submit;
1395 txd->tx.callback = NULL;
1396 txd->tx.callback_param = NULL;
1399 INIT_LIST_HEAD(&txd->node);
1400 ret = pl08x_prep_channel_resources(plchan, txd);
1404 * NB: the channel lock is held at this point so tx_submit()
1405 * must be called in direct succession.
1411 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1412 struct dma_chan *chan, struct scatterlist *sgl,
1413 unsigned int sg_len, enum dma_data_direction direction,
1414 unsigned long flags)
1416 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1417 struct pl08x_driver_data *pl08x = plchan->host;
1418 struct pl08x_txd *txd;
1422 * Current implementation ASSUMES only one sg
1425 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1430 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1431 __func__, sgl->length, plchan->name);
1433 txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1435 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1439 dma_async_tx_descriptor_init(&txd->tx, chan);
1441 if (direction != plchan->runtime_direction)
1442 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1443 "the direction configured for the PrimeCell\n",
1447 * Set up addresses, the PrimeCell configured address
1448 * will take precedence since this may configure the
1449 * channel target address dynamically at runtime.
1451 txd->direction = direction;
1452 if (direction == DMA_TO_DEVICE) {
1453 txd->srcbus.addr = sgl->dma_address;
1454 if (plchan->runtime_addr)
1455 txd->dstbus.addr = plchan->runtime_addr;
1457 txd->dstbus.addr = plchan->cd->addr;
1458 } else if (direction == DMA_FROM_DEVICE) {
1459 if (plchan->runtime_addr)
1460 txd->srcbus.addr = plchan->runtime_addr;
1462 txd->srcbus.addr = plchan->cd->addr;
1463 txd->dstbus.addr = sgl->dma_address;
1465 dev_err(&pl08x->adev->dev,
1466 "%s direction unsupported\n", __func__);
1469 txd->cd = plchan->cd;
1470 txd->tx.tx_submit = pl08x_tx_submit;
1471 txd->tx.callback = NULL;
1472 txd->tx.callback_param = NULL;
1473 txd->len = sgl->length;
1474 INIT_LIST_HEAD(&txd->node);
1476 ret = pl08x_prep_channel_resources(plchan, txd);
1480 * NB: the channel lock is held at this point so tx_submit()
1481 * must be called in direct succession.
1487 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1490 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1491 struct pl08x_driver_data *pl08x = plchan->host;
1492 unsigned long flags;
1495 /* Controls applicable to inactive channels */
1496 if (cmd == DMA_SLAVE_CONFIG) {
1497 dma_set_runtime_config(chan,
1498 (struct dma_slave_config *)
1504 * Anything succeeds on channels with no physical allocation and
1505 * no queued transfers.
1507 spin_lock_irqsave(&plchan->lock, flags);
1508 if (!plchan->phychan && !plchan->at) {
1509 spin_unlock_irqrestore(&plchan->lock, flags);
1514 case DMA_TERMINATE_ALL:
1515 plchan->state = PL08X_CHAN_IDLE;
1517 if (plchan->phychan) {
1518 pl08x_stop_phy_chan(plchan->phychan);
1521 * Mark physical channel as free and free any slave
1524 if ((plchan->phychan->signal >= 0) &&
1525 pl08x->pd->put_signal) {
1526 pl08x->pd->put_signal(plchan);
1527 plchan->phychan->signal = -1;
1529 pl08x_put_phy_channel(pl08x, plchan->phychan);
1530 plchan->phychan = NULL;
1532 /* Dequeue jobs and free LLIs */
1534 pl08x_free_txd(pl08x, plchan->at);
1537 /* Dequeue jobs not yet fired as well */
1538 pl08x_free_txd_list(pl08x, plchan);
1541 pl08x_pause_phy_chan(plchan->phychan);
1542 plchan->state = PL08X_CHAN_PAUSED;
1545 pl08x_resume_phy_chan(plchan->phychan);
1546 plchan->state = PL08X_CHAN_RUNNING;
1549 /* Unknown command */
1554 spin_unlock_irqrestore(&plchan->lock, flags);
1559 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1561 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1562 char *name = chan_id;
1564 /* Check that the channel is not taken! */
1565 if (!strcmp(plchan->name, name))
1572 * Just check that the device is there and active
1573 * TODO: turn this bit on/off depending on the number of
1574 * physical channels actually used, if it is zero... well
1575 * shut it off. That will save some power. Cut the clock
1578 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1582 val = readl(pl08x->base + PL080_CONFIG);
1583 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1584 /* We implicitly clear bit 1 and that means little-endian mode */
1585 val |= PL080_CONFIG_ENABLE;
1586 writel(val, pl08x->base + PL080_CONFIG);
1589 static void pl08x_tasklet(unsigned long data)
1591 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1592 struct pl08x_phy_chan *phychan = plchan->phychan;
1593 struct pl08x_driver_data *pl08x = plchan->host;
1594 unsigned long flags;
1596 spin_lock_irqsave(&plchan->lock, flags);
1599 dma_async_tx_callback callback =
1600 plchan->at->tx.callback;
1601 void *callback_param =
1602 plchan->at->tx.callback_param;
1605 * Update last completed
1607 plchan->lc = plchan->at->tx.cookie;
1610 * Callback to signal completion
1613 callback(callback_param);
1616 * Free the descriptor
1618 pl08x_free_txd(pl08x, plchan->at);
1622 * If a new descriptor is queued, set it up
1623 * plchan->at is NULL here
1625 if (!list_empty(&plchan->desc_list)) {
1626 struct pl08x_txd *next;
1628 next = list_first_entry(&plchan->desc_list,
1631 list_del(&next->node);
1633 /* Configure the physical channel for the next txd */
1634 pl08x_config_phychan_for_txd(plchan);
1635 pl08x_set_cregs(pl08x, plchan->phychan);
1636 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1638 struct pl08x_dma_chan *waiting = NULL;
1641 * No more jobs, so free up the physical channel
1642 * Free any allocated signal on slave transfers too
1644 if ((phychan->signal >= 0) && pl08x->pd->put_signal) {
1645 pl08x->pd->put_signal(plchan);
1646 phychan->signal = -1;
1648 pl08x_put_phy_channel(pl08x, phychan);
1649 plchan->phychan = NULL;
1650 plchan->state = PL08X_CHAN_IDLE;
1653 * And NOW before anyone else can grab that free:d
1654 * up physical channel, see if there is some memcpy
1655 * pending that seriously needs to start because of
1656 * being stacked up while we were choking the
1657 * physical channels with data.
1659 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1661 if (waiting->state == PL08X_CHAN_WAITING &&
1662 waiting->waiting != NULL) {
1665 /* This should REALLY not fail now */
1666 ret = prep_phy_channel(waiting,
1669 waiting->state = PL08X_CHAN_RUNNING;
1670 waiting->waiting = NULL;
1671 pl08x_issue_pending(&waiting->chan);
1677 spin_unlock_irqrestore(&plchan->lock, flags);
1680 static irqreturn_t pl08x_irq(int irq, void *dev)
1682 struct pl08x_driver_data *pl08x = dev;
1687 val = readl(pl08x->base + PL080_ERR_STATUS);
1690 * An error interrupt (on one or more channels)
1692 dev_err(&pl08x->adev->dev,
1693 "%s error interrupt, register value 0x%08x\n",
1696 * Simply clear ALL PL08X error interrupts,
1697 * regardless of channel and cause
1698 * FIXME: should be 0x00000003 on PL081 really.
1700 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1702 val = readl(pl08x->base + PL080_INT_STATUS);
1703 for (i = 0; i < pl08x->vd->channels; i++) {
1704 if ((1 << i) & val) {
1705 /* Locate physical channel */
1706 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1707 struct pl08x_dma_chan *plchan = phychan->serving;
1709 /* Schedule tasklet on this channel */
1710 tasklet_schedule(&plchan->tasklet);
1716 * Clear only the terminal interrupts on channels we processed
1718 writel(mask, pl08x->base + PL080_TC_CLEAR);
1720 return mask ? IRQ_HANDLED : IRQ_NONE;
1724 * Initialise the DMAC memcpy/slave channels.
1725 * Make a local wrapper to hold required data
1727 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1728 struct dma_device *dmadev,
1729 unsigned int channels,
1732 struct pl08x_dma_chan *chan;
1735 INIT_LIST_HEAD(&dmadev->channels);
1737 * Register as many many memcpy as we have physical channels,
1738 * we won't always be able to use all but the code will have
1739 * to cope with that situation.
1741 for (i = 0; i < channels; i++) {
1742 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1744 dev_err(&pl08x->adev->dev,
1745 "%s no memory for channel\n", __func__);
1750 chan->state = PL08X_CHAN_IDLE;
1754 chan->name = pl08x->pd->slave_channels[i].bus_id;
1755 chan->cd = &pl08x->pd->slave_channels[i];
1757 chan->cd = &pl08x->pd->memcpy_channel;
1758 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1764 if (chan->cd->circular_buffer) {
1765 dev_err(&pl08x->adev->dev,
1766 "channel %s: circular buffers not supported\n",
1771 dev_info(&pl08x->adev->dev,
1772 "initialize virtual channel \"%s\"\n",
1775 chan->chan.device = dmadev;
1776 chan->chan.cookie = 0;
1779 spin_lock_init(&chan->lock);
1780 INIT_LIST_HEAD(&chan->desc_list);
1781 tasklet_init(&chan->tasklet, pl08x_tasklet,
1782 (unsigned long) chan);
1784 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1786 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1787 i, slave ? "slave" : "memcpy");
1791 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1793 struct pl08x_dma_chan *chan = NULL;
1794 struct pl08x_dma_chan *next;
1796 list_for_each_entry_safe(chan,
1797 next, &dmadev->channels, chan.device_node) {
1798 list_del(&chan->chan.device_node);
1803 #ifdef CONFIG_DEBUG_FS
1804 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1807 case PL08X_CHAN_IDLE:
1809 case PL08X_CHAN_RUNNING:
1811 case PL08X_CHAN_PAUSED:
1813 case PL08X_CHAN_WAITING:
1818 return "UNKNOWN STATE";
1821 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1823 struct pl08x_driver_data *pl08x = s->private;
1824 struct pl08x_dma_chan *chan;
1825 struct pl08x_phy_chan *ch;
1826 unsigned long flags;
1829 seq_printf(s, "PL08x physical channels:\n");
1830 seq_printf(s, "CHANNEL:\tUSER:\n");
1831 seq_printf(s, "--------\t-----\n");
1832 for (i = 0; i < pl08x->vd->channels; i++) {
1833 struct pl08x_dma_chan *virt_chan;
1835 ch = &pl08x->phy_chans[i];
1837 spin_lock_irqsave(&ch->lock, flags);
1838 virt_chan = ch->serving;
1840 seq_printf(s, "%d\t\t%s\n",
1841 ch->id, virt_chan ? virt_chan->name : "(none)");
1843 spin_unlock_irqrestore(&ch->lock, flags);
1846 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1847 seq_printf(s, "CHANNEL:\tSTATE:\n");
1848 seq_printf(s, "--------\t------\n");
1849 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1850 seq_printf(s, "%s\t\t%s\n", chan->name,
1851 pl08x_state_str(chan->state));
1854 seq_printf(s, "\nPL08x virtual slave channels:\n");
1855 seq_printf(s, "CHANNEL:\tSTATE:\n");
1856 seq_printf(s, "--------\t------\n");
1857 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1858 seq_printf(s, "%s\t\t%s\n", chan->name,
1859 pl08x_state_str(chan->state));
1865 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1867 return single_open(file, pl08x_debugfs_show, inode->i_private);
1870 static const struct file_operations pl08x_debugfs_operations = {
1871 .open = pl08x_debugfs_open,
1873 .llseek = seq_lseek,
1874 .release = single_release,
1877 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1879 /* Expose a simple debugfs interface to view all clocks */
1880 (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1882 &pl08x_debugfs_operations);
1886 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1891 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1893 struct pl08x_driver_data *pl08x;
1894 const struct vendor_data *vd = id->data;
1898 ret = amba_request_regions(adev, NULL);
1902 /* Create the driver state holder */
1903 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1909 /* Initialize memcpy engine */
1910 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1911 pl08x->memcpy.dev = &adev->dev;
1912 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1913 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1914 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1915 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1916 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1917 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1918 pl08x->memcpy.device_control = pl08x_control;
1920 /* Initialize slave engine */
1921 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1922 pl08x->slave.dev = &adev->dev;
1923 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1924 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1925 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1926 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1927 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1928 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1929 pl08x->slave.device_control = pl08x_control;
1931 /* Get the platform data */
1932 pl08x->pd = dev_get_platdata(&adev->dev);
1934 dev_err(&adev->dev, "no platform data supplied\n");
1935 goto out_no_platdata;
1938 /* Assign useful pointers to the driver state */
1942 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1943 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1944 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1947 goto out_no_lli_pool;
1950 spin_lock_init(&pl08x->lock);
1952 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1955 goto out_no_ioremap;
1958 /* Turn on the PL08x */
1959 pl08x_ensure_on(pl08x);
1962 * Attach the interrupt handler
1964 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1965 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1967 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1968 DRIVER_NAME, pl08x);
1970 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1971 __func__, adev->irq[0]);
1975 /* Initialize physical channels */
1976 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1978 if (!pl08x->phy_chans) {
1979 dev_err(&adev->dev, "%s failed to allocate "
1980 "physical channel holders\n",
1982 goto out_no_phychans;
1985 for (i = 0; i < vd->channels; i++) {
1986 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1989 ch->base = pl08x->base + PL080_Cx_BASE(i);
1990 spin_lock_init(&ch->lock);
1993 dev_info(&adev->dev,
1994 "physical channel %d is %s\n", i,
1995 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1998 /* Register as many memcpy channels as there are physical channels */
1999 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
2000 pl08x->vd->channels, false);
2002 dev_warn(&pl08x->adev->dev,
2003 "%s failed to enumerate memcpy channels - %d\n",
2007 pl08x->memcpy.chancnt = ret;
2009 /* Register slave channels */
2010 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2011 pl08x->pd->num_slave_channels,
2014 dev_warn(&pl08x->adev->dev,
2015 "%s failed to enumerate slave channels - %d\n",
2019 pl08x->slave.chancnt = ret;
2021 ret = dma_async_device_register(&pl08x->memcpy);
2023 dev_warn(&pl08x->adev->dev,
2024 "%s failed to register memcpy as an async device - %d\n",
2026 goto out_no_memcpy_reg;
2029 ret = dma_async_device_register(&pl08x->slave);
2031 dev_warn(&pl08x->adev->dev,
2032 "%s failed to register slave as an async device - %d\n",
2034 goto out_no_slave_reg;
2037 amba_set_drvdata(adev, pl08x);
2038 init_pl08x_debugfs(pl08x);
2039 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2040 amba_part(adev), amba_rev(adev),
2041 (unsigned long long)adev->res.start, adev->irq[0]);
2045 dma_async_device_unregister(&pl08x->memcpy);
2047 pl08x_free_virtual_channels(&pl08x->slave);
2049 pl08x_free_virtual_channels(&pl08x->memcpy);
2051 kfree(pl08x->phy_chans);
2053 free_irq(adev->irq[0], pl08x);
2055 iounmap(pl08x->base);
2057 dma_pool_destroy(pl08x->pool);
2062 amba_release_regions(adev);
2066 /* PL080 has 8 channels and the PL080 have just 2 */
2067 static struct vendor_data vendor_pl080 = {
2072 static struct vendor_data vendor_pl081 = {
2074 .dualmaster = false,
2077 static struct amba_id pl08x_ids[] = {
2082 .data = &vendor_pl080,
2088 .data = &vendor_pl081,
2090 /* Nomadik 8815 PL080 variant */
2094 .data = &vendor_pl080,
2099 static struct amba_driver pl08x_amba_driver = {
2100 .drv.name = DRIVER_NAME,
2101 .id_table = pl08x_ids,
2102 .probe = pl08x_probe,
2105 static int __init pl08x_init(void)
2108 retval = amba_driver_register(&pl08x_amba_driver);
2110 printk(KERN_WARNING DRIVER_NAME
2111 "failed to register as an AMBA device (%d)\n",
2115 subsys_initcall(pl08x_init);