1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */
3 #include <linux/device.h>
4 #include <linux/module.h>
5 #include <linux/slab.h>
13 * The port driver enumerates dport via PCI and scans for HDM
14 * (Host-managed-Device-Memory) decoder resources via the
15 * @component_reg_phys value passed in by the agent that registered the
16 * port. All descendant ports of a CXL root port (described by platform
17 * firmware) are managed in this drivers context. Each driver instance
18 * is responsible for tearing down the driver context of immediate
19 * descendant ports. The locking for this is validated by
20 * CONFIG_PROVE_CXL_LOCKING.
22 * The primary service this driver provides is presenting APIs to other
23 * drivers to utilize the decoders, and indicating to userspace (via bind
24 * status) the connectivity of the CXL.mem protocol throughout the
28 static void schedule_detach(void *cxlmd)
30 schedule_cxl_memdev_detach(cxlmd);
33 static int discover_region(struct device *dev, void *root)
35 struct cxl_endpoint_decoder *cxled;
38 if (!is_endpoint_decoder(dev))
41 cxled = to_cxl_endpoint_decoder(dev);
42 if ((cxled->cxld.flags & CXL_DECODER_F_ENABLE) == 0)
45 if (cxled->state != CXL_DECODER_STATE_AUTO)
49 * Region enumeration is opportunistic, if this add-event fails,
50 * continue to the next endpoint decoder.
52 rc = cxl_add_to_region(root, cxled);
54 dev_dbg(dev, "failed to add to region: %#llx-%#llx\n",
55 cxled->cxld.hpa_range.start, cxled->cxld.hpa_range.end);
60 static int cxl_switch_port_probe(struct cxl_port *port)
62 struct cxl_hdm *cxlhdm;
65 rc = devm_cxl_port_enumerate_dports(port);
70 return devm_cxl_add_passthrough_decoder(port);
72 cxlhdm = devm_cxl_setup_hdm(port, NULL);
74 return PTR_ERR(cxlhdm);
76 return devm_cxl_enumerate_decoders(cxlhdm, NULL);
79 static int cxl_endpoint_port_probe(struct cxl_port *port)
81 struct cxl_endpoint_dvsec_info info = { .port = port };
82 struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
83 struct cxl_dev_state *cxlds = cxlmd->cxlds;
84 struct cxl_hdm *cxlhdm;
85 struct cxl_port *root;
88 rc = cxl_dvsec_rr_decode(cxlds->dev, cxlds->cxl_dvsec, &info);
92 cxlhdm = devm_cxl_setup_hdm(port, &info);
94 return PTR_ERR(cxlhdm);
96 /* Cache the data early to ensure is_visible() works */
99 get_device(&cxlmd->dev);
100 rc = devm_add_action_or_reset(&port->dev, schedule_detach, cxlmd);
104 rc = cxl_hdm_decode_init(cxlds, cxlhdm, &info);
108 rc = cxl_await_media_ready(cxlds);
110 dev_err(&port->dev, "Media not active (%d)\n", rc);
114 rc = devm_cxl_enumerate_decoders(cxlhdm, &info);
119 * This can't fail in practice as CXL root exit unregisters all
120 * descendant ports and that in turn synchronizes with cxl_port_probe()
122 root = find_cxl_root(port);
125 * Now that all endpoint decoders are successfully enumerated, try to
126 * assemble regions from committed decoders
128 device_for_each_child(&port->dev, root, discover_region);
129 put_device(&root->dev);
134 static int cxl_port_probe(struct device *dev)
136 struct cxl_port *port = to_cxl_port(dev);
138 if (is_cxl_endpoint(port))
139 return cxl_endpoint_port_probe(port);
140 return cxl_switch_port_probe(port);
143 static ssize_t CDAT_read(struct file *filp, struct kobject *kobj,
144 struct bin_attribute *bin_attr, char *buf,
145 loff_t offset, size_t count)
147 struct device *dev = kobj_to_dev(kobj);
148 struct cxl_port *port = to_cxl_port(dev);
150 if (!port->cdat_available)
153 if (!port->cdat.table)
156 return memory_read_from_buffer(buf, count, &offset,
161 static BIN_ATTR_ADMIN_RO(CDAT, 0);
163 static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
164 struct bin_attribute *attr, int i)
166 struct device *dev = kobj_to_dev(kobj);
167 struct cxl_port *port = to_cxl_port(dev);
169 if ((attr == &bin_attr_CDAT) && port->cdat_available)
170 return attr->attr.mode;
175 static struct bin_attribute *cxl_cdat_bin_attributes[] = {
180 static struct attribute_group cxl_cdat_attribute_group = {
181 .bin_attrs = cxl_cdat_bin_attributes,
182 .is_bin_visible = cxl_port_bin_attr_is_visible,
185 static const struct attribute_group *cxl_port_attribute_groups[] = {
186 &cxl_cdat_attribute_group,
190 static struct cxl_driver cxl_port_driver = {
192 .probe = cxl_port_probe,
193 .id = CXL_DEVICE_PORT,
195 .dev_groups = cxl_port_attribute_groups,
199 module_cxl_driver(cxl_port_driver);
200 MODULE_LICENSE("GPL v2");
201 MODULE_IMPORT_NS(CXL);
202 MODULE_ALIAS_CXL(CXL_DEVICE_PORT);