1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020-2021 Intel Corporation. */
6 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
7 #define CXLMDEV_STATUS_OFFSET 0x0
8 #define CXLMDEV_DEV_FATAL BIT(0)
9 #define CXLMDEV_FW_HALT BIT(1)
10 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
11 #define CXLMDEV_MS_NOT_READY 0
12 #define CXLMDEV_MS_READY 1
13 #define CXLMDEV_MS_ERROR 2
14 #define CXLMDEV_MS_DISABLED 3
15 #define CXLMDEV_READY(status) \
16 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
18 #define CXLMDEV_MBOX_IF_READY BIT(4)
19 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
20 #define CXLMDEV_RESET_NEEDED_NOT 0
21 #define CXLMDEV_RESET_NEEDED_COLD 1
22 #define CXLMDEV_RESET_NEEDED_WARM 2
23 #define CXLMDEV_RESET_NEEDED_HOT 3
24 #define CXLMDEV_RESET_NEEDED_CXL 4
25 #define CXLMDEV_RESET_NEEDED(status) \
26 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
27 CXLMDEV_RESET_NEEDED_NOT)
30 * An entire PCI topology full of devices should be enough for any
33 #define CXL_MEM_MAX_DEVS 65536
36 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
37 * @dev: driver core device object
38 * @cdev: char dev core object for ioctl operations
39 * @cxlm: pointer to the parent device driver data
40 * @id: id number of this memdev instance.
50 * struct cxl_mem - A CXL memory device
51 * @pdev: The PCI device associated with this CXL device.
52 * @base: IO mappings to the device's MMIO
53 * @cxlmd: Logical memory device chardev / interface
54 * @regs: Parsed register blocks
55 * @payload_size: Size of space for payload
56 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
57 * @mbox_mutex: Mutex to synchronize mailbox access.
58 * @firmware_version: Firmware version for the memory device.
59 * @enabled_cmds: Hardware commands found enabled in CEL.
60 * @pmem_range: Persistent memory capacity information.
61 * @ram_range: Volatile memory capacity information.
66 struct cxl_memdev *cxlmd;
71 struct mutex mbox_mutex; /* Protects device mailbox and firmware */
72 char firmware_version[0x10];
73 unsigned long *enabled_cmds;
75 struct range pmem_range;
76 struct range ram_range;
78 #endif /* __CXL_MEM_H__ */