1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020 Intel Corporation. */
7 #include <linux/libnvdimm.h>
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
15 * The CXL core objects like ports, decoders, and regions are shared
16 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
17 * (port-driver, region-driver, nvdimm object-drivers... etc).
20 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
21 #define CXL_CM_OFFSET 0x1000
22 #define CXL_CM_CAP_HDR_OFFSET 0x0
23 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
24 #define CM_CAP_HDR_CAP_ID 1
25 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
26 #define CM_CAP_HDR_CAP_VERSION 1
27 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)
28 #define CM_CAP_HDR_CACHE_MEM_VERSION 1
29 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
30 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
32 #define CXL_CM_CAP_CAP_ID_HDM 0x5
33 #define CXL_CM_CAP_CAP_HDM_VERSION 1
35 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
36 #define CXL_HDM_DECODER_CAP_OFFSET 0x0
37 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
38 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
39 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET 0x10
40 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET 0x14
41 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET 0x18
42 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET 0x1c
43 #define CXL_HDM_DECODER0_CTRL_OFFSET 0x20
45 static inline int cxl_hdm_decoder_count(u32 cap_hdr)
47 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
49 return val ? val * 2 : 1;
52 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
53 #define CXLDEV_CAP_ARRAY_OFFSET 0x0
54 #define CXLDEV_CAP_ARRAY_CAP_ID 0
55 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
56 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
57 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
58 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
59 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
60 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
61 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
62 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3
63 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000
65 /* CXL 2.0 8.2.8.4 Mailbox Registers */
66 #define CXLDEV_MBOX_CAPS_OFFSET 0x00
67 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
68 #define CXLDEV_MBOX_CTRL_OFFSET 0x04
69 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
70 #define CXLDEV_MBOX_CMD_OFFSET 0x08
71 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
72 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
73 #define CXLDEV_MBOX_STATUS_OFFSET 0x10
74 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
75 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18
76 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
78 #define CXL_COMPONENT_REGS() \
79 void __iomem *hdm_decoder
81 #define CXL_DEVICE_REGS() \
82 void __iomem *status; \
86 /* See note for 'struct cxl_regs' for the rationale of this organization */
88 * CXL_COMPONENT_REGS - Common set of CXL Component register block base pointers
89 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
91 struct cxl_component_regs {
95 /* See note for 'struct cxl_regs' for the rationale of this organization */
97 * CXL_DEVICE_REGS - Common set of CXL Device register block base pointers
98 * @status: CXL 2.0 8.2.8.3 Device Status Registers
99 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
100 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
102 struct cxl_device_regs {
107 * Note, the anonymous union organization allows for per
108 * register-block-type helper routines, without requiring block-type
109 * agnostic code to include the prefix.
114 CXL_COMPONENT_REGS();
116 struct cxl_component_regs component;
122 struct cxl_device_regs device_regs;
128 unsigned long offset;
132 struct cxl_component_reg_map {
133 struct cxl_reg_map hdm_decoder;
136 struct cxl_device_reg_map {
137 struct cxl_reg_map status;
138 struct cxl_reg_map mbox;
139 struct cxl_reg_map memdev;
142 struct cxl_register_map {
143 struct list_head list;
148 struct cxl_component_reg_map component_map;
149 struct cxl_device_reg_map device_map;
153 void cxl_probe_component_regs(struct device *dev, void __iomem *base,
154 struct cxl_component_reg_map *map);
155 void cxl_probe_device_regs(struct device *dev, void __iomem *base,
156 struct cxl_device_reg_map *map);
157 int cxl_map_component_regs(struct pci_dev *pdev,
158 struct cxl_component_regs *regs,
159 struct cxl_register_map *map);
160 int cxl_map_device_regs(struct pci_dev *pdev,
161 struct cxl_device_regs *regs,
162 struct cxl_register_map *map);
164 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
165 #define CXL_TARGET_STRLEN 20
168 * cxl_decoder flags that define the type of memory / devices this
169 * decoder supports as well as configuration lock status See "CXL 2.0
170 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
172 #define CXL_DECODER_F_RAM BIT(0)
173 #define CXL_DECODER_F_PMEM BIT(1)
174 #define CXL_DECODER_F_TYPE2 BIT(2)
175 #define CXL_DECODER_F_TYPE3 BIT(3)
176 #define CXL_DECODER_F_LOCK BIT(4)
177 #define CXL_DECODER_F_MASK GENMASK(4, 0)
179 enum cxl_decoder_type {
180 CXL_DECODER_ACCELERATOR = 2,
181 CXL_DECODER_EXPANDER = 3,
185 * struct cxl_decoder - CXL address range decode configuration
186 * @dev: this decoder's device
187 * @id: kernel device name id
188 * @range: address range considered by this decoder
189 * @interleave_ways: number of cxl_dports in this decode
190 * @interleave_granularity: data stride per dport
191 * @target_type: accelerator vs expander (type2 vs type3) selector
192 * @flags: memory type capabilities and locking
193 * @target: active ordered target list in current decoder configuration
200 int interleave_granularity;
201 enum cxl_decoder_type target_type;
203 struct cxl_dport *target[];
207 enum cxl_nvdimm_brige_state {
214 struct cxl_nvdimm_bridge {
216 struct cxl_port *port;
217 struct nvdimm_bus *nvdimm_bus;
218 struct nvdimm_bus_descriptor nd_desc;
219 struct work_struct state_work;
220 enum cxl_nvdimm_brige_state state;
225 struct cxl_memdev *cxlmd;
226 struct nvdimm *nvdimm;
230 * struct cxl_port - logical collection of upstream port devices and
231 * downstream port devices to construct a CXL memory
233 * @dev: this port's device
234 * @uport: PCI or platform device implementing the upstream port capability
235 * @id: id for port device-name
236 * @dports: cxl_dport instances referenced by decoders
237 * @decoder_ida: allocator for decoder ids
238 * @component_reg_phys: component register capability base address (optional)
242 struct device *uport;
244 struct list_head dports;
245 struct ida decoder_ida;
246 resource_size_t component_reg_phys;
250 * struct cxl_dport - CXL downstream port
251 * @dport: PCI bridge or firmware device representing the downstream link
252 * @port_id: unique hardware identifier for dport in decoder target list
253 * @component_reg_phys: downstream port component registers
254 * @port: reference to cxl_port that contains this downstream port
255 * @list: node for a cxl_port's list of cxl_dport instances
258 struct device *dport;
260 resource_size_t component_reg_phys;
261 struct cxl_port *port;
262 struct list_head list;
265 struct cxl_port *to_cxl_port(struct device *dev);
266 struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
267 resource_size_t component_reg_phys,
268 struct cxl_port *parent_port);
270 int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id,
271 resource_size_t component_reg_phys);
273 struct cxl_decoder *to_cxl_decoder(struct device *dev);
274 bool is_root_decoder(struct device *dev);
276 devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
277 resource_size_t base, resource_size_t len,
278 int interleave_ways, int interleave_granularity,
279 enum cxl_decoder_type type, unsigned long flags);
282 * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
283 * single ported host-bridges need not publish a decoder capability when a
284 * passthrough decode can be assumed, i.e. all transactions that the uport sees
285 * are claimed and passed to the single dport. Default the range a 0-base
286 * 0-length until the first CXL region is activated.
288 static inline struct cxl_decoder *
289 devm_cxl_add_passthrough_decoder(struct device *host, struct cxl_port *port)
291 return devm_cxl_add_decoder(host, port, 1, 0, 0, 1, PAGE_SIZE,
292 CXL_DECODER_EXPANDER, 0);
295 extern struct bus_type cxl_bus_type;
299 int (*probe)(struct device *dev);
300 void (*remove)(struct device *dev);
301 struct device_driver drv;
305 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv)
307 return container_of(drv, struct cxl_driver, drv);
310 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
311 const char *modname);
312 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
313 void cxl_driver_unregister(struct cxl_driver *cxl_drv);
315 #define CXL_DEVICE_NVDIMM_BRIDGE 1
316 #define CXL_DEVICE_NVDIMM 2
318 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
319 #define CXL_MODALIAS_FMT "cxl:t%d"
321 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
322 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
323 struct cxl_port *port);
324 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
325 bool is_cxl_nvdimm(struct device *dev);
326 int devm_cxl_add_nvdimm(struct device *host, struct cxl_memdev *cxlmd);
327 #endif /* __CXL_H__ */