drivers/crypto/sunxi-ss/sun4i-ss-core.c

   1 /*
   2  * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
   3  *
   4  * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
   5  *
   6  * Core file which registers crypto algorithms supported by the SS.
   7  *
   8  * You could find a link for the datasheet in Documentation/arm/sunxi/README
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/crypto.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <crypto/scatterwalk.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/reset.h>
  26
  27 #include "sun4i-ss.h"
  28
  29 static struct sun4i_ss_alg_template ss_algs[] = {
  30 {       .type = CRYPTO_ALG_TYPE_AHASH,
  31         .mode = SS_OP_MD5,
  32         .alg.hash = {
  33                 .init = sun4i_hash_init,
  34                 .update = sun4i_hash_update,
  35                 .final = sun4i_hash_final,
  36                 .finup = sun4i_hash_finup,
  37                 .digest = sun4i_hash_digest,
  38                 .export = sun4i_hash_export_md5,
  39                 .import = sun4i_hash_import_md5,
  40                 .halg = {
  41                         .digestsize = MD5_DIGEST_SIZE,
  42                         .statesize = sizeof(struct md5_state),
  43                         .base = {
  44                                 .cra_name = "md5",
  45                                 .cra_driver_name = "md5-sun4i-ss",
  46                                 .cra_priority = 300,
  47                                 .cra_alignmask = 3,
  48                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH,
  49                                 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
  50                                 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
  51                                 .cra_module = THIS_MODULE,
  52                                 .cra_type = &crypto_ahash_type,
  53                                 .cra_init = sun4i_hash_crainit
  54                         }
  55                 }
  56         }
  57 },
  58 {       .type = CRYPTO_ALG_TYPE_AHASH,
  59         .mode = SS_OP_SHA1,
  60         .alg.hash = {
  61                 .init = sun4i_hash_init,
  62                 .update = sun4i_hash_update,
  63                 .final = sun4i_hash_final,
  64                 .finup = sun4i_hash_finup,
  65                 .digest = sun4i_hash_digest,
  66                 .export = sun4i_hash_export_sha1,
  67                 .import = sun4i_hash_import_sha1,
  68                 .halg = {
  69                         .digestsize = SHA1_DIGEST_SIZE,
  70                         .statesize = sizeof(struct sha1_state),
  71                         .base = {
  72                                 .cra_name = "sha1",
  73                                 .cra_driver_name = "sha1-sun4i-ss",
  74                                 .cra_priority = 300,
  75                                 .cra_alignmask = 3,
  76                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH,
  77                                 .cra_blocksize = SHA1_BLOCK_SIZE,
  78                                 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
  79                                 .cra_module = THIS_MODULE,
  80                                 .cra_type = &crypto_ahash_type,
  81                                 .cra_init = sun4i_hash_crainit
  82                         }
  83                 }
  84         }
  85 },
  86 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
  87         .alg.crypto = {
  88                 .setkey         = sun4i_ss_aes_setkey,
  89                 .encrypt        = sun4i_ss_cbc_aes_encrypt,
  90                 .decrypt        = sun4i_ss_cbc_aes_decrypt,
  91                 .min_keysize    = AES_MIN_KEY_SIZE,
  92                 .max_keysize    = AES_MAX_KEY_SIZE,
  93                 .ivsize         = AES_BLOCK_SIZE,
  94                 .base = {
  95                         .cra_name = "cbc(aes)",
  96                         .cra_driver_name = "cbc-aes-sun4i-ss",
  97                         .cra_priority = 300,
  98                         .cra_blocksize = AES_BLOCK_SIZE,
  99                         .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
 100                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
 101                         .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
 102                         .cra_module = THIS_MODULE,
 103                         .cra_alignmask = 3,
 104                         .cra_init = sun4i_ss_cipher_init,
 105                 }
 106         }
 107 },
 108 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
 109         .alg.crypto = {
 110                 .setkey         = sun4i_ss_aes_setkey,
 111                 .encrypt        = sun4i_ss_ecb_aes_encrypt,
 112                 .decrypt        = sun4i_ss_ecb_aes_decrypt,
 113                 .min_keysize    = AES_MIN_KEY_SIZE,
 114                 .max_keysize    = AES_MAX_KEY_SIZE,
 115                 .ivsize         = AES_BLOCK_SIZE,
 116                 .base = {
 117                         .cra_name = "ecb(aes)",
 118                         .cra_driver_name = "ecb-aes-sun4i-ss",
 119                         .cra_priority = 300,
 120                         .cra_blocksize = AES_BLOCK_SIZE,
 121                         .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
 122                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
 123                         .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
 124                         .cra_module = THIS_MODULE,
 125                         .cra_alignmask = 3,
 126                         .cra_init = sun4i_ss_cipher_init,
 127                 }
 128         }
 129 },
 130 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
 131         .alg.crypto = {
 132                 .setkey         = sun4i_ss_des_setkey,
 133                 .encrypt        = sun4i_ss_cbc_des_encrypt,
 134                 .decrypt        = sun4i_ss_cbc_des_decrypt,
 135                 .min_keysize    = DES_KEY_SIZE,
 136                 .max_keysize    = DES_KEY_SIZE,
 137                 .ivsize         = DES_BLOCK_SIZE,
 138                 .base = {
 139                         .cra_name = "cbc(des)",
 140                         .cra_driver_name = "cbc-des-sun4i-ss",
 141                         .cra_priority = 300,
 142                         .cra_blocksize = DES_BLOCK_SIZE,
 143                         .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
 144                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
 145                         .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 146                         .cra_module = THIS_MODULE,
 147                         .cra_alignmask = 3,
 148                         .cra_init = sun4i_ss_cipher_init,
 149                 }
 150         }
 151 },
 152 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
 153         .alg.crypto = {
 154                 .setkey         = sun4i_ss_des_setkey,
 155                 .encrypt        = sun4i_ss_ecb_des_encrypt,
 156                 .decrypt        = sun4i_ss_ecb_des_decrypt,
 157                 .min_keysize    = DES_KEY_SIZE,
 158                 .max_keysize    = DES_KEY_SIZE,
 159                 .base = {
 160                         .cra_name = "ecb(des)",
 161                         .cra_driver_name = "ecb-des-sun4i-ss",
 162                         .cra_priority = 300,
 163                         .cra_blocksize = DES_BLOCK_SIZE,
 164                         .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
 165                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
 166                         .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 167                         .cra_module = THIS_MODULE,
 168                         .cra_alignmask = 3,
 169                         .cra_init = sun4i_ss_cipher_init,
 170                 }
 171         }
 172 },
 173 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
 174         .alg.crypto = {
 175                 .setkey         = sun4i_ss_des3_setkey,
 176                 .encrypt        = sun4i_ss_cbc_des3_encrypt,
 177                 .decrypt        = sun4i_ss_cbc_des3_decrypt,
 178                 .min_keysize    = DES3_EDE_KEY_SIZE,
 179                 .max_keysize    = DES3_EDE_KEY_SIZE,
 180                 .ivsize         = DES3_EDE_BLOCK_SIZE,
 181                 .base = {
 182                         .cra_name = "cbc(des3_ede)",
 183                         .cra_driver_name = "cbc-des3-sun4i-ss",
 184                         .cra_priority = 300,
 185                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
 186                         .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
 187                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
 188                         .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 189                         .cra_module = THIS_MODULE,
 190                         .cra_alignmask = 3,
 191                         .cra_init = sun4i_ss_cipher_init,
 192                 }
 193         }
 194 },
 195 {       .type = CRYPTO_ALG_TYPE_SKCIPHER,
 196         .alg.crypto = {
 197                 .setkey         = sun4i_ss_des3_setkey,
 198                 .encrypt        = sun4i_ss_ecb_des3_encrypt,
 199                 .decrypt        = sun4i_ss_ecb_des3_decrypt,
 200                 .min_keysize    = DES3_EDE_KEY_SIZE,
 201                 .max_keysize    = DES3_EDE_KEY_SIZE,
 202                 .ivsize         = DES3_EDE_BLOCK_SIZE,
 203                 .base = {
 204                         .cra_name = "ecb(des3_ede)",
 205                         .cra_driver_name = "ecb-des3-sun4i-ss",
 206                         .cra_priority = 300,
 207                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
 208                         .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER,
 209                         .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 210                         .cra_module = THIS_MODULE,
 211                         .cra_alignmask = 3,
 212                         .cra_init = sun4i_ss_cipher_init,
 213                 }
 214         }
 215 },
 216 };
 217
 218 static int sun4i_ss_probe(struct platform_device *pdev)
 219 {
 220         struct resource *res;
 221         u32 v;
 222         int err, i;
 223         unsigned long cr;
 224         const unsigned long cr_ahb = 24 * 1000 * 1000;
 225         const unsigned long cr_mod = 150 * 1000 * 1000;
 226         struct sun4i_ss_ctx *ss;
 227
 228         if (!pdev->dev.of_node)
 229                 return -ENODEV;
 230
 231         ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
 232         if (!ss)
 233                 return -ENOMEM;
 234
 235         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 236         ss->base = devm_ioremap_resource(&pdev->dev, res);
 237         if (IS_ERR(ss->base)) {
 238                 dev_err(&pdev->dev, "Cannot request MMIO\n");
 239                 return PTR_ERR(ss->base);
 240         }
 241
 242         ss->ssclk = devm_clk_get(&pdev->dev, "mod");
 243         if (IS_ERR(ss->ssclk)) {
 244                 err = PTR_ERR(ss->ssclk);
 245                 dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
 246                 return err;
 247         }
 248         dev_dbg(&pdev->dev, "clock ss acquired\n");
 249
 250         ss->busclk = devm_clk_get(&pdev->dev, "ahb");
 251         if (IS_ERR(ss->busclk)) {
 252                 err = PTR_ERR(ss->busclk);
 253                 dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
 254                 return err;
 255         }
 256         dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
 257
 258         ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
 259         if (IS_ERR(ss->reset)) {
 260                 if (PTR_ERR(ss->reset) == -EPROBE_DEFER)
 261                         return PTR_ERR(ss->reset);
 262                 dev_info(&pdev->dev, "no reset control found\n");
 263                 ss->reset = NULL;
 264         }
 265
 266         /* Enable both clocks */
 267         err = clk_prepare_enable(ss->busclk);
 268         if (err) {
 269                 dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
 270                 return err;
 271         }
 272         err = clk_prepare_enable(ss->ssclk);
 273         if (err) {
 274                 dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
 275                 goto error_ssclk;
 276         }
 277
 278         /*
 279          * Check that clock have the correct rates given in the datasheet
 280          * Try to set the clock to the maximum allowed
 281          */
 282         err = clk_set_rate(ss->ssclk, cr_mod);
 283         if (err) {
 284                 dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
 285                 goto error_clk;
 286         }
 287
 288         /* Deassert reset if we have a reset control */
 289         if (ss->reset) {
 290                 err = reset_control_deassert(ss->reset);
 291                 if (err) {
 292                         dev_err(&pdev->dev, "Cannot deassert reset control\n");
 293                         goto error_clk;
 294                 }
 295         }
 296
 297         /*
 298          * The only impact on clocks below requirement are bad performance,
 299          * so do not print "errors"
 300          * warn on Overclocked clocks
 301          */
 302         cr = clk_get_rate(ss->busclk);
 303         if (cr >= cr_ahb)
 304                 dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
 305                         cr, cr / 1000000, cr_ahb);
 306         else
 307                 dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
 308                          cr, cr / 1000000, cr_ahb);
 309
 310         cr = clk_get_rate(ss->ssclk);
 311         if (cr <= cr_mod)
 312                 if (cr < cr_mod)
 313                         dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
 314                                  cr, cr / 1000000, cr_mod);
 315                 else
 316                         dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
 317                                 cr, cr / 1000000, cr_mod);
 318         else
 319                 dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
 320                          cr, cr / 1000000, cr_mod);
 321
 322         /*
 323          * Datasheet named it "Die Bonding ID"
 324          * I expect to be a sort of Security System Revision number.
 325          * Since the A80 seems to have an other version of SS
 326          * this info could be useful
 327          */
 328         writel(SS_ENABLED, ss->base + SS_CTL);
 329         v = readl(ss->base + SS_CTL);
 330         v >>= 16;
 331         v &= 0x07;
 332         dev_info(&pdev->dev, "Die ID %d\n", v);
 333         writel(0, ss->base + SS_CTL);
 334
 335         ss->dev = &pdev->dev;
 336
 337         spin_lock_init(&ss->slock);
 338
 339         for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
 340                 ss_algs[i].ss = ss;
 341                 switch (ss_algs[i].type) {
 342                 case CRYPTO_ALG_TYPE_SKCIPHER:
 343                         err = crypto_register_skcipher(&ss_algs[i].alg.crypto);
 344                         if (err) {
 345                                 dev_err(ss->dev, "Fail to register %s\n",
 346                                         ss_algs[i].alg.crypto.base.cra_name);
 347                                 goto error_alg;
 348                         }
 349                         break;
 350                 case CRYPTO_ALG_TYPE_AHASH:
 351                         err = crypto_register_ahash(&ss_algs[i].alg.hash);
 352                         if (err) {
 353                                 dev_err(ss->dev, "Fail to register %s\n",
 354                                         ss_algs[i].alg.hash.halg.base.cra_name);
 355                                 goto error_alg;
 356                         }
 357                         break;
 358                 }
 359         }
 360         platform_set_drvdata(pdev, ss);
 361         return 0;
 362 error_alg:
 363         i--;
 364         for (; i >= 0; i--) {
 365                 switch (ss_algs[i].type) {
 366                 case CRYPTO_ALG_TYPE_SKCIPHER:
 367                         crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
 368                         break;
 369                 case CRYPTO_ALG_TYPE_AHASH:
 370                         crypto_unregister_ahash(&ss_algs[i].alg.hash);
 371                         break;
 372                 }
 373         }
 374         if (ss->reset)
 375                 reset_control_assert(ss->reset);
 376 error_clk:
 377         clk_disable_unprepare(ss->ssclk);
 378 error_ssclk:
 379         clk_disable_unprepare(ss->busclk);
 380         return err;
 381 }
 382
 383 static int sun4i_ss_remove(struct platform_device *pdev)
 384 {
 385         int i;
 386         struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev);
 387
 388         for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
 389                 switch (ss_algs[i].type) {
 390                 case CRYPTO_ALG_TYPE_SKCIPHER:
 391                         crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
 392                         break;
 393                 case CRYPTO_ALG_TYPE_AHASH:
 394                         crypto_unregister_ahash(&ss_algs[i].alg.hash);
 395                         break;
 396                 }
 397         }
 398
 399         writel(0, ss->base + SS_CTL);
 400         if (ss->reset)
 401                 reset_control_assert(ss->reset);
 402         clk_disable_unprepare(ss->busclk);
 403         clk_disable_unprepare(ss->ssclk);
 404         return 0;
 405 }
 406
 407 static const struct of_device_id a20ss_crypto_of_match_table[] = {
 408         { .compatible = "allwinner,sun4i-a10-crypto" },
 409         {}
 410 };
 411 MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
 412
 413 static struct platform_driver sun4i_ss_driver = {
 414         .probe          = sun4i_ss_probe,
 415         .remove         = sun4i_ss_remove,
 416         .driver         = {
 417                 .name           = "sun4i-ss",
 418                 .of_match_table = a20ss_crypto_of_match_table,
 419         },
 420 };
 421
 422 module_platform_driver(sun4i_ss_driver);
 423
 424 MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
 425 MODULE_LICENSE("GPL");
 426 MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");