1 // SPDX-License-Identifier: GPL-2.0
5 // Support for Samsung S5PV210 and Exynos HW acceleration.
7 // Copyright (C) 2011 NetUP Inc. All rights reserved.
8 // Copyright (c) 2017 Samsung Electronics Co., Ltd. All rights reserved.
10 // Hash part based on omap-sham.c driver.
12 #include <linux/clk.h>
13 #include <linux/crypto.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/scatterlist.h>
26 #include <crypto/ctr.h>
27 #include <crypto/aes.h>
28 #include <crypto/algapi.h>
29 #include <crypto/scatterwalk.h>
31 #include <crypto/hash.h>
32 #include <crypto/md5.h>
33 #include <crypto/sha.h>
34 #include <crypto/internal/hash.h>
36 #define _SBF(s, v) ((v) << (s))
38 /* Feed control registers */
39 #define SSS_REG_FCINTSTAT 0x0000
40 #define SSS_FCINTSTAT_HPARTINT BIT(7)
41 #define SSS_FCINTSTAT_HDONEINT BIT(5)
42 #define SSS_FCINTSTAT_BRDMAINT BIT(3)
43 #define SSS_FCINTSTAT_BTDMAINT BIT(2)
44 #define SSS_FCINTSTAT_HRDMAINT BIT(1)
45 #define SSS_FCINTSTAT_PKDMAINT BIT(0)
47 #define SSS_REG_FCINTENSET 0x0004
48 #define SSS_FCINTENSET_HPARTINTENSET BIT(7)
49 #define SSS_FCINTENSET_HDONEINTENSET BIT(5)
50 #define SSS_FCINTENSET_BRDMAINTENSET BIT(3)
51 #define SSS_FCINTENSET_BTDMAINTENSET BIT(2)
52 #define SSS_FCINTENSET_HRDMAINTENSET BIT(1)
53 #define SSS_FCINTENSET_PKDMAINTENSET BIT(0)
55 #define SSS_REG_FCINTENCLR 0x0008
56 #define SSS_FCINTENCLR_HPARTINTENCLR BIT(7)
57 #define SSS_FCINTENCLR_HDONEINTENCLR BIT(5)
58 #define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3)
59 #define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2)
60 #define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1)
61 #define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0)
63 #define SSS_REG_FCINTPEND 0x000C
64 #define SSS_FCINTPEND_HPARTINTP BIT(7)
65 #define SSS_FCINTPEND_HDONEINTP BIT(5)
66 #define SSS_FCINTPEND_BRDMAINTP BIT(3)
67 #define SSS_FCINTPEND_BTDMAINTP BIT(2)
68 #define SSS_FCINTPEND_HRDMAINTP BIT(1)
69 #define SSS_FCINTPEND_PKDMAINTP BIT(0)
71 #define SSS_REG_FCFIFOSTAT 0x0010
72 #define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7)
73 #define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6)
74 #define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5)
75 #define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4)
76 #define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3)
77 #define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2)
78 #define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1)
79 #define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0)
81 #define SSS_REG_FCFIFOCTRL 0x0014
82 #define SSS_FCFIFOCTRL_DESSEL BIT(2)
83 #define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00)
84 #define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01)
85 #define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02)
86 #define SSS_HASHIN_MASK _SBF(0, 0x03)
88 #define SSS_REG_FCBRDMAS 0x0020
89 #define SSS_REG_FCBRDMAL 0x0024
90 #define SSS_REG_FCBRDMAC 0x0028
91 #define SSS_FCBRDMAC_BYTESWAP BIT(1)
92 #define SSS_FCBRDMAC_FLUSH BIT(0)
94 #define SSS_REG_FCBTDMAS 0x0030
95 #define SSS_REG_FCBTDMAL 0x0034
96 #define SSS_REG_FCBTDMAC 0x0038
97 #define SSS_FCBTDMAC_BYTESWAP BIT(1)
98 #define SSS_FCBTDMAC_FLUSH BIT(0)
100 #define SSS_REG_FCHRDMAS 0x0040
101 #define SSS_REG_FCHRDMAL 0x0044
102 #define SSS_REG_FCHRDMAC 0x0048
103 #define SSS_FCHRDMAC_BYTESWAP BIT(1)
104 #define SSS_FCHRDMAC_FLUSH BIT(0)
106 #define SSS_REG_FCPKDMAS 0x0050
107 #define SSS_REG_FCPKDMAL 0x0054
108 #define SSS_REG_FCPKDMAC 0x0058
109 #define SSS_FCPKDMAC_BYTESWAP BIT(3)
110 #define SSS_FCPKDMAC_DESCEND BIT(2)
111 #define SSS_FCPKDMAC_TRANSMIT BIT(1)
112 #define SSS_FCPKDMAC_FLUSH BIT(0)
114 #define SSS_REG_FCPKDMAO 0x005C
117 #define SSS_REG_AES_CONTROL 0x00
118 #define SSS_AES_BYTESWAP_DI BIT(11)
119 #define SSS_AES_BYTESWAP_DO BIT(10)
120 #define SSS_AES_BYTESWAP_IV BIT(9)
121 #define SSS_AES_BYTESWAP_CNT BIT(8)
122 #define SSS_AES_BYTESWAP_KEY BIT(7)
123 #define SSS_AES_KEY_CHANGE_MODE BIT(6)
124 #define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00)
125 #define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01)
126 #define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02)
127 #define SSS_AES_FIFO_MODE BIT(3)
128 #define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00)
129 #define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01)
130 #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
131 #define SSS_AES_MODE_DECRYPT BIT(0)
133 #define SSS_REG_AES_STATUS 0x04
134 #define SSS_AES_BUSY BIT(2)
135 #define SSS_AES_INPUT_READY BIT(1)
136 #define SSS_AES_OUTPUT_READY BIT(0)
138 #define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
139 #define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
140 #define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
141 #define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
142 #define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))
144 #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
145 #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
146 #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
148 #define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
149 #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
150 SSS_AES_REG(dev, reg))
152 /* HW engine modes */
153 #define FLAGS_AES_DECRYPT BIT(0)
154 #define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
155 #define FLAGS_AES_CBC _SBF(1, 0x01)
156 #define FLAGS_AES_CTR _SBF(1, 0x02)
158 #define AES_KEY_LEN 16
159 #define CRYPTO_QUEUE_LEN 1
162 #define SSS_REG_HASH_CTRL 0x00
164 #define SSS_HASH_USER_IV_EN BIT(5)
165 #define SSS_HASH_INIT_BIT BIT(4)
166 #define SSS_HASH_ENGINE_SHA1 _SBF(1, 0x00)
167 #define SSS_HASH_ENGINE_MD5 _SBF(1, 0x01)
168 #define SSS_HASH_ENGINE_SHA256 _SBF(1, 0x02)
170 #define SSS_HASH_ENGINE_MASK _SBF(1, 0x03)
172 #define SSS_REG_HASH_CTRL_PAUSE 0x04
174 #define SSS_HASH_PAUSE BIT(0)
176 #define SSS_REG_HASH_CTRL_FIFO 0x08
178 #define SSS_HASH_FIFO_MODE_DMA BIT(0)
179 #define SSS_HASH_FIFO_MODE_CPU 0
181 #define SSS_REG_HASH_CTRL_SWAP 0x0C
183 #define SSS_HASH_BYTESWAP_DI BIT(3)
184 #define SSS_HASH_BYTESWAP_DO BIT(2)
185 #define SSS_HASH_BYTESWAP_IV BIT(1)
186 #define SSS_HASH_BYTESWAP_KEY BIT(0)
188 #define SSS_REG_HASH_STATUS 0x10
190 #define SSS_HASH_STATUS_MSG_DONE BIT(6)
191 #define SSS_HASH_STATUS_PARTIAL_DONE BIT(4)
192 #define SSS_HASH_STATUS_BUFFER_READY BIT(0)
194 #define SSS_REG_HASH_MSG_SIZE_LOW 0x20
195 #define SSS_REG_HASH_MSG_SIZE_HIGH 0x24
197 #define SSS_REG_HASH_PRE_MSG_SIZE_LOW 0x28
198 #define SSS_REG_HASH_PRE_MSG_SIZE_HIGH 0x2C
200 #define SSS_REG_HASH_IV(s) (0xB0 + ((s) << 2))
201 #define SSS_REG_HASH_OUT(s) (0x100 + ((s) << 2))
203 #define HASH_BLOCK_SIZE 64
204 #define HASH_REG_SIZEOF 4
205 #define HASH_MD5_MAX_REG (MD5_DIGEST_SIZE / HASH_REG_SIZEOF)
206 #define HASH_SHA1_MAX_REG (SHA1_DIGEST_SIZE / HASH_REG_SIZEOF)
207 #define HASH_SHA256_MAX_REG (SHA256_DIGEST_SIZE / HASH_REG_SIZEOF)
210 * HASH bit numbers, used by device, setting in dev->hash_flags with
211 * functions set_bit(), clear_bit() or tested with test_bit() or BIT(),
212 * to keep HASH state BUSY or FREE, or to signal state from irq_handler
213 * to hash_tasklet. SGS keep track of allocated memory for scatterlist
215 #define HASH_FLAGS_BUSY 0
216 #define HASH_FLAGS_FINAL 1
217 #define HASH_FLAGS_DMA_ACTIVE 2
218 #define HASH_FLAGS_OUTPUT_READY 3
219 #define HASH_FLAGS_DMA_READY 4
220 #define HASH_FLAGS_SGS_COPIED 5
221 #define HASH_FLAGS_SGS_ALLOCED 6
223 /* HASH HW constants */
224 #define BUFLEN HASH_BLOCK_SIZE
226 #define SSS_HASH_DMA_LEN_ALIGN 8
227 #define SSS_HASH_DMA_ALIGN_MASK (SSS_HASH_DMA_LEN_ALIGN - 1)
229 #define SSS_HASH_QUEUE_LENGTH 10
232 * struct samsung_aes_variant - platform specific SSS driver data
233 * @aes_offset: AES register offset from SSS module's base.
234 * @hash_offset: HASH register offset from SSS module's base.
236 * Specifies platform specific configuration of SSS module.
237 * Note: A structure for driver specific platform data is used for future
238 * expansion of its usage.
240 struct samsung_aes_variant {
241 unsigned int aes_offset;
242 unsigned int hash_offset;
245 struct s5p_aes_reqctx {
250 struct s5p_aes_dev *dev;
252 u8 aes_key[AES_MAX_KEY_SIZE];
253 u8 nonce[CTR_RFC3686_NONCE_SIZE];
258 * struct s5p_aes_dev - Crypto device state container
259 * @dev: Associated device
260 * @clk: Clock for accessing hardware
261 * @ioaddr: Mapped IO memory region
262 * @aes_ioaddr: Per-varian offset for AES block IO memory
263 * @irq_fc: Feed control interrupt line
264 * @req: Crypto request currently handled by the device
265 * @ctx: Configuration for currently handled crypto request
266 * @sg_src: Scatter list with source data for currently handled block
267 * in device. This is DMA-mapped into device.
268 * @sg_dst: Scatter list with destination data for currently handled block
269 * in device. This is DMA-mapped into device.
270 * @sg_src_cpy: In case of unaligned access, copied scatter list
272 * @sg_dst_cpy: In case of unaligned access, copied scatter list
273 * with destination data.
274 * @tasklet: New request scheduling jib
275 * @queue: Crypto queue
276 * @busy: Indicates whether the device is currently handling some request
277 * thus it uses some of the fields from this state, like:
278 * req, ctx, sg_src/dst (and copies). This essentially
279 * protects against concurrent access to these fields.
280 * @lock: Lock for protecting both access to device hardware registers
281 * and fields related to current request (including the busy field).
282 * @res: Resources for hash.
283 * @io_hash_base: Per-variant offset for HASH block IO memory.
284 * @hash_lock: Lock for protecting hash_req, hash_queue and hash_flags
286 * @hash_flags: Flags for current HASH op.
287 * @hash_queue: Async hash queue.
288 * @hash_tasklet: New HASH request scheduling job.
289 * @xmit_buf: Buffer for current HASH request transfer into SSS block.
290 * @hash_req: Current request sending to SSS HASH block.
291 * @hash_sg_iter: Scatterlist transferred through DMA into SSS HASH block.
292 * @hash_sg_cnt: Counter for hash_sg_iter.
294 * @use_hash: true if HASH algs enabled
299 void __iomem *ioaddr;
300 void __iomem *aes_ioaddr;
303 struct ablkcipher_request *req;
304 struct s5p_aes_ctx *ctx;
305 struct scatterlist *sg_src;
306 struct scatterlist *sg_dst;
308 struct scatterlist *sg_src_cpy;
309 struct scatterlist *sg_dst_cpy;
311 struct tasklet_struct tasklet;
312 struct crypto_queue queue;
316 struct resource *res;
317 void __iomem *io_hash_base;
319 spinlock_t hash_lock; /* protect hash_ vars */
320 unsigned long hash_flags;
321 struct crypto_queue hash_queue;
322 struct tasklet_struct hash_tasklet;
325 struct ahash_request *hash_req;
326 struct scatterlist *hash_sg_iter;
327 unsigned int hash_sg_cnt;
333 * struct s5p_hash_reqctx - HASH request context
334 * @dd: Associated device
335 * @op_update: Current request operation (OP_UPDATE or OP_FINAL)
336 * @digcnt: Number of bytes processed by HW (without buffer[] ones)
337 * @digest: Digest message or IV for partial result
338 * @nregs: Number of HW registers for digest or IV read/write
339 * @engine: Bits for selecting type of HASH in SSS block
340 * @sg: sg for DMA transfer
341 * @sg_len: Length of sg for DMA transfer
342 * @sgl[]: sg for joining buffer and req->src scatterlist
343 * @skip: Skip offset in req->src for current op
344 * @total: Total number of bytes for current request
345 * @finup: Keep state for finup or final.
346 * @error: Keep track of error.
347 * @bufcnt: Number of bytes holded in buffer[]
348 * @buffer[]: For byte(s) from end of req->src in UPDATE op
350 struct s5p_hash_reqctx {
351 struct s5p_aes_dev *dd;
355 u8 digest[SHA256_DIGEST_SIZE];
357 unsigned int nregs; /* digest_size / sizeof(reg) */
360 struct scatterlist *sg;
362 struct scatterlist sgl[2];
373 * struct s5p_hash_ctx - HASH transformation context
374 * @dd: Associated device
375 * @flags: Bits for algorithm HASH.
376 * @fallback: Software transformation for zero message or size < BUFLEN.
378 struct s5p_hash_ctx {
379 struct s5p_aes_dev *dd;
381 struct crypto_shash *fallback;
384 static const struct samsung_aes_variant s5p_aes_data = {
385 .aes_offset = 0x4000,
386 .hash_offset = 0x6000,
389 static const struct samsung_aes_variant exynos_aes_data = {
391 .hash_offset = 0x400,
394 static const struct of_device_id s5p_sss_dt_match[] = {
396 .compatible = "samsung,s5pv210-secss",
397 .data = &s5p_aes_data,
400 .compatible = "samsung,exynos4210-secss",
401 .data = &exynos_aes_data,
405 MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
407 static inline const struct samsung_aes_variant *find_s5p_sss_version
408 (const struct platform_device *pdev)
410 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
411 const struct of_device_id *match;
413 match = of_match_node(s5p_sss_dt_match,
415 return (const struct samsung_aes_variant *)match->data;
417 return (const struct samsung_aes_variant *)
418 platform_get_device_id(pdev)->driver_data;
421 static struct s5p_aes_dev *s5p_dev;
423 static void s5p_set_dma_indata(struct s5p_aes_dev *dev,
424 const struct scatterlist *sg)
426 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
427 SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg));
430 static void s5p_set_dma_outdata(struct s5p_aes_dev *dev,
431 const struct scatterlist *sg)
433 SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg));
434 SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg));
437 static void s5p_free_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist **sg)
444 len = ALIGN(dev->req->nbytes, AES_BLOCK_SIZE);
445 free_pages((unsigned long)sg_virt(*sg), get_order(len));
451 static void s5p_sg_copy_buf(void *buf, struct scatterlist *sg,
452 unsigned int nbytes, int out)
454 struct scatter_walk walk;
459 scatterwalk_start(&walk, sg);
460 scatterwalk_copychunks(buf, &walk, nbytes, out);
461 scatterwalk_done(&walk, out, 0);
464 static void s5p_sg_done(struct s5p_aes_dev *dev)
466 if (dev->sg_dst_cpy) {
468 "Copying %d bytes of output data back to original place\n",
470 s5p_sg_copy_buf(sg_virt(dev->sg_dst_cpy), dev->req->dst,
471 dev->req->nbytes, 1);
473 s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
474 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
477 /* Calls the completion. Cannot be called with dev->lock hold. */
478 static void s5p_aes_complete(struct ablkcipher_request *req, int err)
480 req->base.complete(&req->base, err);
483 static void s5p_unset_outdata(struct s5p_aes_dev *dev)
485 dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE);
488 static void s5p_unset_indata(struct s5p_aes_dev *dev)
490 dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE);
493 static int s5p_make_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist *src,
494 struct scatterlist **dst)
499 *dst = kmalloc(sizeof(**dst), GFP_ATOMIC);
503 len = ALIGN(dev->req->nbytes, AES_BLOCK_SIZE);
504 pages = (void *)__get_free_pages(GFP_ATOMIC, get_order(len));
511 s5p_sg_copy_buf(pages, src, dev->req->nbytes, 0);
513 sg_init_table(*dst, 1);
514 sg_set_buf(*dst, pages, len);
519 static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg)
524 if (!dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE))
532 static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
537 if (!dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE))
546 * Returns -ERRNO on error (mapping of new data failed).
547 * On success returns:
548 * - 0 if there is no more data,
549 * - 1 if new transmitting (output) data is ready and its address+length
550 * have to be written to device (by calling s5p_set_dma_outdata()).
552 static int s5p_aes_tx(struct s5p_aes_dev *dev)
556 s5p_unset_outdata(dev);
558 if (!sg_is_last(dev->sg_dst)) {
559 ret = s5p_set_outdata(dev, sg_next(dev->sg_dst));
568 * Returns -ERRNO on error (mapping of new data failed).
569 * On success returns:
570 * - 0 if there is no more data,
571 * - 1 if new receiving (input) data is ready and its address+length
572 * have to be written to device (by calling s5p_set_dma_indata()).
574 static int s5p_aes_rx(struct s5p_aes_dev *dev/*, bool *set_dma*/)
578 s5p_unset_indata(dev);
580 if (!sg_is_last(dev->sg_src)) {
581 ret = s5p_set_indata(dev, sg_next(dev->sg_src));
589 static inline u32 s5p_hash_read(struct s5p_aes_dev *dd, u32 offset)
591 return __raw_readl(dd->io_hash_base + offset);
594 static inline void s5p_hash_write(struct s5p_aes_dev *dd,
595 u32 offset, u32 value)
597 __raw_writel(value, dd->io_hash_base + offset);
601 * s5p_set_dma_hashdata() - start DMA with sg
603 * @sg: scatterlist ready to DMA transmit
605 static void s5p_set_dma_hashdata(struct s5p_aes_dev *dev,
606 const struct scatterlist *sg)
609 SSS_WRITE(dev, FCHRDMAS, sg_dma_address(sg));
610 SSS_WRITE(dev, FCHRDMAL, sg_dma_len(sg)); /* DMA starts */
614 * s5p_hash_rx() - get next hash_sg_iter
618 * 2 if there is no more data and it is UPDATE op
619 * 1 if new receiving (input) data is ready and can be written to device
620 * 0 if there is no more data and it is FINAL op
622 static int s5p_hash_rx(struct s5p_aes_dev *dev)
624 if (dev->hash_sg_cnt > 0) {
625 dev->hash_sg_iter = sg_next(dev->hash_sg_iter);
629 set_bit(HASH_FLAGS_DMA_READY, &dev->hash_flags);
630 if (test_bit(HASH_FLAGS_FINAL, &dev->hash_flags))
636 static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id)
638 struct platform_device *pdev = dev_id;
639 struct s5p_aes_dev *dev = platform_get_drvdata(pdev);
640 struct ablkcipher_request *req;
650 spin_lock_irqsave(&dev->lock, flags);
653 * Handle rx or tx interrupt. If there is still data (scatterlist did not
654 * reach end), then map next scatterlist entry.
655 * In case of such mapping error, s5p_aes_complete() should be called.
657 * If there is no more data in tx scatter list, call s5p_aes_complete()
658 * and schedule new tasklet.
660 * Handle hx interrupt. If there is still data map next entry.
662 status = SSS_READ(dev, FCINTSTAT);
663 if (status & SSS_FCINTSTAT_BRDMAINT)
664 err_dma_rx = s5p_aes_rx(dev);
666 if (status & SSS_FCINTSTAT_BTDMAINT) {
667 if (sg_is_last(dev->sg_dst))
669 err_dma_tx = s5p_aes_tx(dev);
672 if (status & SSS_FCINTSTAT_HRDMAINT)
673 err_dma_hx = s5p_hash_rx(dev);
675 st_bits = status & (SSS_FCINTSTAT_BRDMAINT | SSS_FCINTSTAT_BTDMAINT |
676 SSS_FCINTSTAT_HRDMAINT);
678 SSS_WRITE(dev, FCINTPEND, st_bits);
680 /* clear HASH irq bits */
681 if (status & (SSS_FCINTSTAT_HDONEINT | SSS_FCINTSTAT_HPARTINT)) {
682 /* cannot have both HPART and HDONE */
683 if (status & SSS_FCINTSTAT_HPARTINT)
684 st_bits = SSS_HASH_STATUS_PARTIAL_DONE;
686 if (status & SSS_FCINTSTAT_HDONEINT)
687 st_bits = SSS_HASH_STATUS_MSG_DONE;
689 set_bit(HASH_FLAGS_OUTPUT_READY, &dev->hash_flags);
690 s5p_hash_write(dev, SSS_REG_HASH_STATUS, st_bits);
692 /* when DONE or PART, do not handle HASH DMA */
696 if (err_dma_rx < 0) {
700 if (err_dma_tx < 0) {
708 s5p_set_dma_hashdata(dev, dev->hash_sg_iter);
710 spin_unlock_irqrestore(&dev->lock, flags);
712 s5p_aes_complete(dev->req, 0);
713 /* Device is still busy */
714 tasklet_schedule(&dev->tasklet);
717 * Writing length of DMA block (either receiving or
718 * transmitting) will start the operation immediately, so this
719 * should be done at the end (even after clearing pending
720 * interrupts to not miss the interrupt).
723 s5p_set_dma_outdata(dev, dev->sg_dst);
725 s5p_set_dma_indata(dev, dev->sg_src);
727 s5p_set_dma_hashdata(dev, dev->hash_sg_iter);
729 spin_unlock_irqrestore(&dev->lock, flags);
739 s5p_set_dma_hashdata(dev, dev->hash_sg_iter);
741 spin_unlock_irqrestore(&dev->lock, flags);
742 s5p_aes_complete(req, err);
746 * Note about else if:
747 * when hash_sg_iter reaches end and its UPDATE op,
748 * issue SSS_HASH_PAUSE and wait for HPART irq
751 tasklet_schedule(&dev->hash_tasklet);
752 else if (err_dma_hx == 2)
753 s5p_hash_write(dev, SSS_REG_HASH_CTRL_PAUSE,
760 * s5p_hash_read_msg() - read message or IV from HW
761 * @req: AHASH request
763 static void s5p_hash_read_msg(struct ahash_request *req)
765 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
766 struct s5p_aes_dev *dd = ctx->dd;
767 u32 *hash = (u32 *)ctx->digest;
770 for (i = 0; i < ctx->nregs; i++)
771 hash[i] = s5p_hash_read(dd, SSS_REG_HASH_OUT(i));
775 * s5p_hash_write_ctx_iv() - write IV for next partial/finup op.
777 * @ctx: request context
779 static void s5p_hash_write_ctx_iv(struct s5p_aes_dev *dd,
780 const struct s5p_hash_reqctx *ctx)
782 const u32 *hash = (const u32 *)ctx->digest;
785 for (i = 0; i < ctx->nregs; i++)
786 s5p_hash_write(dd, SSS_REG_HASH_IV(i), hash[i]);
790 * s5p_hash_write_iv() - write IV for next partial/finup op.
791 * @req: AHASH request
793 static void s5p_hash_write_iv(struct ahash_request *req)
795 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
797 s5p_hash_write_ctx_iv(ctx->dd, ctx);
801 * s5p_hash_copy_result() - copy digest into req->result
802 * @req: AHASH request
804 static void s5p_hash_copy_result(struct ahash_request *req)
806 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
811 memcpy(req->result, ctx->digest, ctx->nregs * HASH_REG_SIZEOF);
815 * s5p_hash_dma_flush() - flush HASH DMA
818 static void s5p_hash_dma_flush(struct s5p_aes_dev *dev)
820 SSS_WRITE(dev, FCHRDMAC, SSS_FCHRDMAC_FLUSH);
824 * s5p_hash_dma_enable() - enable DMA mode for HASH
827 * enable DMA mode for HASH
829 static void s5p_hash_dma_enable(struct s5p_aes_dev *dev)
831 s5p_hash_write(dev, SSS_REG_HASH_CTRL_FIFO, SSS_HASH_FIFO_MODE_DMA);
835 * s5p_hash_irq_disable() - disable irq HASH signals
837 * @flags: bitfield with irq's to be disabled
839 static void s5p_hash_irq_disable(struct s5p_aes_dev *dev, u32 flags)
841 SSS_WRITE(dev, FCINTENCLR, flags);
845 * s5p_hash_irq_enable() - enable irq signals
847 * @flags: bitfield with irq's to be enabled
849 static void s5p_hash_irq_enable(struct s5p_aes_dev *dev, int flags)
851 SSS_WRITE(dev, FCINTENSET, flags);
855 * s5p_hash_set_flow() - set flow inside SecSS AES/DES with/without HASH
857 * @hashflow: HASH stream flow with/without crypto AES/DES
859 static void s5p_hash_set_flow(struct s5p_aes_dev *dev, u32 hashflow)
864 spin_lock_irqsave(&dev->lock, flags);
866 flow = SSS_READ(dev, FCFIFOCTRL);
867 flow &= ~SSS_HASHIN_MASK;
869 SSS_WRITE(dev, FCFIFOCTRL, flow);
871 spin_unlock_irqrestore(&dev->lock, flags);
875 * s5p_ahash_dma_init() - enable DMA and set HASH flow inside SecSS
877 * @hashflow: HASH stream flow with/without AES/DES
879 * flush HASH DMA and enable DMA, set HASH stream flow inside SecSS HW,
880 * enable HASH irq's HRDMA, HDONE, HPART
882 static void s5p_ahash_dma_init(struct s5p_aes_dev *dev, u32 hashflow)
884 s5p_hash_irq_disable(dev, SSS_FCINTENCLR_HRDMAINTENCLR |
885 SSS_FCINTENCLR_HDONEINTENCLR |
886 SSS_FCINTENCLR_HPARTINTENCLR);
887 s5p_hash_dma_flush(dev);
889 s5p_hash_dma_enable(dev);
890 s5p_hash_set_flow(dev, hashflow & SSS_HASHIN_MASK);
891 s5p_hash_irq_enable(dev, SSS_FCINTENSET_HRDMAINTENSET |
892 SSS_FCINTENSET_HDONEINTENSET |
893 SSS_FCINTENSET_HPARTINTENSET);
897 * s5p_hash_write_ctrl() - prepare HASH block in SecSS for processing
899 * @length: length for request
900 * @final: true if final op
902 * Prepare SSS HASH block for processing bytes in DMA mode. If it is called
903 * after previous updates, fill up IV words. For final, calculate and set
904 * lengths for HASH so SecSS can finalize hash. For partial, set SSS HASH
905 * length as 2^63 so it will be never reached and set to zero prelow and
908 * This function does not start DMA transfer.
910 static void s5p_hash_write_ctrl(struct s5p_aes_dev *dd, size_t length,
913 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req);
914 u32 prelow, prehigh, low, high;
915 u32 configflags, swapflags;
918 configflags = ctx->engine | SSS_HASH_INIT_BIT;
920 if (likely(ctx->digcnt)) {
921 s5p_hash_write_ctx_iv(dd, ctx);
922 configflags |= SSS_HASH_USER_IV_EN;
926 /* number of bytes for last part */
929 /* total number of bits prev hashed */
930 tmplen = ctx->digcnt * 8;
931 prelow = (u32)tmplen;
932 prehigh = (u32)(tmplen >> 32);
940 swapflags = SSS_HASH_BYTESWAP_DI | SSS_HASH_BYTESWAP_DO |
941 SSS_HASH_BYTESWAP_IV | SSS_HASH_BYTESWAP_KEY;
943 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_LOW, low);
944 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_HIGH, high);
945 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_LOW, prelow);
946 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_HIGH, prehigh);
948 s5p_hash_write(dd, SSS_REG_HASH_CTRL_SWAP, swapflags);
949 s5p_hash_write(dd, SSS_REG_HASH_CTRL, configflags);
953 * s5p_hash_xmit_dma() - start DMA hash processing
955 * @length: length for request
956 * @final: true if final op
958 * Update digcnt here, as it is needed for finup/final op.
960 static int s5p_hash_xmit_dma(struct s5p_aes_dev *dd, size_t length,
963 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req);
966 cnt = dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
968 dev_err(dd->dev, "dma_map_sg error\n");
973 set_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags);
974 dd->hash_sg_iter = ctx->sg;
975 dd->hash_sg_cnt = cnt;
976 s5p_hash_write_ctrl(dd, length, final);
977 ctx->digcnt += length;
978 ctx->total -= length;
980 /* catch last interrupt */
982 set_bit(HASH_FLAGS_FINAL, &dd->hash_flags);
984 s5p_set_dma_hashdata(dd, dd->hash_sg_iter); /* DMA starts */
990 * s5p_hash_copy_sgs() - copy request's bytes into new buffer
991 * @ctx: request context
992 * @sg: source scatterlist request
993 * @new_len: number of bytes to process from sg
995 * Allocate new buffer, copy data for HASH into it. If there was xmit_buf
996 * filled, copy it first, then copy data from sg into it. Prepare one sgl[0]
997 * with allocated buffer.
999 * Set bit in dd->hash_flag so we can free it after irq ends processing.
1001 static int s5p_hash_copy_sgs(struct s5p_hash_reqctx *ctx,
1002 struct scatterlist *sg, unsigned int new_len)
1004 unsigned int pages, len;
1007 len = new_len + ctx->bufcnt;
1008 pages = get_order(len);
1010 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
1012 dev_err(ctx->dd->dev, "alloc pages for unaligned case.\n");
1018 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
1020 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->skip,
1022 sg_init_table(ctx->sgl, 1);
1023 sg_set_buf(ctx->sgl, buf, len);
1028 set_bit(HASH_FLAGS_SGS_COPIED, &ctx->dd->hash_flags);
1034 * s5p_hash_copy_sg_lists() - copy sg list and make fixes in copy
1035 * @ctx: request context
1036 * @sg: source scatterlist request
1037 * @new_len: number of bytes to process from sg
1039 * Allocate new scatterlist table, copy data for HASH into it. If there was
1040 * xmit_buf filled, prepare it first, then copy page, length and offset from
1041 * source sg into it, adjusting begin and/or end for skip offset and
1044 * Resulting sg table will be assigned to ctx->sg. Set flag so we can free
1045 * it after irq ends processing.
1047 static int s5p_hash_copy_sg_lists(struct s5p_hash_reqctx *ctx,
1048 struct scatterlist *sg, unsigned int new_len)
1050 unsigned int skip = ctx->skip, n = sg_nents(sg);
1051 struct scatterlist *tmp;
1057 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
1063 sg_init_table(ctx->sg, n);
1070 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
1075 while (sg && skip >= sg->length) {
1080 while (sg && new_len) {
1081 len = sg->length - skip;
1086 sg_set_page(tmp, sg_page(sg), len, sg->offset + skip);
1096 set_bit(HASH_FLAGS_SGS_ALLOCED, &ctx->dd->hash_flags);
1102 * s5p_hash_prepare_sgs() - prepare sg for processing
1103 * @ctx: request context
1104 * @sg: source scatterlist request
1105 * @nbytes: number of bytes to process from sg
1106 * @final: final flag
1108 * Check two conditions: (1) if buffers in sg have len aligned data, and (2)
1109 * sg table have good aligned elements (list_ok). If one of this checks fails,
1110 * then either (1) allocates new buffer for data with s5p_hash_copy_sgs, copy
1111 * data into this buffer and prepare request in sgl, or (2) allocates new sg
1112 * table and prepare sg elements.
1114 * For digest or finup all conditions can be good, and we may not need any
1117 static int s5p_hash_prepare_sgs(struct s5p_hash_reqctx *ctx,
1118 struct scatterlist *sg,
1119 unsigned int new_len, bool final)
1121 unsigned int skip = ctx->skip, nbytes = new_len, n = 0;
1122 bool aligned = true, list_ok = true;
1123 struct scatterlist *sg_tmp = sg;
1125 if (!sg || !sg->length || !new_len)
1131 while (nbytes > 0 && sg_tmp) {
1133 if (skip >= sg_tmp->length) {
1134 skip -= sg_tmp->length;
1135 if (!sg_tmp->length) {
1140 if (!IS_ALIGNED(sg_tmp->length - skip, BUFLEN)) {
1145 if (nbytes < sg_tmp->length - skip) {
1150 nbytes -= sg_tmp->length - skip;
1154 sg_tmp = sg_next(sg_tmp);
1158 return s5p_hash_copy_sgs(ctx, sg, new_len);
1160 return s5p_hash_copy_sg_lists(ctx, sg, new_len);
1163 * Have aligned data from previous operation and/or current
1164 * Note: will enter here only if (digest or finup) and aligned
1168 sg_init_table(ctx->sgl, 2);
1169 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, ctx->bufcnt);
1170 sg_chain(ctx->sgl, 2, sg);
1182 * s5p_hash_prepare_request() - prepare request for processing
1183 * @req: AHASH request
1184 * @update: true if UPDATE op
1186 * Note 1: we can have update flag _and_ final flag at the same time.
1187 * Note 2: we enter here when digcnt > BUFLEN (=HASH_BLOCK_SIZE) or
1188 * either req->nbytes or ctx->bufcnt + req->nbytes is > BUFLEN or
1191 static int s5p_hash_prepare_request(struct ahash_request *req, bool update)
1193 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1194 bool final = ctx->finup;
1195 int xmit_len, hash_later, nbytes;
1199 nbytes = req->nbytes;
1203 ctx->total = nbytes + ctx->bufcnt;
1207 if (nbytes && (!IS_ALIGNED(ctx->bufcnt, BUFLEN))) {
1208 /* bytes left from previous request, so fill up to BUFLEN */
1209 int len = BUFLEN - ctx->bufcnt % BUFLEN;
1214 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1224 memcpy(ctx->dd->xmit_buf, ctx->buffer, ctx->bufcnt);
1226 xmit_len = ctx->total;
1230 if (IS_ALIGNED(xmit_len, BUFLEN))
1233 xmit_len -= xmit_len & (BUFLEN - 1);
1235 hash_later = ctx->total - xmit_len;
1236 /* copy hash_later bytes from end of req->src */
1237 /* previous bytes are in xmit_buf, so no overwrite */
1238 scatterwalk_map_and_copy(ctx->buffer, req->src,
1239 req->nbytes - hash_later,
1243 if (xmit_len > BUFLEN) {
1244 ret = s5p_hash_prepare_sgs(ctx, req->src, nbytes - hash_later,
1249 /* have buffered data only */
1250 if (unlikely(!ctx->bufcnt)) {
1251 /* first update didn't fill up buffer */
1252 scatterwalk_map_and_copy(ctx->dd->xmit_buf, req->src,
1256 sg_init_table(ctx->sgl, 1);
1257 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, xmit_len);
1263 ctx->bufcnt = hash_later;
1265 ctx->total = xmit_len;
1271 * s5p_hash_update_dma_stop() - unmap DMA
1274 * Unmap scatterlist ctx->sg.
1276 static void s5p_hash_update_dma_stop(struct s5p_aes_dev *dd)
1278 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req);
1280 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
1281 clear_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags);
1285 * s5p_hash_finish() - copy calculated digest to crypto layer
1286 * @req: AHASH request
1288 static void s5p_hash_finish(struct ahash_request *req)
1290 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1291 struct s5p_aes_dev *dd = ctx->dd;
1294 s5p_hash_copy_result(req);
1296 dev_dbg(dd->dev, "hash_finish digcnt: %lld\n", ctx->digcnt);
1300 * s5p_hash_finish_req() - finish request
1301 * @req: AHASH request
1304 static void s5p_hash_finish_req(struct ahash_request *req, int err)
1306 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1307 struct s5p_aes_dev *dd = ctx->dd;
1308 unsigned long flags;
1310 if (test_bit(HASH_FLAGS_SGS_COPIED, &dd->hash_flags))
1311 free_pages((unsigned long)sg_virt(ctx->sg),
1312 get_order(ctx->sg->length));
1314 if (test_bit(HASH_FLAGS_SGS_ALLOCED, &dd->hash_flags))
1318 dd->hash_flags &= ~(BIT(HASH_FLAGS_SGS_ALLOCED) |
1319 BIT(HASH_FLAGS_SGS_COPIED));
1321 if (!err && !ctx->error) {
1322 s5p_hash_read_msg(req);
1323 if (test_bit(HASH_FLAGS_FINAL, &dd->hash_flags))
1324 s5p_hash_finish(req);
1329 spin_lock_irqsave(&dd->hash_lock, flags);
1330 dd->hash_flags &= ~(BIT(HASH_FLAGS_BUSY) | BIT(HASH_FLAGS_FINAL) |
1331 BIT(HASH_FLAGS_DMA_READY) |
1332 BIT(HASH_FLAGS_OUTPUT_READY));
1333 spin_unlock_irqrestore(&dd->hash_lock, flags);
1335 if (req->base.complete)
1336 req->base.complete(&req->base, err);
1340 * s5p_hash_handle_queue() - handle hash queue
1341 * @dd: device s5p_aes_dev
1342 * @req: AHASH request
1344 * If req!=NULL enqueue it on dd->queue, if FLAGS_BUSY is not set on the
1345 * device then processes the first request from the dd->queue
1347 * Returns: see s5p_hash_final below.
1349 static int s5p_hash_handle_queue(struct s5p_aes_dev *dd,
1350 struct ahash_request *req)
1352 struct crypto_async_request *async_req, *backlog;
1353 struct s5p_hash_reqctx *ctx;
1354 unsigned long flags;
1355 int err = 0, ret = 0;
1358 spin_lock_irqsave(&dd->hash_lock, flags);
1360 ret = ahash_enqueue_request(&dd->hash_queue, req);
1362 if (test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) {
1363 spin_unlock_irqrestore(&dd->hash_lock, flags);
1367 backlog = crypto_get_backlog(&dd->hash_queue);
1368 async_req = crypto_dequeue_request(&dd->hash_queue);
1370 set_bit(HASH_FLAGS_BUSY, &dd->hash_flags);
1372 spin_unlock_irqrestore(&dd->hash_lock, flags);
1378 backlog->complete(backlog, -EINPROGRESS);
1380 req = ahash_request_cast(async_req);
1382 ctx = ahash_request_ctx(req);
1384 err = s5p_hash_prepare_request(req, ctx->op_update);
1385 if (err || !ctx->total)
1388 dev_dbg(dd->dev, "handling new req, op_update: %u, nbytes: %d\n",
1389 ctx->op_update, req->nbytes);
1391 s5p_ahash_dma_init(dd, SSS_HASHIN_INDEPENDENT);
1393 s5p_hash_write_iv(req); /* restore hash IV */
1395 if (ctx->op_update) { /* HASH_OP_UPDATE */
1396 err = s5p_hash_xmit_dma(dd, ctx->total, ctx->finup);
1397 if (err != -EINPROGRESS && ctx->finup && !ctx->error)
1398 /* no final() after finup() */
1399 err = s5p_hash_xmit_dma(dd, ctx->total, true);
1400 } else { /* HASH_OP_FINAL */
1401 err = s5p_hash_xmit_dma(dd, ctx->total, true);
1404 if (err != -EINPROGRESS) {
1405 /* hash_tasklet_cb will not finish it, so do it here */
1406 s5p_hash_finish_req(req, err);
1410 * Execute next request immediately if there is anything
1420 * s5p_hash_tasklet_cb() - hash tasklet
1421 * @data: ptr to s5p_aes_dev
1423 static void s5p_hash_tasklet_cb(unsigned long data)
1425 struct s5p_aes_dev *dd = (struct s5p_aes_dev *)data;
1427 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) {
1428 s5p_hash_handle_queue(dd, NULL);
1432 if (test_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags)) {
1433 if (test_and_clear_bit(HASH_FLAGS_DMA_ACTIVE,
1435 s5p_hash_update_dma_stop(dd);
1438 if (test_and_clear_bit(HASH_FLAGS_OUTPUT_READY,
1440 /* hash or semi-hash ready */
1441 clear_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags);
1449 /* finish curent request */
1450 s5p_hash_finish_req(dd->hash_req, 0);
1452 /* If we are not busy, process next req */
1453 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags))
1454 s5p_hash_handle_queue(dd, NULL);
1458 * s5p_hash_enqueue() - enqueue request
1459 * @req: AHASH request
1460 * @op: operation UPDATE (true) or FINAL (false)
1462 * Returns: see s5p_hash_final below.
1464 static int s5p_hash_enqueue(struct ahash_request *req, bool op)
1466 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1467 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1469 ctx->op_update = op;
1471 return s5p_hash_handle_queue(tctx->dd, req);
1475 * s5p_hash_update() - process the hash input data
1476 * @req: AHASH request
1478 * If request will fit in buffer, copy it and return immediately
1479 * else enqueue it with OP_UPDATE.
1481 * Returns: see s5p_hash_final below.
1483 static int s5p_hash_update(struct ahash_request *req)
1485 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1490 if (ctx->bufcnt + req->nbytes <= BUFLEN) {
1491 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1493 ctx->bufcnt += req->nbytes;
1497 return s5p_hash_enqueue(req, true); /* HASH_OP_UPDATE */
1501 * s5p_hash_shash_digest() - calculate shash digest
1502 * @tfm: crypto transformation
1505 * @len: length of data
1506 * @out: output buffer
1508 static int s5p_hash_shash_digest(struct crypto_shash *tfm, u32 flags,
1509 const u8 *data, unsigned int len, u8 *out)
1511 SHASH_DESC_ON_STACK(shash, tfm);
1514 shash->flags = flags & ~CRYPTO_TFM_REQ_MAY_SLEEP;
1516 return crypto_shash_digest(shash, data, len, out);
1520 * s5p_hash_final_shash() - calculate shash digest
1521 * @req: AHASH request
1523 static int s5p_hash_final_shash(struct ahash_request *req)
1525 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1526 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1528 return s5p_hash_shash_digest(tctx->fallback, req->base.flags,
1529 ctx->buffer, ctx->bufcnt, req->result);
1533 * s5p_hash_final() - close up hash and calculate digest
1534 * @req: AHASH request
1536 * Note: in final req->src do not have any data, and req->nbytes can be
1539 * If there were no input data processed yet and the buffered hash data is
1540 * less than BUFLEN (64) then calculate the final hash immediately by using
1541 * SW algorithm fallback.
1543 * Otherwise enqueues the current AHASH request with OP_FINAL operation op
1544 * and finalize hash message in HW. Note that if digcnt!=0 then there were
1545 * previous update op, so there are always some buffered bytes in ctx->buffer,
1546 * which means that ctx->bufcnt!=0
1549 * 0 if the request has been processed immediately,
1550 * -EINPROGRESS if the operation has been queued for later execution or is set
1551 * to processing by HW,
1552 * -EBUSY if queue is full and request should be resubmitted later,
1553 * other negative values denotes an error.
1555 static int s5p_hash_final(struct ahash_request *req)
1557 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1561 return -EINVAL; /* uncompleted hash is not needed */
1563 if (!ctx->digcnt && ctx->bufcnt < BUFLEN)
1564 return s5p_hash_final_shash(req);
1566 return s5p_hash_enqueue(req, false); /* HASH_OP_FINAL */
1570 * s5p_hash_finup() - process last req->src and calculate digest
1571 * @req: AHASH request containing the last update data
1573 * Return values: see s5p_hash_final above.
1575 static int s5p_hash_finup(struct ahash_request *req)
1577 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1582 err1 = s5p_hash_update(req);
1583 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1587 * final() has to be always called to cleanup resources even if
1588 * update() failed, except EINPROGRESS or calculate digest for small
1591 err2 = s5p_hash_final(req);
1593 return err1 ?: err2;
1597 * s5p_hash_init() - initialize AHASH request contex
1598 * @req: AHASH request
1600 * Init async hash request context.
1602 static int s5p_hash_init(struct ahash_request *req)
1604 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1605 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1606 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm);
1616 dev_dbg(tctx->dd->dev, "init: digest size: %d\n",
1617 crypto_ahash_digestsize(tfm));
1619 switch (crypto_ahash_digestsize(tfm)) {
1620 case MD5_DIGEST_SIZE:
1621 ctx->engine = SSS_HASH_ENGINE_MD5;
1622 ctx->nregs = HASH_MD5_MAX_REG;
1624 case SHA1_DIGEST_SIZE:
1625 ctx->engine = SSS_HASH_ENGINE_SHA1;
1626 ctx->nregs = HASH_SHA1_MAX_REG;
1628 case SHA256_DIGEST_SIZE:
1629 ctx->engine = SSS_HASH_ENGINE_SHA256;
1630 ctx->nregs = HASH_SHA256_MAX_REG;
1641 * s5p_hash_digest - calculate digest from req->src
1642 * @req: AHASH request
1644 * Return values: see s5p_hash_final above.
1646 static int s5p_hash_digest(struct ahash_request *req)
1648 return s5p_hash_init(req) ?: s5p_hash_finup(req);
1652 * s5p_hash_cra_init_alg - init crypto alg transformation
1653 * @tfm: crypto transformation
1655 static int s5p_hash_cra_init_alg(struct crypto_tfm *tfm)
1657 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm);
1658 const char *alg_name = crypto_tfm_alg_name(tfm);
1661 /* Allocate a fallback and abort if it failed. */
1662 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1663 CRYPTO_ALG_NEED_FALLBACK);
1664 if (IS_ERR(tctx->fallback)) {
1665 pr_err("fallback alloc fails for '%s'\n", alg_name);
1666 return PTR_ERR(tctx->fallback);
1669 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1670 sizeof(struct s5p_hash_reqctx) + BUFLEN);
1676 * s5p_hash_cra_init - init crypto tfm
1677 * @tfm: crypto transformation
1679 static int s5p_hash_cra_init(struct crypto_tfm *tfm)
1681 return s5p_hash_cra_init_alg(tfm);
1685 * s5p_hash_cra_exit - exit crypto tfm
1686 * @tfm: crypto transformation
1688 * free allocated fallback
1690 static void s5p_hash_cra_exit(struct crypto_tfm *tfm)
1692 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm);
1694 crypto_free_shash(tctx->fallback);
1695 tctx->fallback = NULL;
1699 * s5p_hash_export - export hash state
1700 * @req: AHASH request
1701 * @out: buffer for exported state
1703 static int s5p_hash_export(struct ahash_request *req, void *out)
1705 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1707 memcpy(out, ctx, sizeof(*ctx) + ctx->bufcnt);
1713 * s5p_hash_import - import hash state
1714 * @req: AHASH request
1715 * @in: buffer with state to be imported from
1717 static int s5p_hash_import(struct ahash_request *req, const void *in)
1719 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req);
1720 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1721 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm);
1722 const struct s5p_hash_reqctx *ctx_in = in;
1724 memcpy(ctx, in, sizeof(*ctx) + BUFLEN);
1725 if (ctx_in->bufcnt > BUFLEN) {
1736 static struct ahash_alg algs_sha1_md5_sha256[] = {
1738 .init = s5p_hash_init,
1739 .update = s5p_hash_update,
1740 .final = s5p_hash_final,
1741 .finup = s5p_hash_finup,
1742 .digest = s5p_hash_digest,
1743 .export = s5p_hash_export,
1744 .import = s5p_hash_import,
1745 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN,
1746 .halg.digestsize = SHA1_DIGEST_SIZE,
1749 .cra_driver_name = "exynos-sha1",
1750 .cra_priority = 100,
1751 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1753 CRYPTO_ALG_NEED_FALLBACK,
1754 .cra_blocksize = HASH_BLOCK_SIZE,
1755 .cra_ctxsize = sizeof(struct s5p_hash_ctx),
1756 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK,
1757 .cra_module = THIS_MODULE,
1758 .cra_init = s5p_hash_cra_init,
1759 .cra_exit = s5p_hash_cra_exit,
1763 .init = s5p_hash_init,
1764 .update = s5p_hash_update,
1765 .final = s5p_hash_final,
1766 .finup = s5p_hash_finup,
1767 .digest = s5p_hash_digest,
1768 .export = s5p_hash_export,
1769 .import = s5p_hash_import,
1770 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN,
1771 .halg.digestsize = MD5_DIGEST_SIZE,
1774 .cra_driver_name = "exynos-md5",
1775 .cra_priority = 100,
1776 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1778 CRYPTO_ALG_NEED_FALLBACK,
1779 .cra_blocksize = HASH_BLOCK_SIZE,
1780 .cra_ctxsize = sizeof(struct s5p_hash_ctx),
1781 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK,
1782 .cra_module = THIS_MODULE,
1783 .cra_init = s5p_hash_cra_init,
1784 .cra_exit = s5p_hash_cra_exit,
1788 .init = s5p_hash_init,
1789 .update = s5p_hash_update,
1790 .final = s5p_hash_final,
1791 .finup = s5p_hash_finup,
1792 .digest = s5p_hash_digest,
1793 .export = s5p_hash_export,
1794 .import = s5p_hash_import,
1795 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN,
1796 .halg.digestsize = SHA256_DIGEST_SIZE,
1798 .cra_name = "sha256",
1799 .cra_driver_name = "exynos-sha256",
1800 .cra_priority = 100,
1801 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1803 CRYPTO_ALG_NEED_FALLBACK,
1804 .cra_blocksize = HASH_BLOCK_SIZE,
1805 .cra_ctxsize = sizeof(struct s5p_hash_ctx),
1806 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK,
1807 .cra_module = THIS_MODULE,
1808 .cra_init = s5p_hash_cra_init,
1809 .cra_exit = s5p_hash_cra_exit,
1815 static void s5p_set_aes(struct s5p_aes_dev *dev,
1816 const u8 *key, const u8 *iv, const u8 *ctr,
1817 unsigned int keylen)
1819 void __iomem *keystart;
1822 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
1825 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), ctr, 0x10);
1827 if (keylen == AES_KEYSIZE_256)
1828 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
1829 else if (keylen == AES_KEYSIZE_192)
1830 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2);
1832 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4);
1834 memcpy_toio(keystart, key, keylen);
1837 static bool s5p_is_sg_aligned(struct scatterlist *sg)
1840 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
1848 static int s5p_set_indata_start(struct s5p_aes_dev *dev,
1849 struct ablkcipher_request *req)
1851 struct scatterlist *sg;
1854 dev->sg_src_cpy = NULL;
1856 if (!s5p_is_sg_aligned(sg)) {
1858 "At least one unaligned source scatter list, making a copy\n");
1859 err = s5p_make_sg_cpy(dev, sg, &dev->sg_src_cpy);
1863 sg = dev->sg_src_cpy;
1866 err = s5p_set_indata(dev, sg);
1868 s5p_free_sg_cpy(dev, &dev->sg_src_cpy);
1875 static int s5p_set_outdata_start(struct s5p_aes_dev *dev,
1876 struct ablkcipher_request *req)
1878 struct scatterlist *sg;
1881 dev->sg_dst_cpy = NULL;
1883 if (!s5p_is_sg_aligned(sg)) {
1885 "At least one unaligned dest scatter list, making a copy\n");
1886 err = s5p_make_sg_cpy(dev, sg, &dev->sg_dst_cpy);
1890 sg = dev->sg_dst_cpy;
1893 err = s5p_set_outdata(dev, sg);
1895 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy);
1902 static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
1904 struct ablkcipher_request *req = dev->req;
1906 unsigned long flags;
1910 /* This sets bit [13:12] to 00, which selects 128-bit counter */
1911 aes_control = SSS_AES_KEY_CHANGE_MODE;
1912 if (mode & FLAGS_AES_DECRYPT)
1913 aes_control |= SSS_AES_MODE_DECRYPT;
1915 if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC) {
1916 aes_control |= SSS_AES_CHAIN_MODE_CBC;
1919 } else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR) {
1920 aes_control |= SSS_AES_CHAIN_MODE_CTR;
1924 iv = NULL; /* AES_ECB */
1928 if (dev->ctx->keylen == AES_KEYSIZE_192)
1929 aes_control |= SSS_AES_KEY_SIZE_192;
1930 else if (dev->ctx->keylen == AES_KEYSIZE_256)
1931 aes_control |= SSS_AES_KEY_SIZE_256;
1933 aes_control |= SSS_AES_FIFO_MODE;
1935 /* as a variant it is possible to use byte swapping on DMA side */
1936 aes_control |= SSS_AES_BYTESWAP_DI
1937 | SSS_AES_BYTESWAP_DO
1938 | SSS_AES_BYTESWAP_IV
1939 | SSS_AES_BYTESWAP_KEY
1940 | SSS_AES_BYTESWAP_CNT;
1942 spin_lock_irqsave(&dev->lock, flags);
1944 SSS_WRITE(dev, FCINTENCLR,
1945 SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR);
1946 SSS_WRITE(dev, FCFIFOCTRL, 0x00);
1948 err = s5p_set_indata_start(dev, req);
1952 err = s5p_set_outdata_start(dev, req);
1956 SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
1957 s5p_set_aes(dev, dev->ctx->aes_key, iv, ctr, dev->ctx->keylen);
1959 s5p_set_dma_indata(dev, dev->sg_src);
1960 s5p_set_dma_outdata(dev, dev->sg_dst);
1962 SSS_WRITE(dev, FCINTENSET,
1963 SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET);
1965 spin_unlock_irqrestore(&dev->lock, flags);
1970 s5p_unset_indata(dev);
1975 spin_unlock_irqrestore(&dev->lock, flags);
1976 s5p_aes_complete(req, err);
1979 static void s5p_tasklet_cb(unsigned long data)
1981 struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data;
1982 struct crypto_async_request *async_req, *backlog;
1983 struct s5p_aes_reqctx *reqctx;
1984 unsigned long flags;
1986 spin_lock_irqsave(&dev->lock, flags);
1987 backlog = crypto_get_backlog(&dev->queue);
1988 async_req = crypto_dequeue_request(&dev->queue);
1992 spin_unlock_irqrestore(&dev->lock, flags);
1995 spin_unlock_irqrestore(&dev->lock, flags);
1998 backlog->complete(backlog, -EINPROGRESS);
2000 dev->req = ablkcipher_request_cast(async_req);
2001 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm);
2002 reqctx = ablkcipher_request_ctx(dev->req);
2004 s5p_aes_crypt_start(dev, reqctx->mode);
2007 static int s5p_aes_handle_req(struct s5p_aes_dev *dev,
2008 struct ablkcipher_request *req)
2010 unsigned long flags;
2013 spin_lock_irqsave(&dev->lock, flags);
2014 err = ablkcipher_enqueue_request(&dev->queue, req);
2016 spin_unlock_irqrestore(&dev->lock, flags);
2021 spin_unlock_irqrestore(&dev->lock, flags);
2023 tasklet_schedule(&dev->tasklet);
2028 static int s5p_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
2030 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
2031 struct s5p_aes_reqctx *reqctx = ablkcipher_request_ctx(req);
2032 struct s5p_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
2033 struct s5p_aes_dev *dev = ctx->dev;
2035 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE) &&
2036 ((mode & FLAGS_AES_MODE_MASK) != FLAGS_AES_CTR)) {
2037 dev_err(dev->dev, "request size is not exact amount of AES blocks\n");
2041 reqctx->mode = mode;
2043 return s5p_aes_handle_req(dev, req);
2046 static int s5p_aes_setkey(struct crypto_ablkcipher *cipher,
2047 const u8 *key, unsigned int keylen)
2049 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
2050 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
2052 if (keylen != AES_KEYSIZE_128 &&
2053 keylen != AES_KEYSIZE_192 &&
2054 keylen != AES_KEYSIZE_256)
2057 memcpy(ctx->aes_key, key, keylen);
2058 ctx->keylen = keylen;
2063 static int s5p_aes_ecb_encrypt(struct ablkcipher_request *req)
2065 return s5p_aes_crypt(req, 0);
2068 static int s5p_aes_ecb_decrypt(struct ablkcipher_request *req)
2070 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT);
2073 static int s5p_aes_cbc_encrypt(struct ablkcipher_request *req)
2075 return s5p_aes_crypt(req, FLAGS_AES_CBC);
2078 static int s5p_aes_cbc_decrypt(struct ablkcipher_request *req)
2080 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC);
2083 static int s5p_aes_ctr_crypt(struct ablkcipher_request *req)
2085 return s5p_aes_crypt(req, FLAGS_AES_CTR);
2088 static int s5p_aes_cra_init(struct crypto_tfm *tfm)
2090 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm);
2093 tfm->crt_ablkcipher.reqsize = sizeof(struct s5p_aes_reqctx);
2098 static struct crypto_alg algs[] = {
2100 .cra_name = "ecb(aes)",
2101 .cra_driver_name = "ecb-aes-s5p",
2102 .cra_priority = 100,
2103 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2105 CRYPTO_ALG_KERN_DRIVER_ONLY,
2106 .cra_blocksize = AES_BLOCK_SIZE,
2107 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
2108 .cra_alignmask = 0x0f,
2109 .cra_type = &crypto_ablkcipher_type,
2110 .cra_module = THIS_MODULE,
2111 .cra_init = s5p_aes_cra_init,
2112 .cra_u.ablkcipher = {
2113 .min_keysize = AES_MIN_KEY_SIZE,
2114 .max_keysize = AES_MAX_KEY_SIZE,
2115 .setkey = s5p_aes_setkey,
2116 .encrypt = s5p_aes_ecb_encrypt,
2117 .decrypt = s5p_aes_ecb_decrypt,
2121 .cra_name = "cbc(aes)",
2122 .cra_driver_name = "cbc-aes-s5p",
2123 .cra_priority = 100,
2124 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2126 CRYPTO_ALG_KERN_DRIVER_ONLY,
2127 .cra_blocksize = AES_BLOCK_SIZE,
2128 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
2129 .cra_alignmask = 0x0f,
2130 .cra_type = &crypto_ablkcipher_type,
2131 .cra_module = THIS_MODULE,
2132 .cra_init = s5p_aes_cra_init,
2133 .cra_u.ablkcipher = {
2134 .min_keysize = AES_MIN_KEY_SIZE,
2135 .max_keysize = AES_MAX_KEY_SIZE,
2136 .ivsize = AES_BLOCK_SIZE,
2137 .setkey = s5p_aes_setkey,
2138 .encrypt = s5p_aes_cbc_encrypt,
2139 .decrypt = s5p_aes_cbc_decrypt,
2143 .cra_name = "ctr(aes)",
2144 .cra_driver_name = "ctr-aes-s5p",
2145 .cra_priority = 100,
2146 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2148 CRYPTO_ALG_KERN_DRIVER_ONLY,
2149 .cra_blocksize = AES_BLOCK_SIZE,
2150 .cra_ctxsize = sizeof(struct s5p_aes_ctx),
2151 .cra_alignmask = 0x0f,
2152 .cra_type = &crypto_ablkcipher_type,
2153 .cra_module = THIS_MODULE,
2154 .cra_init = s5p_aes_cra_init,
2155 .cra_u.ablkcipher = {
2156 .min_keysize = AES_MIN_KEY_SIZE,
2157 .max_keysize = AES_MAX_KEY_SIZE,
2158 .ivsize = AES_BLOCK_SIZE,
2159 .setkey = s5p_aes_setkey,
2160 .encrypt = s5p_aes_ctr_crypt,
2161 .decrypt = s5p_aes_ctr_crypt,
2166 static int s5p_aes_probe(struct platform_device *pdev)
2168 struct device *dev = &pdev->dev;
2169 int i, j, err = -ENODEV;
2170 const struct samsung_aes_variant *variant;
2171 struct s5p_aes_dev *pdata;
2172 struct resource *res;
2173 unsigned int hash_i;
2178 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2182 variant = find_s5p_sss_version(pdev);
2183 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2186 * Note: HASH and PRNG uses the same registers in secss, avoid
2187 * overwrite each other. This will drop HASH when CONFIG_EXYNOS_RNG
2188 * is enabled in config. We need larger size for HASH registers in
2189 * secss, current describe only AES/DES
2191 if (IS_ENABLED(CONFIG_CRYPTO_DEV_EXYNOS_HASH)) {
2192 if (variant == &exynos_aes_data) {
2194 pdata->use_hash = true;
2199 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
2200 if (IS_ERR(pdata->ioaddr)) {
2201 if (!pdata->use_hash)
2202 return PTR_ERR(pdata->ioaddr);
2203 /* try AES without HASH */
2205 pdata->use_hash = false;
2206 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
2207 if (IS_ERR(pdata->ioaddr))
2208 return PTR_ERR(pdata->ioaddr);
2211 pdata->clk = devm_clk_get(dev, "secss");
2212 if (IS_ERR(pdata->clk)) {
2213 dev_err(dev, "failed to find secss clock source\n");
2217 err = clk_prepare_enable(pdata->clk);
2219 dev_err(dev, "Enabling SSS clk failed, err %d\n", err);
2223 spin_lock_init(&pdata->lock);
2224 spin_lock_init(&pdata->hash_lock);
2226 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset;
2227 pdata->io_hash_base = pdata->ioaddr + variant->hash_offset;
2229 pdata->irq_fc = platform_get_irq(pdev, 0);
2230 if (pdata->irq_fc < 0) {
2231 err = pdata->irq_fc;
2232 dev_warn(dev, "feed control interrupt is not available.\n");
2235 err = devm_request_threaded_irq(dev, pdata->irq_fc, NULL,
2236 s5p_aes_interrupt, IRQF_ONESHOT,
2239 dev_warn(dev, "feed control interrupt is not available.\n");
2243 pdata->busy = false;
2245 platform_set_drvdata(pdev, pdata);
2248 tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata);
2249 crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN);
2251 for (i = 0; i < ARRAY_SIZE(algs); i++) {
2252 err = crypto_register_alg(&algs[i]);
2257 if (pdata->use_hash) {
2258 tasklet_init(&pdata->hash_tasklet, s5p_hash_tasklet_cb,
2259 (unsigned long)pdata);
2260 crypto_init_queue(&pdata->hash_queue, SSS_HASH_QUEUE_LENGTH);
2262 for (hash_i = 0; hash_i < ARRAY_SIZE(algs_sha1_md5_sha256);
2264 struct ahash_alg *alg;
2266 alg = &algs_sha1_md5_sha256[hash_i];
2267 err = crypto_register_ahash(alg);
2269 dev_err(dev, "can't register '%s': %d\n",
2270 alg->halg.base.cra_driver_name, err);
2276 dev_info(dev, "s5p-sss driver registered\n");
2281 for (j = hash_i - 1; j >= 0; j--)
2282 crypto_unregister_ahash(&algs_sha1_md5_sha256[j]);
2284 tasklet_kill(&pdata->hash_tasklet);
2288 if (i < ARRAY_SIZE(algs))
2289 dev_err(dev, "can't register '%s': %d\n", algs[i].cra_name,
2292 for (j = 0; j < i; j++)
2293 crypto_unregister_alg(&algs[j]);
2295 tasklet_kill(&pdata->tasklet);
2298 clk_disable_unprepare(pdata->clk);
2305 static int s5p_aes_remove(struct platform_device *pdev)
2307 struct s5p_aes_dev *pdata = platform_get_drvdata(pdev);
2313 for (i = 0; i < ARRAY_SIZE(algs); i++)
2314 crypto_unregister_alg(&algs[i]);
2316 tasklet_kill(&pdata->tasklet);
2317 if (pdata->use_hash) {
2318 for (i = ARRAY_SIZE(algs_sha1_md5_sha256) - 1; i >= 0; i--)
2319 crypto_unregister_ahash(&algs_sha1_md5_sha256[i]);
2321 pdata->res->end -= 0x300;
2322 tasklet_kill(&pdata->hash_tasklet);
2323 pdata->use_hash = false;
2326 clk_disable_unprepare(pdata->clk);
2332 static struct platform_driver s5p_aes_crypto = {
2333 .probe = s5p_aes_probe,
2334 .remove = s5p_aes_remove,
2336 .name = "s5p-secss",
2337 .of_match_table = s5p_sss_dt_match,
2341 module_platform_driver(s5p_aes_crypto);
2343 MODULE_DESCRIPTION("S5PV210 AES hw acceleration support.");
2344 MODULE_LICENSE("GPL v2");
2345 MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>");
2346 MODULE_AUTHOR("Kamil Konieczny <k.konieczny@partner.samsung.com>");