1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
6 enum icp_qat_hw_ae_id {
17 ICP_QAT_HW_AE_10 = 10,
18 ICP_QAT_HW_AE_11 = 11,
19 ICP_QAT_HW_AE_DELIMITER = 12
22 enum icp_qat_hw_qat_id {
29 ICP_QAT_HW_QAT_DELIMITER = 6
32 enum icp_qat_hw_auth_algo {
33 ICP_QAT_HW_AUTH_ALGO_NULL = 0,
34 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1,
35 ICP_QAT_HW_AUTH_ALGO_MD5 = 2,
36 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3,
37 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4,
38 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5,
39 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6,
40 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,
41 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
42 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,
43 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
44 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,
45 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
46 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
47 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
48 ICP_QAT_HW_AUTH_RESERVED_1 = 15,
49 ICP_QAT_HW_AUTH_RESERVED_2 = 16,
50 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
51 ICP_QAT_HW_AUTH_RESERVED_3 = 18,
52 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
53 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20
56 enum icp_qat_hw_auth_mode {
57 ICP_QAT_HW_AUTH_MODE0 = 0,
58 ICP_QAT_HW_AUTH_MODE1 = 1,
59 ICP_QAT_HW_AUTH_MODE2 = 2,
60 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3
63 struct icp_qat_hw_auth_config {
68 enum icp_qat_slice_mask {
69 ICP_ACCEL_MASK_CIPHER_SLICE = BIT(0),
70 ICP_ACCEL_MASK_AUTH_SLICE = BIT(1),
71 ICP_ACCEL_MASK_PKE_SLICE = BIT(2),
72 ICP_ACCEL_MASK_COMPRESS_SLICE = BIT(3),
73 ICP_ACCEL_MASK_LZS_SLICE = BIT(4),
74 ICP_ACCEL_MASK_EIA3_SLICE = BIT(5),
75 ICP_ACCEL_MASK_SHA3_SLICE = BIT(6),
78 enum icp_qat_capabilities_mask {
79 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
80 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1),
81 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2),
82 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3),
83 ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4),
84 ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5),
85 ICP_ACCEL_CAPABILITIES_LZS_COMPRESSION = BIT(6),
86 ICP_ACCEL_CAPABILITIES_RAND = BIT(7),
87 ICP_ACCEL_CAPABILITIES_ZUC = BIT(8),
88 ICP_ACCEL_CAPABILITIES_SHA3 = BIT(9),
91 #define QAT_AUTH_MODE_BITPOS 4
92 #define QAT_AUTH_MODE_MASK 0xF
93 #define QAT_AUTH_ALGO_BITPOS 0
94 #define QAT_AUTH_ALGO_MASK 0xF
95 #define QAT_AUTH_CMP_BITPOS 8
96 #define QAT_AUTH_CMP_MASK 0x7F
97 #define QAT_AUTH_SHA3_PADDING_BITPOS 16
98 #define QAT_AUTH_SHA3_PADDING_MASK 0x1
99 #define QAT_AUTH_ALGO_SHA3_BITPOS 22
100 #define QAT_AUTH_ALGO_SHA3_MASK 0x3
101 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
102 (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
103 ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
104 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
105 QAT_AUTH_ALGO_SHA3_BITPOS) | \
106 (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
107 (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
108 & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
109 ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
111 struct icp_qat_hw_auth_counter {
116 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
117 #define QAT_AUTH_COUNT_BITPOS 0
118 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \
119 (((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)
121 struct icp_qat_hw_auth_setup {
122 struct icp_qat_hw_auth_config auth_config;
123 struct icp_qat_hw_auth_counter auth_counter;
126 #define QAT_HW_DEFAULT_ALIGNMENT 8
127 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1)))
128 #define ICP_QAT_HW_NULL_STATE1_SZ 32
129 #define ICP_QAT_HW_MD5_STATE1_SZ 16
130 #define ICP_QAT_HW_SHA1_STATE1_SZ 20
131 #define ICP_QAT_HW_SHA224_STATE1_SZ 32
132 #define ICP_QAT_HW_SHA256_STATE1_SZ 32
133 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
134 #define ICP_QAT_HW_SHA384_STATE1_SZ 64
135 #define ICP_QAT_HW_SHA512_STATE1_SZ 64
136 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
137 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
138 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
139 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
140 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
141 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32
142 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
143 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
144 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
145 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
146 #define ICP_QAT_HW_NULL_STATE2_SZ 32
147 #define ICP_QAT_HW_MD5_STATE2_SZ 16
148 #define ICP_QAT_HW_SHA1_STATE2_SZ 20
149 #define ICP_QAT_HW_SHA224_STATE2_SZ 32
150 #define ICP_QAT_HW_SHA256_STATE2_SZ 32
151 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
152 #define ICP_QAT_HW_SHA384_STATE2_SZ 64
153 #define ICP_QAT_HW_SHA512_STATE2_SZ 64
154 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
155 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
156 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
157 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
158 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
159 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
160 #define ICP_QAT_HW_F9_IK_SZ 16
161 #define ICP_QAT_HW_F9_FK_SZ 16
162 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \
164 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ
165 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24
166 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32
167 #define ICP_QAT_HW_GALOIS_H_SZ 16
168 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
169 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
171 struct icp_qat_hw_auth_sha512 {
172 struct icp_qat_hw_auth_setup inner_setup;
173 __u8 state1[ICP_QAT_HW_SHA512_STATE1_SZ];
174 struct icp_qat_hw_auth_setup outer_setup;
175 __u8 state2[ICP_QAT_HW_SHA512_STATE2_SZ];
178 struct icp_qat_hw_auth_algo_blk {
179 struct icp_qat_hw_auth_sha512 sha;
182 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0
183 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF
185 enum icp_qat_hw_cipher_algo {
186 ICP_QAT_HW_CIPHER_ALGO_NULL = 0,
187 ICP_QAT_HW_CIPHER_ALGO_DES = 1,
188 ICP_QAT_HW_CIPHER_ALGO_3DES = 2,
189 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3,
190 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4,
191 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5,
192 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,
193 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,
194 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,
195 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,
196 ICP_QAT_HW_CIPHER_DELIMITER = 10
199 enum icp_qat_hw_cipher_mode {
200 ICP_QAT_HW_CIPHER_ECB_MODE = 0,
201 ICP_QAT_HW_CIPHER_CBC_MODE = 1,
202 ICP_QAT_HW_CIPHER_CTR_MODE = 2,
203 ICP_QAT_HW_CIPHER_F8_MODE = 3,
204 ICP_QAT_HW_CIPHER_XTS_MODE = 6,
205 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
208 struct icp_qat_hw_cipher_config {
213 enum icp_qat_hw_cipher_dir {
214 ICP_QAT_HW_CIPHER_ENCRYPT = 0,
215 ICP_QAT_HW_CIPHER_DECRYPT = 1,
218 enum icp_qat_hw_cipher_convert {
219 ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
220 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
223 #define QAT_CIPHER_MODE_BITPOS 4
224 #define QAT_CIPHER_MODE_MASK 0xF
225 #define QAT_CIPHER_ALGO_BITPOS 0
226 #define QAT_CIPHER_ALGO_MASK 0xF
227 #define QAT_CIPHER_CONVERT_BITPOS 9
228 #define QAT_CIPHER_CONVERT_MASK 0x1
229 #define QAT_CIPHER_DIR_BITPOS 8
230 #define QAT_CIPHER_DIR_MASK 0x1
231 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
232 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
233 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
234 (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \
235 ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
236 ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
237 ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
238 #define ICP_QAT_HW_DES_BLK_SZ 8
239 #define ICP_QAT_HW_3DES_BLK_SZ 8
240 #define ICP_QAT_HW_NULL_BLK_SZ 8
241 #define ICP_QAT_HW_AES_BLK_SZ 16
242 #define ICP_QAT_HW_KASUMI_BLK_SZ 8
243 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8
244 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8
245 #define ICP_QAT_HW_NULL_KEY_SZ 256
246 #define ICP_QAT_HW_DES_KEY_SZ 8
247 #define ICP_QAT_HW_3DES_KEY_SZ 24
248 #define ICP_QAT_HW_AES_128_KEY_SZ 16
249 #define ICP_QAT_HW_AES_192_KEY_SZ 24
250 #define ICP_QAT_HW_AES_256_KEY_SZ 32
251 #define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
252 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
253 #define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \
254 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
255 #define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
256 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
257 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
258 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
259 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
260 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
261 #define ICP_QAT_HW_KASUMI_KEY_SZ 16
262 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \
263 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
264 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
265 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
266 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
267 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
268 #define ICP_QAT_HW_ARC4_KEY_SZ 256
269 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
270 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
271 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
272 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16
273 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2
274 #define INIT_SHRAM_CONSTANTS_TABLE_SZ 1024
276 struct icp_qat_hw_cipher_aes256_f8 {
277 struct icp_qat_hw_cipher_config cipher_config;
278 __u8 key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
281 struct icp_qat_hw_cipher_algo_blk {
282 struct icp_qat_hw_cipher_aes256_f8 aes;