drivers/crypto/qat/qat_common/adf_transport.c

   1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
   2 /* Copyright(c) 2014 - 2020 Intel Corporation */
   3 #include <linux/delay.h>
   4 #include <linux/nospec.h>
   5 #include "adf_accel_devices.h"
   6 #include "adf_transport_internal.h"
   7 #include "adf_transport_access_macros.h"
   8 #include "adf_cfg.h"
   9 #include "adf_common_drv.h"
  10
  11 static inline u32 adf_modulo(u32 data, u32 shift)
  12 {
  13         u32 div = data >> shift;
  14         u32 mult = div << shift;
  15
  16         return data - mult;
  17 }
  18
  19 static inline int adf_check_ring_alignment(u64 addr, u64 size)
  20 {
  21         if (((size - 1) & addr) != 0)
  22                 return -EFAULT;
  23         return 0;
  24 }
  25
  26 static int adf_verify_ring_size(u32 msg_size, u32 msg_num)
  27 {
  28         int i = ADF_MIN_RING_SIZE;
  29
  30         for (; i <= ADF_MAX_RING_SIZE; i++)
  31                 if ((msg_size * msg_num) == ADF_SIZE_TO_RING_SIZE_IN_BYTES(i))
  32                         return i;
  33
  34         return ADF_DEFAULT_RING_SIZE;
  35 }
  36
  37 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring)
  38 {
  39         spin_lock(&bank->lock);
  40         if (bank->ring_mask & (1 << ring)) {
  41                 spin_unlock(&bank->lock);
  42                 return -EFAULT;
  43         }
  44         bank->ring_mask |= (1 << ring);
  45         spin_unlock(&bank->lock);
  46         return 0;
  47 }
  48
  49 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring)
  50 {
  51         spin_lock(&bank->lock);
  52         bank->ring_mask &= ~(1 << ring);
  53         spin_unlock(&bank->lock);
  54 }
  55
  56 static void adf_enable_ring_irq(struct adf_etr_bank_data *bank, u32 ring)
  57 {
  58         struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);
  59
  60         spin_lock_bh(&bank->lock);
  61         bank->irq_mask |= (1 << ring);
  62         spin_unlock_bh(&bank->lock);
  63         csr_ops->write_csr_int_col_en(bank->csr_addr, bank->bank_number,
  64                                       bank->irq_mask);
  65         csr_ops->write_csr_int_col_ctl(bank->csr_addr, bank->bank_number,
  66                                        bank->irq_coalesc_timer);
  67 }
  68
  69 static void adf_disable_ring_irq(struct adf_etr_bank_data *bank, u32 ring)
  70 {
  71         struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);
  72
  73         spin_lock_bh(&bank->lock);
  74         bank->irq_mask &= ~(1 << ring);
  75         spin_unlock_bh(&bank->lock);
  76         csr_ops->write_csr_int_col_en(bank->csr_addr, bank->bank_number,
  77                                       bank->irq_mask);
  78 }
  79
  80 int adf_send_message(struct adf_etr_ring_data *ring, u32 *msg)
  81 {
  82         struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(ring->bank->accel_dev);
  83
  84         if (atomic_add_return(1, ring->inflights) >
  85             ADF_MAX_INFLIGHTS(ring->ring_size, ring->msg_size)) {
  86                 atomic_dec(ring->inflights);
  87                 return -EAGAIN;
  88         }
  89         spin_lock_bh(&ring->lock);
  90         memcpy((void *)((uintptr_t)ring->base_addr + ring->tail), msg,
  91                ADF_MSG_SIZE_TO_BYTES(ring->msg_size));
  92
  93         ring->tail = adf_modulo(ring->tail +
  94                                 ADF_MSG_SIZE_TO_BYTES(ring->msg_size),
  95                                 ADF_RING_SIZE_MODULO(ring->ring_size));
  96         csr_ops->write_csr_ring_tail(ring->bank->csr_addr,
  97                                      ring->bank->bank_number, ring->ring_number,
  98                                      ring->tail);
  99         spin_unlock_bh(&ring->lock);
 100
 101         return 0;
 102 }
 103
 104 static int adf_handle_response(struct adf_etr_ring_data *ring)
 105 {
 106         struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(ring->bank->accel_dev);
 107         u32 msg_counter = 0;
 108         u32 *msg = (u32 *)((uintptr_t)ring->base_addr + ring->head);
 109
 110         while (*msg != ADF_RING_EMPTY_SIG) {
 111                 ring->callback((u32 *)msg);
 112                 atomic_dec(ring->inflights);
 113                 *msg = ADF_RING_EMPTY_SIG;
 114                 ring->head = adf_modulo(ring->head +
 115                                         ADF_MSG_SIZE_TO_BYTES(ring->msg_size),
 116                                         ADF_RING_SIZE_MODULO(ring->ring_size));
 117                 msg_counter++;
 118                 msg = (u32 *)((uintptr_t)ring->base_addr + ring->head);
 119         }
 120         if (msg_counter > 0) {
 121                 csr_ops->write_csr_ring_head(ring->bank->csr_addr,
 122                                              ring->bank->bank_number,
 123                                              ring->ring_number, ring->head);
 124         }
 125         return 0;
 126 }
 127
 128 static void adf_configure_tx_ring(struct adf_etr_ring_data *ring)
 129 {
 130         struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(ring->bank->accel_dev);
 131         u32 ring_config = BUILD_RING_CONFIG(ring->ring_size);
 132
 133         csr_ops->write_csr_ring_config(ring->bank->csr_addr,
 134                                        ring->bank->bank_number,
 135                                        ring->ring_number, ring_config);
 136
 137 }
 138
 139 static void adf_configure_rx_ring(struct adf_etr_ring_data *ring)
 140 {
 141         struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(ring->bank->accel_dev);
 142         u32 ring_config =
 143                         BUILD_RESP_RING_CONFIG(ring->ring_size,
 144                                                ADF_RING_NEAR_WATERMARK_512,
 145                                                ADF_RING_NEAR_WATERMARK_0);
 146
 147         csr_ops->write_csr_ring_config(ring->bank->csr_addr,
 148                                        ring->bank->bank_number,
 149                                        ring->ring_number, ring_config);
 150 }
 151
 152 static int adf_init_ring(struct adf_etr_ring_data *ring)
 153 {
 154         struct adf_etr_bank_data *bank = ring->bank;
 155         struct adf_accel_dev *accel_dev = bank->accel_dev;
 156         struct adf_hw_device_data *hw_data = accel_dev->hw_device;
 157         struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
 158         u64 ring_base;
 159         u32 ring_size_bytes =
 160                         ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size);
 161
 162         ring_size_bytes = ADF_RING_SIZE_BYTES_MIN(ring_size_bytes);
 163         ring->base_addr = dma_alloc_coherent(&GET_DEV(accel_dev),
 164                                              ring_size_bytes, &ring->dma_addr,
 165                                              GFP_KERNEL);
 166         if (!ring->base_addr)
 167                 return -ENOMEM;
 168
 169         memset(ring->base_addr, 0x7F, ring_size_bytes);
 170         /* The base_addr has to be aligned to the size of the buffer */
 171         if (adf_check_ring_alignment(ring->dma_addr, ring_size_bytes)) {
 172                 dev_err(&GET_DEV(accel_dev), "Ring address not aligned\n");
 173                 dma_free_coherent(&GET_DEV(accel_dev), ring_size_bytes,
 174                                   ring->base_addr, ring->dma_addr);
 175                 return -EFAULT;
 176         }
 177
 178         if (hw_data->tx_rings_mask & (1 << ring->ring_number))
 179                 adf_configure_tx_ring(ring);
 180
 181         else
 182                 adf_configure_rx_ring(ring);
 183
 184         ring_base = csr_ops->build_csr_ring_base_addr(ring->dma_addr,
 185                                                       ring->ring_size);
 186
 187         csr_ops->write_csr_ring_base(ring->bank->csr_addr,
 188                                      ring->bank->bank_number, ring->ring_number,
 189                                      ring_base);
 190         spin_lock_init(&ring->lock);
 191         return 0;
 192 }
 193
 194 static void adf_cleanup_ring(struct adf_etr_ring_data *ring)
 195 {
 196         u32 ring_size_bytes =
 197                         ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size);
 198         ring_size_bytes = ADF_RING_SIZE_BYTES_MIN(ring_size_bytes);
 199
 200         if (ring->base_addr) {
 201                 memset(ring->base_addr, 0x7F, ring_size_bytes);
 202                 dma_free_coherent(&GET_DEV(ring->bank->accel_dev),
 203                                   ring_size_bytes, ring->base_addr,
 204                                   ring->dma_addr);
 205         }
 206 }
 207
 208 int adf_create_ring(struct adf_accel_dev *accel_dev, const char *section,
 209                     u32 bank_num, u32 num_msgs,
 210                     u32 msg_size, const char *ring_name,
 211                     adf_callback_fn callback, int poll_mode,
 212                     struct adf_etr_ring_data **ring_ptr)
 213 {
 214         struct adf_etr_data *transport_data = accel_dev->transport;
 215         u8 num_rings_per_bank = GET_NUM_RINGS_PER_BANK(accel_dev);
 216         struct adf_etr_bank_data *bank;
 217         struct adf_etr_ring_data *ring;
 218         char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES];
 219         u32 ring_num;
 220         int ret;
 221
 222         if (bank_num >= GET_MAX_BANKS(accel_dev)) {
 223                 dev_err(&GET_DEV(accel_dev), "Invalid bank number\n");
 224                 return -EFAULT;
 225         }
 226         if (msg_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {
 227                 dev_err(&GET_DEV(accel_dev), "Invalid msg size\n");
 228                 return -EFAULT;
 229         }
 230         if (ADF_MAX_INFLIGHTS(adf_verify_ring_size(msg_size, num_msgs),
 231                               ADF_BYTES_TO_MSG_SIZE(msg_size)) < 2) {
 232                 dev_err(&GET_DEV(accel_dev),
 233                         "Invalid ring size for given msg size\n");
 234                 return -EFAULT;
 235         }
 236         if (adf_cfg_get_param_value(accel_dev, section, ring_name, val)) {
 237                 dev_err(&GET_DEV(accel_dev), "Section %s, no such entry : %s\n",
 238                         section, ring_name);
 239                 return -EFAULT;
 240         }
 241         if (kstrtouint(val, 10, &ring_num)) {
 242                 dev_err(&GET_DEV(accel_dev), "Can't get ring number\n");
 243                 return -EFAULT;
 244         }
 245         if (ring_num >= num_rings_per_bank) {
 246                 dev_err(&GET_DEV(accel_dev), "Invalid ring number\n");
 247                 return -EFAULT;
 248         }
 249
 250         ring_num = array_index_nospec(ring_num, num_rings_per_bank);
 251         bank = &transport_data->banks[bank_num];
 252         if (adf_reserve_ring(bank, ring_num)) {
 253                 dev_err(&GET_DEV(accel_dev), "Ring %d, %s already exists.\n",
 254                         ring_num, ring_name);
 255                 return -EFAULT;
 256         }
 257         ring = &bank->rings[ring_num];
 258         ring->ring_number = ring_num;
 259         ring->bank = bank;
 260         ring->callback = callback;
 261         ring->msg_size = ADF_BYTES_TO_MSG_SIZE(msg_size);
 262         ring->ring_size = adf_verify_ring_size(msg_size, num_msgs);
 263         ring->head = 0;
 264         ring->tail = 0;
 265         atomic_set(ring->inflights, 0);
 266         ret = adf_init_ring(ring);
 267         if (ret)
 268                 goto err;
 269
 270         /* Enable HW arbitration for the given ring */
 271         adf_update_ring_arb(ring);
 272
 273         if (adf_ring_debugfs_add(ring, ring_name)) {
 274                 dev_err(&GET_DEV(accel_dev),
 275                         "Couldn't add ring debugfs entry\n");
 276                 ret = -EFAULT;
 277                 goto err;
 278         }
 279
 280         /* Enable interrupts if needed */
 281         if (callback && (!poll_mode))
 282                 adf_enable_ring_irq(bank, ring->ring_number);
 283         *ring_ptr = ring;
 284         return 0;
 285 err:
 286         adf_cleanup_ring(ring);
 287         adf_unreserve_ring(bank, ring_num);
 288         adf_update_ring_arb(ring);
 289         return ret;
 290 }
 291
 292 void adf_remove_ring(struct adf_etr_ring_data *ring)
 293 {
 294         struct adf_etr_bank_data *bank = ring->bank;
 295         struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);
 296
 297         /* Disable interrupts for the given ring */
 298         adf_disable_ring_irq(bank, ring->ring_number);
 299
 300         /* Clear PCI config space */
 301
 302         csr_ops->write_csr_ring_config(bank->csr_addr, bank->bank_number,
 303                                        ring->ring_number, 0);
 304         csr_ops->write_csr_ring_base(bank->csr_addr, bank->bank_number,
 305                                      ring->ring_number, 0);
 306         adf_ring_debugfs_rm(ring);
 307         adf_unreserve_ring(bank, ring->ring_number);
 308         /* Disable HW arbitration for the given ring */
 309         adf_update_ring_arb(ring);
 310         adf_cleanup_ring(ring);
 311 }
 312
 313 static void adf_ring_response_handler(struct adf_etr_bank_data *bank)
 314 {
 315         struct adf_accel_dev *accel_dev = bank->accel_dev;
 316         u8 num_rings_per_bank = GET_NUM_RINGS_PER_BANK(accel_dev);
 317         struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
 318         unsigned long empty_rings;
 319         int i;
 320
 321         empty_rings = csr_ops->read_csr_e_stat(bank->csr_addr,
 322                                                bank->bank_number);
 323         empty_rings = ~empty_rings & bank->irq_mask;
 324
 325         for_each_set_bit(i, &empty_rings, num_rings_per_bank)
 326                 adf_handle_response(&bank->rings[i]);
 327 }
 328
 329 void adf_response_handler(uintptr_t bank_addr)
 330 {
 331         struct adf_etr_bank_data *bank = (void *)bank_addr;
 332         struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev);
 333
 334         /* Handle all the responses and reenable IRQs */
 335         adf_ring_response_handler(bank);
 336
 337         csr_ops->write_csr_int_flag_and_col(bank->csr_addr, bank->bank_number,
 338                                             bank->irq_mask);
 339 }
 340
 341 static inline int adf_get_cfg_int(struct adf_accel_dev *accel_dev,
 342                                   const char *section, const char *format,
 343                                   u32 key, u32 *value)
 344 {
 345         char key_buf[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
 346         char val_buf[ADF_CFG_MAX_VAL_LEN_IN_BYTES];
 347
 348         snprintf(key_buf, ADF_CFG_MAX_KEY_LEN_IN_BYTES, format, key);
 349
 350         if (adf_cfg_get_param_value(accel_dev, section, key_buf, val_buf))
 351                 return -EFAULT;
 352
 353         if (kstrtouint(val_buf, 10, value))
 354                 return -EFAULT;
 355         return 0;
 356 }
 357
 358 static void adf_get_coalesc_timer(struct adf_etr_bank_data *bank,
 359                                   const char *section,
 360                                   u32 bank_num_in_accel)
 361 {
 362         if (adf_get_cfg_int(bank->accel_dev, section,
 363                             ADF_ETRMGR_COALESCE_TIMER_FORMAT,
 364                             bank_num_in_accel, &bank->irq_coalesc_timer))
 365                 bank->irq_coalesc_timer = ADF_COALESCING_DEF_TIME;
 366
 367         if (ADF_COALESCING_MAX_TIME < bank->irq_coalesc_timer ||
 368             ADF_COALESCING_MIN_TIME > bank->irq_coalesc_timer)
 369                 bank->irq_coalesc_timer = ADF_COALESCING_DEF_TIME;
 370 }
 371
 372 static int adf_init_bank(struct adf_accel_dev *accel_dev,
 373                          struct adf_etr_bank_data *bank,
 374                          u32 bank_num, void __iomem *csr_addr)
 375 {
 376         struct adf_hw_device_data *hw_data = accel_dev->hw_device;
 377         u8 num_rings_per_bank = hw_data->num_rings_per_bank;
 378         struct adf_hw_csr_ops *csr_ops = &hw_data->csr_ops;
 379         u32 irq_mask = BIT(num_rings_per_bank) - 1;
 380         struct adf_etr_ring_data *ring;
 381         struct adf_etr_ring_data *tx_ring;
 382         u32 i, coalesc_enabled = 0;
 383         unsigned long ring_mask;
 384         int size;
 385
 386         memset(bank, 0, sizeof(*bank));
 387         bank->bank_number = bank_num;
 388         bank->csr_addr = csr_addr;
 389         bank->accel_dev = accel_dev;
 390         spin_lock_init(&bank->lock);
 391
 392         /* Allocate the rings in the bank */
 393         size = num_rings_per_bank * sizeof(struct adf_etr_ring_data);
 394         bank->rings = kzalloc_node(size, GFP_KERNEL,
 395                                    dev_to_node(&GET_DEV(accel_dev)));
 396         if (!bank->rings)
 397                 return -ENOMEM;
 398
 399         /* Enable IRQ coalescing always. This will allow to use
 400          * the optimised flag and coalesc register.
 401          * If it is disabled in the config file just use min time value */
 402         if ((adf_get_cfg_int(accel_dev, "Accelerator0",
 403                              ADF_ETRMGR_COALESCING_ENABLED_FORMAT, bank_num,
 404                              &coalesc_enabled) == 0) && coalesc_enabled)
 405                 adf_get_coalesc_timer(bank, "Accelerator0", bank_num);
 406         else
 407                 bank->irq_coalesc_timer = ADF_COALESCING_MIN_TIME;
 408
 409         for (i = 0; i < num_rings_per_bank; i++) {
 410                 csr_ops->write_csr_ring_config(csr_addr, bank_num, i, 0);
 411                 csr_ops->write_csr_ring_base(csr_addr, bank_num, i, 0);
 412
 413                 ring = &bank->rings[i];
 414                 if (hw_data->tx_rings_mask & (1 << i)) {
 415                         ring->inflights =
 416                                 kzalloc_node(sizeof(atomic_t),
 417                                              GFP_KERNEL,
 418                                              dev_to_node(&GET_DEV(accel_dev)));
 419                         if (!ring->inflights)
 420                                 goto err;
 421                 } else {
 422                         if (i < hw_data->tx_rx_gap) {
 423                                 dev_err(&GET_DEV(accel_dev),
 424                                         "Invalid tx rings mask config\n");
 425                                 goto err;
 426                         }
 427                         tx_ring = &bank->rings[i - hw_data->tx_rx_gap];
 428                         ring->inflights = tx_ring->inflights;
 429                 }
 430         }
 431         if (adf_bank_debugfs_add(bank)) {
 432                 dev_err(&GET_DEV(accel_dev),
 433                         "Failed to add bank debugfs entry\n");
 434                 goto err;
 435         }
 436
 437         csr_ops->write_csr_int_flag(csr_addr, bank_num, irq_mask);
 438         csr_ops->write_csr_int_srcsel(csr_addr, bank_num);
 439
 440         return 0;
 441 err:
 442         ring_mask = hw_data->tx_rings_mask;
 443         for_each_set_bit(i, &ring_mask, num_rings_per_bank) {
 444                 ring = &bank->rings[i];
 445                 kfree(ring->inflights);
 446                 ring->inflights = NULL;
 447         }
 448         kfree(bank->rings);
 449         return -ENOMEM;
 450 }
 451
 452 /**
 453  * adf_init_etr_data() - Initialize transport rings for acceleration device
 454  * @accel_dev:  Pointer to acceleration device.
 455  *
 456  * Function is the initializes the communications channels (rings) to the
 457  * acceleration device accel_dev.
 458  * To be used by QAT device specific drivers.
 459  *
 460  * Return: 0 on success, error code otherwise.
 461  */
 462 int adf_init_etr_data(struct adf_accel_dev *accel_dev)
 463 {
 464         struct adf_etr_data *etr_data;
 465         struct adf_hw_device_data *hw_data = accel_dev->hw_device;
 466         void __iomem *csr_addr;
 467         u32 size;
 468         u32 num_banks = 0;
 469         int i, ret;
 470
 471         etr_data = kzalloc_node(sizeof(*etr_data), GFP_KERNEL,
 472                                 dev_to_node(&GET_DEV(accel_dev)));
 473         if (!etr_data)
 474                 return -ENOMEM;
 475
 476         num_banks = GET_MAX_BANKS(accel_dev);
 477         size = num_banks * sizeof(struct adf_etr_bank_data);
 478         etr_data->banks = kzalloc_node(size, GFP_KERNEL,
 479                                        dev_to_node(&GET_DEV(accel_dev)));
 480         if (!etr_data->banks) {
 481                 ret = -ENOMEM;
 482                 goto err_bank;
 483         }
 484
 485         accel_dev->transport = etr_data;
 486         i = hw_data->get_etr_bar_id(hw_data);
 487         csr_addr = accel_dev->accel_pci_dev.pci_bars[i].virt_addr;
 488
 489         /* accel_dev->debugfs_dir should always be non-NULL here */
 490         etr_data->debug = debugfs_create_dir("transport",
 491                                              accel_dev->debugfs_dir);
 492
 493         for (i = 0; i < num_banks; i++) {
 494                 ret = adf_init_bank(accel_dev, &etr_data->banks[i], i,
 495                                     csr_addr);
 496                 if (ret)
 497                         goto err_bank_all;
 498         }
 499
 500         return 0;
 501
 502 err_bank_all:
 503         debugfs_remove(etr_data->debug);
 504         kfree(etr_data->banks);
 505 err_bank:
 506         kfree(etr_data);
 507         accel_dev->transport = NULL;
 508         return ret;
 509 }
 510 EXPORT_SYMBOL_GPL(adf_init_etr_data);
 511
 512 static void cleanup_bank(struct adf_etr_bank_data *bank)
 513 {
 514         struct adf_accel_dev *accel_dev = bank->accel_dev;
 515         struct adf_hw_device_data *hw_data = accel_dev->hw_device;
 516         u8 num_rings_per_bank = hw_data->num_rings_per_bank;
 517         u32 i;
 518
 519         for (i = 0; i < num_rings_per_bank; i++) {
 520                 struct adf_etr_ring_data *ring = &bank->rings[i];
 521
 522                 if (bank->ring_mask & (1 << i))
 523                         adf_cleanup_ring(ring);
 524
 525                 if (hw_data->tx_rings_mask & (1 << i))
 526                         kfree(ring->inflights);
 527         }
 528         kfree(bank->rings);
 529         adf_bank_debugfs_rm(bank);
 530         memset(bank, 0, sizeof(*bank));
 531 }
 532
 533 static void adf_cleanup_etr_handles(struct adf_accel_dev *accel_dev)
 534 {
 535         struct adf_etr_data *etr_data = accel_dev->transport;
 536         u32 i, num_banks = GET_MAX_BANKS(accel_dev);
 537
 538         for (i = 0; i < num_banks; i++)
 539                 cleanup_bank(&etr_data->banks[i]);
 540 }
 541
 542 /**
 543  * adf_cleanup_etr_data() - Clear transport rings for acceleration device
 544  * @accel_dev:  Pointer to acceleration device.
 545  *
 546  * Function is the clears the communications channels (rings) of the
 547  * acceleration device accel_dev.
 548  * To be used by QAT device specific drivers.
 549  *
 550  * Return: void
 551  */
 552 void adf_cleanup_etr_data(struct adf_accel_dev *accel_dev)
 553 {
 554         struct adf_etr_data *etr_data = accel_dev->transport;
 555
 556         if (etr_data) {
 557                 adf_cleanup_etr_handles(accel_dev);
 558                 debugfs_remove(etr_data->debug);
 559                 kfree(etr_data->banks->rings);
 560                 kfree(etr_data->banks);
 561                 kfree(etr_data);
 562                 accel_dev->transport = NULL;
 563         }
 564 }
 565 EXPORT_SYMBOL_GPL(adf_cleanup_etr_data);