drivers/crypto/omap-sham.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Cryptographic API.
   4  *
   5  * Support for OMAP SHA1/MD5 HW acceleration.
   6  *
   7  * Copyright (c) 2010 Nokia Corporation
   8  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   9  * Copyright (c) 2011 Texas Instruments Incorporated
  10  *
  11  * Some ideas are from old omap-sha1-md5.c driver.
  12  */
  13
  14 #define pr_fmt(fmt) "%s: " fmt, __func__
  15
  16 #include <linux/err.h>
  17 #include <linux/device.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/irq.h>
  24 #include <linux/io.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/delay.h>
  35 #include <linux/crypto.h>
  36 #include <linux/cryptohash.h>
  37 #include <crypto/scatterwalk.h>
  38 #include <crypto/algapi.h>
  39 #include <crypto/sha.h>
  40 #include <crypto/hash.h>
  41 #include <crypto/hmac.h>
  42 #include <crypto/internal/hash.h>
  43
  44 #define MD5_DIGEST_SIZE                 16
  45
  46 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  47 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  48 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  49
  50 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  51
  52 #define SHA_REG_CTRL                    0x18
  53 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  54 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  55 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  56 #define SHA_REG_CTRL_ALGO               (1 << 2)
  57 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  58 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  59
  60 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  61
  62 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  63 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  64 #define SHA_REG_MASK_IT_EN              (1 << 2)
  65 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  66 #define SHA_REG_AUTOIDLE                (1 << 0)
  67
  68 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  69 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  70
  71 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  72 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  73 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  74 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  75 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  76
  77 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  78 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  79 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  80 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  81 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  83 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  84
  85 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  86
  87 #define SHA_REG_IRQSTATUS               0x118
  88 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  89 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  90 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  91 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  92
  93 #define SHA_REG_IRQENA                  0x11C
  94 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  95 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  96 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
  97 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
  98
  99 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 100
 101 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 102
 103 /* mostly device flags */
 104 #define FLAGS_BUSY              0
 105 #define FLAGS_FINAL             1
 106 #define FLAGS_DMA_ACTIVE        2
 107 #define FLAGS_OUTPUT_READY      3
 108 #define FLAGS_INIT              4
 109 #define FLAGS_CPU               5
 110 #define FLAGS_DMA_READY         6
 111 #define FLAGS_AUTO_XOR          7
 112 #define FLAGS_BE32_SHA1         8
 113 #define FLAGS_SGS_COPIED        9
 114 #define FLAGS_SGS_ALLOCED       10
 115 #define FLAGS_HUGE              11
 116
 117 /* context flags */
 118 #define FLAGS_FINUP             16
 119
 120 #define FLAGS_MODE_SHIFT        18
 121 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 122 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 126 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 127 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 128
 129 #define FLAGS_HMAC              21
 130 #define FLAGS_ERROR             22
 131
 132 #define OP_UPDATE               1
 133 #define OP_FINAL                2
 134
 135 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 136 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 137
 138 #define BUFLEN                  SHA512_BLOCK_SIZE
 139 #define OMAP_SHA_DMA_THRESHOLD  256
 140
 141 #define OMAP_SHA_MAX_DMA_LEN    (1024 * 2048)
 142
 143 struct omap_sham_dev;
 144
 145 struct omap_sham_reqctx {
 146         struct omap_sham_dev    *dd;
 147         unsigned long           flags;
 148         unsigned long           op;
 149
 150         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 151         size_t                  digcnt;
 152         size_t                  bufcnt;
 153         size_t                  buflen;
 154
 155         /* walk state */
 156         struct scatterlist      *sg;
 157         struct scatterlist      sgl[2];
 158         int                     offset; /* offset in current sg */
 159         int                     sg_len;
 160         unsigned int            total;  /* total request */
 161
 162         u8                      buffer[0] OMAP_ALIGNED;
 163 };
 164
 165 struct omap_sham_hmac_ctx {
 166         struct crypto_shash     *shash;
 167         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 168         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 169 };
 170
 171 struct omap_sham_ctx {
 172         struct omap_sham_dev    *dd;
 173
 174         unsigned long           flags;
 175
 176         /* fallback stuff */
 177         struct crypto_shash     *fallback;
 178
 179         struct omap_sham_hmac_ctx base[0];
 180 };
 181
 182 #define OMAP_SHAM_QUEUE_LENGTH  10
 183
 184 struct omap_sham_algs_info {
 185         struct ahash_alg        *algs_list;
 186         unsigned int            size;
 187         unsigned int            registered;
 188 };
 189
 190 struct omap_sham_pdata {
 191         struct omap_sham_algs_info      *algs_info;
 192         unsigned int    algs_info_size;
 193         unsigned long   flags;
 194         int             digest_size;
 195
 196         void            (*copy_hash)(struct ahash_request *req, int out);
 197         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 198                                       int final, int dma);
 199         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 200         int             (*poll_irq)(struct omap_sham_dev *dd);
 201         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 202
 203         u32             odigest_ofs;
 204         u32             idigest_ofs;
 205         u32             din_ofs;
 206         u32             digcnt_ofs;
 207         u32             rev_ofs;
 208         u32             mask_ofs;
 209         u32             sysstatus_ofs;
 210         u32             mode_ofs;
 211         u32             length_ofs;
 212
 213         u32             major_mask;
 214         u32             major_shift;
 215         u32             minor_mask;
 216         u32             minor_shift;
 217 };
 218
 219 struct omap_sham_dev {
 220         struct list_head        list;
 221         unsigned long           phys_base;
 222         struct device           *dev;
 223         void __iomem            *io_base;
 224         int                     irq;
 225         spinlock_t              lock;
 226         int                     err;
 227         struct dma_chan         *dma_lch;
 228         struct tasklet_struct   done_task;
 229         u8                      polling_mode;
 230         u8                      xmit_buf[BUFLEN] OMAP_ALIGNED;
 231
 232         unsigned long           flags;
 233         int                     fallback_sz;
 234         struct crypto_queue     queue;
 235         struct ahash_request    *req;
 236
 237         const struct omap_sham_pdata    *pdata;
 238 };
 239
 240 struct omap_sham_drv {
 241         struct list_head        dev_list;
 242         spinlock_t              lock;
 243         unsigned long           flags;
 244 };
 245
 246 static struct omap_sham_drv sham = {
 247         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 248         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 249 };
 250
 251 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 252 {
 253         return __raw_readl(dd->io_base + offset);
 254 }
 255
 256 static inline void omap_sham_write(struct omap_sham_dev *dd,
 257                                         u32 offset, u32 value)
 258 {
 259         __raw_writel(value, dd->io_base + offset);
 260 }
 261
 262 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 263                                         u32 value, u32 mask)
 264 {
 265         u32 val;
 266
 267         val = omap_sham_read(dd, address);
 268         val &= ~mask;
 269         val |= value;
 270         omap_sham_write(dd, address, val);
 271 }
 272
 273 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 274 {
 275         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 276
 277         while (!(omap_sham_read(dd, offset) & bit)) {
 278                 if (time_is_before_jiffies(timeout))
 279                         return -ETIMEDOUT;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 286 {
 287         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 288         struct omap_sham_dev *dd = ctx->dd;
 289         u32 *hash = (u32 *)ctx->digest;
 290         int i;
 291
 292         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 293                 if (out)
 294                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 295                 else
 296                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 297         }
 298 }
 299
 300 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 301 {
 302         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 303         struct omap_sham_dev *dd = ctx->dd;
 304         int i;
 305
 306         if (ctx->flags & BIT(FLAGS_HMAC)) {
 307                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 308                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 309                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 310                 u32 *opad = (u32 *)bctx->opad;
 311
 312                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 313                         if (out)
 314                                 opad[i] = omap_sham_read(dd,
 315                                                 SHA_REG_ODIGEST(dd, i));
 316                         else
 317                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 318                                                 opad[i]);
 319                 }
 320         }
 321
 322         omap_sham_copy_hash_omap2(req, out);
 323 }
 324
 325 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 326 {
 327         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 328         u32 *in = (u32 *)ctx->digest;
 329         u32 *hash = (u32 *)req->result;
 330         int i, d, big_endian = 0;
 331
 332         if (!hash)
 333                 return;
 334
 335         switch (ctx->flags & FLAGS_MODE_MASK) {
 336         case FLAGS_MODE_MD5:
 337                 d = MD5_DIGEST_SIZE / sizeof(u32);
 338                 break;
 339         case FLAGS_MODE_SHA1:
 340                 /* OMAP2 SHA1 is big endian */
 341                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 342                         big_endian = 1;
 343                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 344                 break;
 345         case FLAGS_MODE_SHA224:
 346                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 347                 break;
 348         case FLAGS_MODE_SHA256:
 349                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 350                 break;
 351         case FLAGS_MODE_SHA384:
 352                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 353                 break;
 354         case FLAGS_MODE_SHA512:
 355                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 356                 break;
 357         default:
 358                 d = 0;
 359         }
 360
 361         if (big_endian)
 362                 for (i = 0; i < d; i++)
 363                         hash[i] = be32_to_cpu(in[i]);
 364         else
 365                 for (i = 0; i < d; i++)
 366                         hash[i] = le32_to_cpu(in[i]);
 367 }
 368
 369 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 370 {
 371         int err;
 372
 373         err = pm_runtime_get_sync(dd->dev);
 374         if (err < 0) {
 375                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 376                 return err;
 377         }
 378
 379         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 380                 set_bit(FLAGS_INIT, &dd->flags);
 381                 dd->err = 0;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 388                                  int final, int dma)
 389 {
 390         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 391         u32 val = length << 5, mask;
 392
 393         if (likely(ctx->digcnt))
 394                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 395
 396         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 397                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 398                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 399         /*
 400          * Setting ALGO_CONST only for the first iteration
 401          * and CLOSE_HASH only for the last one.
 402          */
 403         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 404                 val |= SHA_REG_CTRL_ALGO;
 405         if (!ctx->digcnt)
 406                 val |= SHA_REG_CTRL_ALGO_CONST;
 407         if (final)
 408                 val |= SHA_REG_CTRL_CLOSE_HASH;
 409
 410         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 411                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 412
 413         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 414 }
 415
 416 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 417 {
 418 }
 419
 420 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 421 {
 422         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 423 }
 424
 425 static int get_block_size(struct omap_sham_reqctx *ctx)
 426 {
 427         int d;
 428
 429         switch (ctx->flags & FLAGS_MODE_MASK) {
 430         case FLAGS_MODE_MD5:
 431         case FLAGS_MODE_SHA1:
 432                 d = SHA1_BLOCK_SIZE;
 433                 break;
 434         case FLAGS_MODE_SHA224:
 435         case FLAGS_MODE_SHA256:
 436                 d = SHA256_BLOCK_SIZE;
 437                 break;
 438         case FLAGS_MODE_SHA384:
 439         case FLAGS_MODE_SHA512:
 440                 d = SHA512_BLOCK_SIZE;
 441                 break;
 442         default:
 443                 d = 0;
 444         }
 445
 446         return d;
 447 }
 448
 449 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 450                                     u32 *value, int count)
 451 {
 452         for (; count--; value++, offset += 4)
 453                 omap_sham_write(dd, offset, *value);
 454 }
 455
 456 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 457                                  int final, int dma)
 458 {
 459         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 460         u32 val, mask;
 461
 462         /*
 463          * Setting ALGO_CONST only for the first iteration and
 464          * CLOSE_HASH only for the last one. Note that flags mode bits
 465          * correspond to algorithm encoding in mode register.
 466          */
 467         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 468         if (!ctx->digcnt) {
 469                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 470                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 471                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 472                 int bs, nr_dr;
 473
 474                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 475
 476                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 477                         bs = get_block_size(ctx);
 478                         nr_dr = bs / (2 * sizeof(u32));
 479                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 480                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 481                                           (u32 *)bctx->ipad, nr_dr);
 482                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 483                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 484                         ctx->digcnt += bs;
 485                 }
 486         }
 487
 488         if (final) {
 489                 val |= SHA_REG_MODE_CLOSE_HASH;
 490
 491                 if (ctx->flags & BIT(FLAGS_HMAC))
 492                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 493         }
 494
 495         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 496                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 497                SHA_REG_MODE_HMAC_KEY_PROC;
 498
 499         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 500         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 501         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 502         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 503                              SHA_REG_MASK_IT_EN |
 504                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 505                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 506 }
 507
 508 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 509 {
 510         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 511 }
 512
 513 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 514 {
 515         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 516                               SHA_REG_IRQSTATUS_INPUT_RDY);
 517 }
 518
 519 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 520                               int final)
 521 {
 522         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 523         int count, len32, bs32, offset = 0;
 524         const u32 *buffer;
 525         int mlen;
 526         struct sg_mapping_iter mi;
 527
 528         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 529                                                 ctx->digcnt, length, final);
 530
 531         dd->pdata->write_ctrl(dd, length, final, 0);
 532         dd->pdata->trigger(dd, length);
 533
 534         /* should be non-zero before next lines to disable clocks later */
 535         ctx->digcnt += length;
 536         ctx->total -= length;
 537
 538         if (final)
 539                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 540
 541         set_bit(FLAGS_CPU, &dd->flags);
 542
 543         len32 = DIV_ROUND_UP(length, sizeof(u32));
 544         bs32 = get_block_size(ctx) / sizeof(u32);
 545
 546         sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 547                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 548
 549         mlen = 0;
 550
 551         while (len32) {
 552                 if (dd->pdata->poll_irq(dd))
 553                         return -ETIMEDOUT;
 554
 555                 for (count = 0; count < min(len32, bs32); count++, offset++) {
 556                         if (!mlen) {
 557                                 sg_miter_next(&mi);
 558                                 mlen = mi.length;
 559                                 if (!mlen) {
 560                                         pr_err("sg miter failure.\n");
 561                                         return -EINVAL;
 562                                 }
 563                                 offset = 0;
 564                                 buffer = mi.addr;
 565                         }
 566                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 567                                         buffer[offset]);
 568                         mlen -= 4;
 569                 }
 570                 len32 -= min(len32, bs32);
 571         }
 572
 573         sg_miter_stop(&mi);
 574
 575         return -EINPROGRESS;
 576 }
 577
 578 static void omap_sham_dma_callback(void *param)
 579 {
 580         struct omap_sham_dev *dd = param;
 581
 582         set_bit(FLAGS_DMA_READY, &dd->flags);
 583         tasklet_schedule(&dd->done_task);
 584 }
 585
 586 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 587                               int final)
 588 {
 589         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 590         struct dma_async_tx_descriptor *tx;
 591         struct dma_slave_config cfg;
 592         int ret;
 593
 594         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 595                                                 ctx->digcnt, length, final);
 596
 597         if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 598                 dev_err(dd->dev, "dma_map_sg error\n");
 599                 return -EINVAL;
 600         }
 601
 602         memset(&cfg, 0, sizeof(cfg));
 603
 604         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 605         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 606         cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 607
 608         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 609         if (ret) {
 610                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 611                 return ret;
 612         }
 613
 614         tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 615                                      DMA_MEM_TO_DEV,
 616                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 617
 618         if (!tx) {
 619                 dev_err(dd->dev, "prep_slave_sg failed\n");
 620                 return -EINVAL;
 621         }
 622
 623         tx->callback = omap_sham_dma_callback;
 624         tx->callback_param = dd;
 625
 626         dd->pdata->write_ctrl(dd, length, final, 1);
 627
 628         ctx->digcnt += length;
 629         ctx->total -= length;
 630
 631         if (final)
 632                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 633
 634         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 635
 636         dmaengine_submit(tx);
 637         dma_async_issue_pending(dd->dma_lch);
 638
 639         dd->pdata->trigger(dd, length);
 640
 641         return -EINPROGRESS;
 642 }
 643
 644 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 645                                    struct scatterlist *sg, int bs, int new_len)
 646 {
 647         int n = sg_nents(sg);
 648         struct scatterlist *tmp;
 649         int offset = ctx->offset;
 650
 651         ctx->total = new_len;
 652
 653         if (ctx->bufcnt)
 654                 n++;
 655
 656         ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 657         if (!ctx->sg)
 658                 return -ENOMEM;
 659
 660         sg_init_table(ctx->sg, n);
 661
 662         tmp = ctx->sg;
 663
 664         ctx->sg_len = 0;
 665
 666         if (ctx->bufcnt) {
 667                 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 668                 tmp = sg_next(tmp);
 669                 ctx->sg_len++;
 670                 new_len -= ctx->bufcnt;
 671         }
 672
 673         while (sg && new_len) {
 674                 int len = sg->length - offset;
 675
 676                 if (len <= 0) {
 677                         offset -= sg->length;
 678                         sg = sg_next(sg);
 679                         continue;
 680                 }
 681
 682                 if (new_len < len)
 683                         len = new_len;
 684
 685                 if (len > 0) {
 686                         new_len -= len;
 687                         sg_set_page(tmp, sg_page(sg), len, sg->offset + offset);
 688                         offset = 0;
 689                         ctx->offset = 0;
 690                         ctx->sg_len++;
 691                         if (new_len <= 0)
 692                                 break;
 693                         tmp = sg_next(tmp);
 694                 }
 695
 696                 sg = sg_next(sg);
 697         }
 698
 699         if (tmp)
 700                 sg_mark_end(tmp);
 701
 702         set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 703
 704         ctx->offset += new_len - ctx->bufcnt;
 705         ctx->bufcnt = 0;
 706
 707         return 0;
 708 }
 709
 710 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 711                               struct scatterlist *sg, int bs,
 712                               unsigned int new_len)
 713 {
 714         int pages;
 715         void *buf;
 716
 717         pages = get_order(new_len);
 718
 719         buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 720         if (!buf) {
 721                 pr_err("Couldn't allocate pages for unaligned cases.\n");
 722                 return -ENOMEM;
 723         }
 724
 725         if (ctx->bufcnt)
 726                 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 727
 728         scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 729                                  min(new_len, ctx->total) - ctx->bufcnt, 0);
 730         sg_init_table(ctx->sgl, 1);
 731         sg_set_buf(ctx->sgl, buf, new_len);
 732         ctx->sg = ctx->sgl;
 733         set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 734         ctx->sg_len = 1;
 735         ctx->offset += new_len - ctx->bufcnt;
 736         ctx->bufcnt = 0;
 737         ctx->total = new_len;
 738
 739         return 0;
 740 }
 741
 742 static int omap_sham_align_sgs(struct scatterlist *sg,
 743                                int nbytes, int bs, bool final,
 744                                struct omap_sham_reqctx *rctx)
 745 {
 746         int n = 0;
 747         bool aligned = true;
 748         bool list_ok = true;
 749         struct scatterlist *sg_tmp = sg;
 750         int new_len;
 751         int offset = rctx->offset;
 752         int bufcnt = rctx->bufcnt;
 753
 754         if (!sg || !sg->length || !nbytes)
 755                 return 0;
 756
 757         new_len = nbytes;
 758
 759         if (offset)
 760                 list_ok = false;
 761
 762         if (final)
 763                 new_len = DIV_ROUND_UP(new_len, bs) * bs;
 764         else
 765                 new_len = (new_len - 1) / bs * bs;
 766
 767         if (!new_len)
 768                 return 0;
 769
 770         if (nbytes != new_len)
 771                 list_ok = false;
 772
 773         while (nbytes > 0 && sg_tmp) {
 774                 n++;
 775
 776                 if (bufcnt) {
 777                         if (!IS_ALIGNED(bufcnt, bs)) {
 778                                 aligned = false;
 779                                 break;
 780                         }
 781                         nbytes -= bufcnt;
 782                         bufcnt = 0;
 783                         if (!nbytes)
 784                                 list_ok = false;
 785
 786                         continue;
 787                 }
 788
 789 #ifdef CONFIG_ZONE_DMA
 790                 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
 791                         aligned = false;
 792                         break;
 793                 }
 794 #endif
 795
 796                 if (offset < sg_tmp->length) {
 797                         if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 798                                 aligned = false;
 799                                 break;
 800                         }
 801
 802                         if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 803                                 aligned = false;
 804                                 break;
 805                         }
 806                 }
 807
 808                 if (offset) {
 809                         offset -= sg_tmp->length;
 810                         if (offset < 0) {
 811                                 nbytes += offset;
 812                                 offset = 0;
 813                         }
 814                 } else {
 815                         nbytes -= sg_tmp->length;
 816                 }
 817
 818                 sg_tmp = sg_next(sg_tmp);
 819
 820                 if (nbytes < 0) {
 821                         list_ok = false;
 822                         break;
 823                 }
 824         }
 825
 826         if (new_len > OMAP_SHA_MAX_DMA_LEN) {
 827                 new_len = OMAP_SHA_MAX_DMA_LEN;
 828                 aligned = false;
 829         }
 830
 831         if (!aligned)
 832                 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 833         else if (!list_ok)
 834                 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 835
 836         rctx->total = new_len;
 837         rctx->offset += new_len;
 838         rctx->sg_len = n;
 839         if (rctx->bufcnt) {
 840                 sg_init_table(rctx->sgl, 2);
 841                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 842                 sg_chain(rctx->sgl, 2, sg);
 843                 rctx->sg = rctx->sgl;
 844         } else {
 845                 rctx->sg = sg;
 846         }
 847
 848         return 0;
 849 }
 850
 851 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
 852 {
 853         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 854         int bs;
 855         int ret;
 856         unsigned int nbytes;
 857         bool final = rctx->flags & BIT(FLAGS_FINUP);
 858         int hash_later;
 859
 860         bs = get_block_size(rctx);
 861
 862         nbytes = rctx->bufcnt;
 863
 864         if (update)
 865                 nbytes += req->nbytes - rctx->offset;
 866
 867         dev_dbg(rctx->dd->dev,
 868                 "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%d\n",
 869                 __func__, nbytes, bs, rctx->total, rctx->offset,
 870                 rctx->bufcnt);
 871
 872         if (!nbytes)
 873                 return 0;
 874
 875         rctx->total = nbytes;
 876
 877         if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 878                 int len = bs - rctx->bufcnt % bs;
 879
 880                 if (len > req->nbytes)
 881                         len = req->nbytes;
 882                 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 883                                          0, len, 0);
 884                 rctx->bufcnt += len;
 885                 rctx->offset = len;
 886         }
 887
 888         if (rctx->bufcnt)
 889                 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 890
 891         ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
 892         if (ret)
 893                 return ret;
 894
 895         hash_later = nbytes - rctx->total;
 896         if (hash_later < 0)
 897                 hash_later = 0;
 898
 899         if (hash_later) {
 900                 scatterwalk_map_and_copy(rctx->buffer,
 901                                          req->src,
 902                                          req->nbytes - hash_later,
 903                                          hash_later, 0);
 904
 905                 rctx->bufcnt = hash_later;
 906         } else {
 907                 rctx->bufcnt = 0;
 908         }
 909
 910         if (hash_later > rctx->buflen)
 911                 set_bit(FLAGS_HUGE, &rctx->dd->flags);
 912
 913         rctx->total = min(nbytes, rctx->total);
 914
 915         return 0;
 916 }
 917
 918 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 919 {
 920         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 921
 922         dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 923
 924         clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 925
 926         return 0;
 927 }
 928
 929 static int omap_sham_init(struct ahash_request *req)
 930 {
 931         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 932         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 933         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 934         struct omap_sham_dev *dd = NULL, *tmp;
 935         int bs = 0;
 936
 937         spin_lock_bh(&sham.lock);
 938         if (!tctx->dd) {
 939                 list_for_each_entry(tmp, &sham.dev_list, list) {
 940                         dd = tmp;
 941                         break;
 942                 }
 943                 tctx->dd = dd;
 944         } else {
 945                 dd = tctx->dd;
 946         }
 947         spin_unlock_bh(&sham.lock);
 948
 949         ctx->dd = dd;
 950
 951         ctx->flags = 0;
 952
 953         dev_dbg(dd->dev, "init: digest size: %d\n",
 954                 crypto_ahash_digestsize(tfm));
 955
 956         switch (crypto_ahash_digestsize(tfm)) {
 957         case MD5_DIGEST_SIZE:
 958                 ctx->flags |= FLAGS_MODE_MD5;
 959                 bs = SHA1_BLOCK_SIZE;
 960                 break;
 961         case SHA1_DIGEST_SIZE:
 962                 ctx->flags |= FLAGS_MODE_SHA1;
 963                 bs = SHA1_BLOCK_SIZE;
 964                 break;
 965         case SHA224_DIGEST_SIZE:
 966                 ctx->flags |= FLAGS_MODE_SHA224;
 967                 bs = SHA224_BLOCK_SIZE;
 968                 break;
 969         case SHA256_DIGEST_SIZE:
 970                 ctx->flags |= FLAGS_MODE_SHA256;
 971                 bs = SHA256_BLOCK_SIZE;
 972                 break;
 973         case SHA384_DIGEST_SIZE:
 974                 ctx->flags |= FLAGS_MODE_SHA384;
 975                 bs = SHA384_BLOCK_SIZE;
 976                 break;
 977         case SHA512_DIGEST_SIZE:
 978                 ctx->flags |= FLAGS_MODE_SHA512;
 979                 bs = SHA512_BLOCK_SIZE;
 980                 break;
 981         }
 982
 983         ctx->bufcnt = 0;
 984         ctx->digcnt = 0;
 985         ctx->total = 0;
 986         ctx->offset = 0;
 987         ctx->buflen = BUFLEN;
 988
 989         if (tctx->flags & BIT(FLAGS_HMAC)) {
 990                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 991                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 992
 993                         memcpy(ctx->buffer, bctx->ipad, bs);
 994                         ctx->bufcnt = bs;
 995                 }
 996
 997                 ctx->flags |= BIT(FLAGS_HMAC);
 998         }
 999
1000         return 0;
1001
1002 }
1003
1004 static int omap_sham_update_req(struct omap_sham_dev *dd)
1005 {
1006         struct ahash_request *req = dd->req;
1007         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1008         int err;
1009         bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
1010                         !(dd->flags & BIT(FLAGS_HUGE));
1011
1012         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, final: %d",
1013                 ctx->total, ctx->digcnt, final);
1014
1015         if (ctx->total < get_block_size(ctx) ||
1016             ctx->total < dd->fallback_sz)
1017                 ctx->flags |= BIT(FLAGS_CPU);
1018
1019         if (ctx->flags & BIT(FLAGS_CPU))
1020                 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1021         else
1022                 err = omap_sham_xmit_dma(dd, ctx->total, final);
1023
1024         /* wait for dma completion before can take more data */
1025         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1026
1027         return err;
1028 }
1029
1030 static int omap_sham_final_req(struct omap_sham_dev *dd)
1031 {
1032         struct ahash_request *req = dd->req;
1033         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1034         int err = 0, use_dma = 1;
1035
1036         if (dd->flags & BIT(FLAGS_HUGE))
1037                 return 0;
1038
1039         if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1040                 /*
1041                  * faster to handle last block with cpu or
1042                  * use cpu when dma is not present.
1043                  */
1044                 use_dma = 0;
1045
1046         if (use_dma)
1047                 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1048         else
1049                 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1050
1051         ctx->bufcnt = 0;
1052
1053         dev_dbg(dd->dev, "final_req: err: %d\n", err);
1054
1055         return err;
1056 }
1057
1058 static int omap_sham_finish_hmac(struct ahash_request *req)
1059 {
1060         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1061         struct omap_sham_hmac_ctx *bctx = tctx->base;
1062         int bs = crypto_shash_blocksize(bctx->shash);
1063         int ds = crypto_shash_digestsize(bctx->shash);
1064         SHASH_DESC_ON_STACK(shash, bctx->shash);
1065
1066         shash->tfm = bctx->shash;
1067
1068         return crypto_shash_init(shash) ?:
1069                crypto_shash_update(shash, bctx->opad, bs) ?:
1070                crypto_shash_finup(shash, req->result, ds, req->result);
1071 }
1072
1073 static int omap_sham_finish(struct ahash_request *req)
1074 {
1075         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1076         struct omap_sham_dev *dd = ctx->dd;
1077         int err = 0;
1078
1079         if (ctx->digcnt) {
1080                 omap_sham_copy_ready_hash(req);
1081                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1082                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1083                         err = omap_sham_finish_hmac(req);
1084         }
1085
1086         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1087
1088         return err;
1089 }
1090
1091 static void omap_sham_finish_req(struct ahash_request *req, int err)
1092 {
1093         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1094         struct omap_sham_dev *dd = ctx->dd;
1095
1096         if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1097                 free_pages((unsigned long)sg_virt(ctx->sg),
1098                            get_order(ctx->sg->length));
1099
1100         if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1101                 kfree(ctx->sg);
1102
1103         ctx->sg = NULL;
1104
1105         dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1106
1107         if (dd->flags & BIT(FLAGS_HUGE)) {
1108                 dd->flags &= ~(BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) |
1109                                 BIT(FLAGS_OUTPUT_READY) | BIT(FLAGS_HUGE));
1110                 omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1111                 if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) {
1112                         err = omap_sham_update_req(dd);
1113                         if (err != -EINPROGRESS &&
1114                             (ctx->flags & BIT(FLAGS_FINUP)))
1115                                 err = omap_sham_final_req(dd);
1116                 } else if (ctx->op == OP_FINAL) {
1117                         omap_sham_final_req(dd);
1118                 }
1119                 return;
1120         }
1121
1122         if (!err) {
1123                 dd->pdata->copy_hash(req, 1);
1124                 if (test_bit(FLAGS_FINAL, &dd->flags))
1125                         err = omap_sham_finish(req);
1126         } else {
1127                 ctx->flags |= BIT(FLAGS_ERROR);
1128         }
1129
1130         /* atomic operation is not needed here */
1131         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1132                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1133
1134         pm_runtime_mark_last_busy(dd->dev);
1135         pm_runtime_put_autosuspend(dd->dev);
1136
1137         ctx->offset = 0;
1138
1139         if (req->base.complete)
1140                 req->base.complete(&req->base, err);
1141 }
1142
1143 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1144                                   struct ahash_request *req)
1145 {
1146         struct crypto_async_request *async_req, *backlog;
1147         struct omap_sham_reqctx *ctx;
1148         unsigned long flags;
1149         int err = 0, ret = 0;
1150
1151 retry:
1152         spin_lock_irqsave(&dd->lock, flags);
1153         if (req)
1154                 ret = ahash_enqueue_request(&dd->queue, req);
1155         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1156                 spin_unlock_irqrestore(&dd->lock, flags);
1157                 return ret;
1158         }
1159         backlog = crypto_get_backlog(&dd->queue);
1160         async_req = crypto_dequeue_request(&dd->queue);
1161         if (async_req)
1162                 set_bit(FLAGS_BUSY, &dd->flags);
1163         spin_unlock_irqrestore(&dd->lock, flags);
1164
1165         if (!async_req)
1166                 return ret;
1167
1168         if (backlog)
1169                 backlog->complete(backlog, -EINPROGRESS);
1170
1171         req = ahash_request_cast(async_req);
1172         dd->req = req;
1173         ctx = ahash_request_ctx(req);
1174
1175         err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1176         if (err || !ctx->total)
1177                 goto err1;
1178
1179         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1180                                                 ctx->op, req->nbytes);
1181
1182         err = omap_sham_hw_init(dd);
1183         if (err)
1184                 goto err1;
1185
1186         if (ctx->digcnt)
1187                 /* request has changed - restore hash */
1188                 dd->pdata->copy_hash(req, 0);
1189
1190         if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) {
1191                 err = omap_sham_update_req(dd);
1192                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1193                         /* no final() after finup() */
1194                         err = omap_sham_final_req(dd);
1195         } else if (ctx->op == OP_FINAL) {
1196                 err = omap_sham_final_req(dd);
1197         }
1198 err1:
1199         dev_dbg(dd->dev, "exit, err: %d\n", err);
1200
1201         if (err != -EINPROGRESS) {
1202                 /* done_task will not finish it, so do it here */
1203                 omap_sham_finish_req(req, err);
1204                 req = NULL;
1205
1206                 /*
1207                  * Execute next request immediately if there is anything
1208                  * in queue.
1209                  */
1210                 goto retry;
1211         }
1212
1213         return ret;
1214 }
1215
1216 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1217 {
1218         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1219         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1220         struct omap_sham_dev *dd = tctx->dd;
1221
1222         ctx->op = op;
1223
1224         return omap_sham_handle_queue(dd, req);
1225 }
1226
1227 static int omap_sham_update(struct ahash_request *req)
1228 {
1229         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1230         struct omap_sham_dev *dd = ctx->dd;
1231
1232         if (!req->nbytes)
1233                 return 0;
1234
1235         if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1236                 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1237                                          0, req->nbytes, 0);
1238                 ctx->bufcnt += req->nbytes;
1239                 return 0;
1240         }
1241
1242         if (dd->polling_mode)
1243                 ctx->flags |= BIT(FLAGS_CPU);
1244
1245         return omap_sham_enqueue(req, OP_UPDATE);
1246 }
1247
1248 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1249                                   const u8 *data, unsigned int len, u8 *out)
1250 {
1251         SHASH_DESC_ON_STACK(shash, tfm);
1252
1253         shash->tfm = tfm;
1254
1255         return crypto_shash_digest(shash, data, len, out);
1256 }
1257
1258 static int omap_sham_final_shash(struct ahash_request *req)
1259 {
1260         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1261         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1262         int offset = 0;
1263
1264         /*
1265          * If we are running HMAC on limited hardware support, skip
1266          * the ipad in the beginning of the buffer if we are going for
1267          * software fallback algorithm.
1268          */
1269         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1270             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1271                 offset = get_block_size(ctx);
1272
1273         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1274                                       ctx->buffer + offset,
1275                                       ctx->bufcnt - offset, req->result);
1276 }
1277
1278 static int omap_sham_final(struct ahash_request *req)
1279 {
1280         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1281
1282         ctx->flags |= BIT(FLAGS_FINUP);
1283
1284         if (ctx->flags & BIT(FLAGS_ERROR))
1285                 return 0; /* uncompleted hash is not needed */
1286
1287         /*
1288          * OMAP HW accel works only with buffers >= 9.
1289          * HMAC is always >= 9 because ipad == block size.
1290          * If buffersize is less than fallback_sz, we use fallback
1291          * SW encoding, as using DMA + HW in this case doesn't provide
1292          * any benefit.
1293          */
1294         if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1295                 return omap_sham_final_shash(req);
1296         else if (ctx->bufcnt)
1297                 return omap_sham_enqueue(req, OP_FINAL);
1298
1299         /* copy ready hash (+ finalize hmac) */
1300         return omap_sham_finish(req);
1301 }
1302
1303 static int omap_sham_finup(struct ahash_request *req)
1304 {
1305         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1306         int err1, err2;
1307
1308         ctx->flags |= BIT(FLAGS_FINUP);
1309
1310         err1 = omap_sham_update(req);
1311         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1312                 return err1;
1313         /*
1314          * final() has to be always called to cleanup resources
1315          * even if udpate() failed, except EINPROGRESS
1316          */
1317         err2 = omap_sham_final(req);
1318
1319         return err1 ?: err2;
1320 }
1321
1322 static int omap_sham_digest(struct ahash_request *req)
1323 {
1324         return omap_sham_init(req) ?: omap_sham_finup(req);
1325 }
1326
1327 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1328                       unsigned int keylen)
1329 {
1330         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1331         struct omap_sham_hmac_ctx *bctx = tctx->base;
1332         int bs = crypto_shash_blocksize(bctx->shash);
1333         int ds = crypto_shash_digestsize(bctx->shash);
1334         struct omap_sham_dev *dd = NULL, *tmp;
1335         int err, i;
1336
1337         spin_lock_bh(&sham.lock);
1338         if (!tctx->dd) {
1339                 list_for_each_entry(tmp, &sham.dev_list, list) {
1340                         dd = tmp;
1341                         break;
1342                 }
1343                 tctx->dd = dd;
1344         } else {
1345                 dd = tctx->dd;
1346         }
1347         spin_unlock_bh(&sham.lock);
1348
1349         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1350         if (err)
1351                 return err;
1352
1353         if (keylen > bs) {
1354                 err = omap_sham_shash_digest(bctx->shash,
1355                                 crypto_shash_get_flags(bctx->shash),
1356                                 key, keylen, bctx->ipad);
1357                 if (err)
1358                         return err;
1359                 keylen = ds;
1360         } else {
1361                 memcpy(bctx->ipad, key, keylen);
1362         }
1363
1364         memset(bctx->ipad + keylen, 0, bs - keylen);
1365
1366         if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1367                 memcpy(bctx->opad, bctx->ipad, bs);
1368
1369                 for (i = 0; i < bs; i++) {
1370                         bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1371                         bctx->opad[i] ^= HMAC_OPAD_VALUE;
1372                 }
1373         }
1374
1375         return err;
1376 }
1377
1378 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1379 {
1380         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1381         const char *alg_name = crypto_tfm_alg_name(tfm);
1382
1383         /* Allocate a fallback and abort if it failed. */
1384         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1385                                             CRYPTO_ALG_NEED_FALLBACK);
1386         if (IS_ERR(tctx->fallback)) {
1387                 pr_err("omap-sham: fallback driver '%s' "
1388                                 "could not be loaded.\n", alg_name);
1389                 return PTR_ERR(tctx->fallback);
1390         }
1391
1392         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1393                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1394
1395         if (alg_base) {
1396                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1397                 tctx->flags |= BIT(FLAGS_HMAC);
1398                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1399                                                 CRYPTO_ALG_NEED_FALLBACK);
1400                 if (IS_ERR(bctx->shash)) {
1401                         pr_err("omap-sham: base driver '%s' "
1402                                         "could not be loaded.\n", alg_base);
1403                         crypto_free_shash(tctx->fallback);
1404                         return PTR_ERR(bctx->shash);
1405                 }
1406
1407         }
1408
1409         return 0;
1410 }
1411
1412 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1413 {
1414         return omap_sham_cra_init_alg(tfm, NULL);
1415 }
1416
1417 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1418 {
1419         return omap_sham_cra_init_alg(tfm, "sha1");
1420 }
1421
1422 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1423 {
1424         return omap_sham_cra_init_alg(tfm, "sha224");
1425 }
1426
1427 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1428 {
1429         return omap_sham_cra_init_alg(tfm, "sha256");
1430 }
1431
1432 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1433 {
1434         return omap_sham_cra_init_alg(tfm, "md5");
1435 }
1436
1437 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1438 {
1439         return omap_sham_cra_init_alg(tfm, "sha384");
1440 }
1441
1442 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1443 {
1444         return omap_sham_cra_init_alg(tfm, "sha512");
1445 }
1446
1447 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1448 {
1449         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1450
1451         crypto_free_shash(tctx->fallback);
1452         tctx->fallback = NULL;
1453
1454         if (tctx->flags & BIT(FLAGS_HMAC)) {
1455                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1456                 crypto_free_shash(bctx->shash);
1457         }
1458 }
1459
1460 static int omap_sham_export(struct ahash_request *req, void *out)
1461 {
1462         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1463
1464         memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1465
1466         return 0;
1467 }
1468
1469 static int omap_sham_import(struct ahash_request *req, const void *in)
1470 {
1471         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1472         const struct omap_sham_reqctx *ctx_in = in;
1473
1474         memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1475
1476         return 0;
1477 }
1478
1479 static struct ahash_alg algs_sha1_md5[] = {
1480 {
1481         .init           = omap_sham_init,
1482         .update         = omap_sham_update,
1483         .final          = omap_sham_final,
1484         .finup          = omap_sham_finup,
1485         .digest         = omap_sham_digest,
1486         .halg.digestsize        = SHA1_DIGEST_SIZE,
1487         .halg.base      = {
1488                 .cra_name               = "sha1",
1489                 .cra_driver_name        = "omap-sha1",
1490                 .cra_priority           = 400,
1491                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1492                                                 CRYPTO_ALG_ASYNC |
1493                                                 CRYPTO_ALG_NEED_FALLBACK,
1494                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1495                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1496                 .cra_alignmask          = OMAP_ALIGN_MASK,
1497                 .cra_module             = THIS_MODULE,
1498                 .cra_init               = omap_sham_cra_init,
1499                 .cra_exit               = omap_sham_cra_exit,
1500         }
1501 },
1502 {
1503         .init           = omap_sham_init,
1504         .update         = omap_sham_update,
1505         .final          = omap_sham_final,
1506         .finup          = omap_sham_finup,
1507         .digest         = omap_sham_digest,
1508         .halg.digestsize        = MD5_DIGEST_SIZE,
1509         .halg.base      = {
1510                 .cra_name               = "md5",
1511                 .cra_driver_name        = "omap-md5",
1512                 .cra_priority           = 400,
1513                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1514                                                 CRYPTO_ALG_ASYNC |
1515                                                 CRYPTO_ALG_NEED_FALLBACK,
1516                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1517                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1518                 .cra_alignmask          = OMAP_ALIGN_MASK,
1519                 .cra_module             = THIS_MODULE,
1520                 .cra_init               = omap_sham_cra_init,
1521                 .cra_exit               = omap_sham_cra_exit,
1522         }
1523 },
1524 {
1525         .init           = omap_sham_init,
1526         .update         = omap_sham_update,
1527         .final          = omap_sham_final,
1528         .finup          = omap_sham_finup,
1529         .digest         = omap_sham_digest,
1530         .setkey         = omap_sham_setkey,
1531         .halg.digestsize        = SHA1_DIGEST_SIZE,
1532         .halg.base      = {
1533                 .cra_name               = "hmac(sha1)",
1534                 .cra_driver_name        = "omap-hmac-sha1",
1535                 .cra_priority           = 400,
1536                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1537                                                 CRYPTO_ALG_ASYNC |
1538                                                 CRYPTO_ALG_NEED_FALLBACK,
1539                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1540                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1541                                         sizeof(struct omap_sham_hmac_ctx),
1542                 .cra_alignmask          = OMAP_ALIGN_MASK,
1543                 .cra_module             = THIS_MODULE,
1544                 .cra_init               = omap_sham_cra_sha1_init,
1545                 .cra_exit               = omap_sham_cra_exit,
1546         }
1547 },
1548 {
1549         .init           = omap_sham_init,
1550         .update         = omap_sham_update,
1551         .final          = omap_sham_final,
1552         .finup          = omap_sham_finup,
1553         .digest         = omap_sham_digest,
1554         .setkey         = omap_sham_setkey,
1555         .halg.digestsize        = MD5_DIGEST_SIZE,
1556         .halg.base      = {
1557                 .cra_name               = "hmac(md5)",
1558                 .cra_driver_name        = "omap-hmac-md5",
1559                 .cra_priority           = 400,
1560                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1561                                                 CRYPTO_ALG_ASYNC |
1562                                                 CRYPTO_ALG_NEED_FALLBACK,
1563                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1564                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1565                                         sizeof(struct omap_sham_hmac_ctx),
1566                 .cra_alignmask          = OMAP_ALIGN_MASK,
1567                 .cra_module             = THIS_MODULE,
1568                 .cra_init               = omap_sham_cra_md5_init,
1569                 .cra_exit               = omap_sham_cra_exit,
1570         }
1571 }
1572 };
1573
1574 /* OMAP4 has some algs in addition to what OMAP2 has */
1575 static struct ahash_alg algs_sha224_sha256[] = {
1576 {
1577         .init           = omap_sham_init,
1578         .update         = omap_sham_update,
1579         .final          = omap_sham_final,
1580         .finup          = omap_sham_finup,
1581         .digest         = omap_sham_digest,
1582         .halg.digestsize        = SHA224_DIGEST_SIZE,
1583         .halg.base      = {
1584                 .cra_name               = "sha224",
1585                 .cra_driver_name        = "omap-sha224",
1586                 .cra_priority           = 400,
1587                 .cra_flags              = CRYPTO_ALG_ASYNC |
1588                                                 CRYPTO_ALG_NEED_FALLBACK,
1589                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1590                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1591                 .cra_alignmask          = OMAP_ALIGN_MASK,
1592                 .cra_module             = THIS_MODULE,
1593                 .cra_init               = omap_sham_cra_init,
1594                 .cra_exit               = omap_sham_cra_exit,
1595         }
1596 },
1597 {
1598         .init           = omap_sham_init,
1599         .update         = omap_sham_update,
1600         .final          = omap_sham_final,
1601         .finup          = omap_sham_finup,
1602         .digest         = omap_sham_digest,
1603         .halg.digestsize        = SHA256_DIGEST_SIZE,
1604         .halg.base      = {
1605                 .cra_name               = "sha256",
1606                 .cra_driver_name        = "omap-sha256",
1607                 .cra_priority           = 400,
1608                 .cra_flags              = CRYPTO_ALG_ASYNC |
1609                                                 CRYPTO_ALG_NEED_FALLBACK,
1610                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1611                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1612                 .cra_alignmask          = OMAP_ALIGN_MASK,
1613                 .cra_module             = THIS_MODULE,
1614                 .cra_init               = omap_sham_cra_init,
1615                 .cra_exit               = omap_sham_cra_exit,
1616         }
1617 },
1618 {
1619         .init           = omap_sham_init,
1620         .update         = omap_sham_update,
1621         .final          = omap_sham_final,
1622         .finup          = omap_sham_finup,
1623         .digest         = omap_sham_digest,
1624         .setkey         = omap_sham_setkey,
1625         .halg.digestsize        = SHA224_DIGEST_SIZE,
1626         .halg.base      = {
1627                 .cra_name               = "hmac(sha224)",
1628                 .cra_driver_name        = "omap-hmac-sha224",
1629                 .cra_priority           = 400,
1630                 .cra_flags              = CRYPTO_ALG_ASYNC |
1631                                                 CRYPTO_ALG_NEED_FALLBACK,
1632                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1633                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1634                                         sizeof(struct omap_sham_hmac_ctx),
1635                 .cra_alignmask          = OMAP_ALIGN_MASK,
1636                 .cra_module             = THIS_MODULE,
1637                 .cra_init               = omap_sham_cra_sha224_init,
1638                 .cra_exit               = omap_sham_cra_exit,
1639         }
1640 },
1641 {
1642         .init           = omap_sham_init,
1643         .update         = omap_sham_update,
1644         .final          = omap_sham_final,
1645         .finup          = omap_sham_finup,
1646         .digest         = omap_sham_digest,
1647         .setkey         = omap_sham_setkey,
1648         .halg.digestsize        = SHA256_DIGEST_SIZE,
1649         .halg.base      = {
1650                 .cra_name               = "hmac(sha256)",
1651                 .cra_driver_name        = "omap-hmac-sha256",
1652                 .cra_priority           = 400,
1653                 .cra_flags              = CRYPTO_ALG_ASYNC |
1654                                                 CRYPTO_ALG_NEED_FALLBACK,
1655                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1656                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1657                                         sizeof(struct omap_sham_hmac_ctx),
1658                 .cra_alignmask          = OMAP_ALIGN_MASK,
1659                 .cra_module             = THIS_MODULE,
1660                 .cra_init               = omap_sham_cra_sha256_init,
1661                 .cra_exit               = omap_sham_cra_exit,
1662         }
1663 },
1664 };
1665
1666 static struct ahash_alg algs_sha384_sha512[] = {
1667 {
1668         .init           = omap_sham_init,
1669         .update         = omap_sham_update,
1670         .final          = omap_sham_final,
1671         .finup          = omap_sham_finup,
1672         .digest         = omap_sham_digest,
1673         .halg.digestsize        = SHA384_DIGEST_SIZE,
1674         .halg.base      = {
1675                 .cra_name               = "sha384",
1676                 .cra_driver_name        = "omap-sha384",
1677                 .cra_priority           = 400,
1678                 .cra_flags              = CRYPTO_ALG_ASYNC |
1679                                                 CRYPTO_ALG_NEED_FALLBACK,
1680                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1681                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1682                 .cra_alignmask          = OMAP_ALIGN_MASK,
1683                 .cra_module             = THIS_MODULE,
1684                 .cra_init               = omap_sham_cra_init,
1685                 .cra_exit               = omap_sham_cra_exit,
1686         }
1687 },
1688 {
1689         .init           = omap_sham_init,
1690         .update         = omap_sham_update,
1691         .final          = omap_sham_final,
1692         .finup          = omap_sham_finup,
1693         .digest         = omap_sham_digest,
1694         .halg.digestsize        = SHA512_DIGEST_SIZE,
1695         .halg.base      = {
1696                 .cra_name               = "sha512",
1697                 .cra_driver_name        = "omap-sha512",
1698                 .cra_priority           = 400,
1699                 .cra_flags              = CRYPTO_ALG_ASYNC |
1700                                                 CRYPTO_ALG_NEED_FALLBACK,
1701                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1702                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1703                 .cra_alignmask          = OMAP_ALIGN_MASK,
1704                 .cra_module             = THIS_MODULE,
1705                 .cra_init               = omap_sham_cra_init,
1706                 .cra_exit               = omap_sham_cra_exit,
1707         }
1708 },
1709 {
1710         .init           = omap_sham_init,
1711         .update         = omap_sham_update,
1712         .final          = omap_sham_final,
1713         .finup          = omap_sham_finup,
1714         .digest         = omap_sham_digest,
1715         .setkey         = omap_sham_setkey,
1716         .halg.digestsize        = SHA384_DIGEST_SIZE,
1717         .halg.base      = {
1718                 .cra_name               = "hmac(sha384)",
1719                 .cra_driver_name        = "omap-hmac-sha384",
1720                 .cra_priority           = 400,
1721                 .cra_flags              = CRYPTO_ALG_ASYNC |
1722                                                 CRYPTO_ALG_NEED_FALLBACK,
1723                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1724                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1725                                         sizeof(struct omap_sham_hmac_ctx),
1726                 .cra_alignmask          = OMAP_ALIGN_MASK,
1727                 .cra_module             = THIS_MODULE,
1728                 .cra_init               = omap_sham_cra_sha384_init,
1729                 .cra_exit               = omap_sham_cra_exit,
1730         }
1731 },
1732 {
1733         .init           = omap_sham_init,
1734         .update         = omap_sham_update,
1735         .final          = omap_sham_final,
1736         .finup          = omap_sham_finup,
1737         .digest         = omap_sham_digest,
1738         .setkey         = omap_sham_setkey,
1739         .halg.digestsize        = SHA512_DIGEST_SIZE,
1740         .halg.base      = {
1741                 .cra_name               = "hmac(sha512)",
1742                 .cra_driver_name        = "omap-hmac-sha512",
1743                 .cra_priority           = 400,
1744                 .cra_flags              = CRYPTO_ALG_ASYNC |
1745                                                 CRYPTO_ALG_NEED_FALLBACK,
1746                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1747                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1748                                         sizeof(struct omap_sham_hmac_ctx),
1749                 .cra_alignmask          = OMAP_ALIGN_MASK,
1750                 .cra_module             = THIS_MODULE,
1751                 .cra_init               = omap_sham_cra_sha512_init,
1752                 .cra_exit               = omap_sham_cra_exit,
1753         }
1754 },
1755 };
1756
1757 static void omap_sham_done_task(unsigned long data)
1758 {
1759         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1760         int err = 0;
1761
1762         dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags);
1763
1764         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1765                 omap_sham_handle_queue(dd, NULL);
1766                 return;
1767         }
1768
1769         if (test_bit(FLAGS_CPU, &dd->flags)) {
1770                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1771                         goto finish;
1772         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1773                 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1774                         omap_sham_update_dma_stop(dd);
1775                         if (dd->err) {
1776                                 err = dd->err;
1777                                 goto finish;
1778                         }
1779                 }
1780                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1781                         /* hash or semi-hash ready */
1782                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1783                         goto finish;
1784                 }
1785         }
1786
1787         return;
1788
1789 finish:
1790         dev_dbg(dd->dev, "update done: err: %d\n", err);
1791         /* finish curent request */
1792         omap_sham_finish_req(dd->req, err);
1793
1794         /* If we are not busy, process next req */
1795         if (!test_bit(FLAGS_BUSY, &dd->flags))
1796                 omap_sham_handle_queue(dd, NULL);
1797 }
1798
1799 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1800 {
1801         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1802                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1803         } else {
1804                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1805                 tasklet_schedule(&dd->done_task);
1806         }
1807
1808         return IRQ_HANDLED;
1809 }
1810
1811 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1812 {
1813         struct omap_sham_dev *dd = dev_id;
1814
1815         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1816                 /* final -> allow device to go to power-saving mode */
1817                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1818
1819         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1820                                  SHA_REG_CTRL_OUTPUT_READY);
1821         omap_sham_read(dd, SHA_REG_CTRL);
1822
1823         return omap_sham_irq_common(dd);
1824 }
1825
1826 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1827 {
1828         struct omap_sham_dev *dd = dev_id;
1829
1830         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1831
1832         return omap_sham_irq_common(dd);
1833 }
1834
1835 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1836         {
1837                 .algs_list      = algs_sha1_md5,
1838                 .size           = ARRAY_SIZE(algs_sha1_md5),
1839         },
1840 };
1841
1842 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1843         .algs_info      = omap_sham_algs_info_omap2,
1844         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1845         .flags          = BIT(FLAGS_BE32_SHA1),
1846         .digest_size    = SHA1_DIGEST_SIZE,
1847         .copy_hash      = omap_sham_copy_hash_omap2,
1848         .write_ctrl     = omap_sham_write_ctrl_omap2,
1849         .trigger        = omap_sham_trigger_omap2,
1850         .poll_irq       = omap_sham_poll_irq_omap2,
1851         .intr_hdlr      = omap_sham_irq_omap2,
1852         .idigest_ofs    = 0x00,
1853         .din_ofs        = 0x1c,
1854         .digcnt_ofs     = 0x14,
1855         .rev_ofs        = 0x5c,
1856         .mask_ofs       = 0x60,
1857         .sysstatus_ofs  = 0x64,
1858         .major_mask     = 0xf0,
1859         .major_shift    = 4,
1860         .minor_mask     = 0x0f,
1861         .minor_shift    = 0,
1862 };
1863
1864 #ifdef CONFIG_OF
1865 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1866         {
1867                 .algs_list      = algs_sha1_md5,
1868                 .size           = ARRAY_SIZE(algs_sha1_md5),
1869         },
1870         {
1871                 .algs_list      = algs_sha224_sha256,
1872                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1873         },
1874 };
1875
1876 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1877         .algs_info      = omap_sham_algs_info_omap4,
1878         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1879         .flags          = BIT(FLAGS_AUTO_XOR),
1880         .digest_size    = SHA256_DIGEST_SIZE,
1881         .copy_hash      = omap_sham_copy_hash_omap4,
1882         .write_ctrl     = omap_sham_write_ctrl_omap4,
1883         .trigger        = omap_sham_trigger_omap4,
1884         .poll_irq       = omap_sham_poll_irq_omap4,
1885         .intr_hdlr      = omap_sham_irq_omap4,
1886         .idigest_ofs    = 0x020,
1887         .odigest_ofs    = 0x0,
1888         .din_ofs        = 0x080,
1889         .digcnt_ofs     = 0x040,
1890         .rev_ofs        = 0x100,
1891         .mask_ofs       = 0x110,
1892         .sysstatus_ofs  = 0x114,
1893         .mode_ofs       = 0x44,
1894         .length_ofs     = 0x48,
1895         .major_mask     = 0x0700,
1896         .major_shift    = 8,
1897         .minor_mask     = 0x003f,
1898         .minor_shift    = 0,
1899 };
1900
1901 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1902         {
1903                 .algs_list      = algs_sha1_md5,
1904                 .size           = ARRAY_SIZE(algs_sha1_md5),
1905         },
1906         {
1907                 .algs_list      = algs_sha224_sha256,
1908                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1909         },
1910         {
1911                 .algs_list      = algs_sha384_sha512,
1912                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1913         },
1914 };
1915
1916 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1917         .algs_info      = omap_sham_algs_info_omap5,
1918         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1919         .flags          = BIT(FLAGS_AUTO_XOR),
1920         .digest_size    = SHA512_DIGEST_SIZE,
1921         .copy_hash      = omap_sham_copy_hash_omap4,
1922         .write_ctrl     = omap_sham_write_ctrl_omap4,
1923         .trigger        = omap_sham_trigger_omap4,
1924         .poll_irq       = omap_sham_poll_irq_omap4,
1925         .intr_hdlr      = omap_sham_irq_omap4,
1926         .idigest_ofs    = 0x240,
1927         .odigest_ofs    = 0x200,
1928         .din_ofs        = 0x080,
1929         .digcnt_ofs     = 0x280,
1930         .rev_ofs        = 0x100,
1931         .mask_ofs       = 0x110,
1932         .sysstatus_ofs  = 0x114,
1933         .mode_ofs       = 0x284,
1934         .length_ofs     = 0x288,
1935         .major_mask     = 0x0700,
1936         .major_shift    = 8,
1937         .minor_mask     = 0x003f,
1938         .minor_shift    = 0,
1939 };
1940
1941 static const struct of_device_id omap_sham_of_match[] = {
1942         {
1943                 .compatible     = "ti,omap2-sham",
1944                 .data           = &omap_sham_pdata_omap2,
1945         },
1946         {
1947                 .compatible     = "ti,omap3-sham",
1948                 .data           = &omap_sham_pdata_omap2,
1949         },
1950         {
1951                 .compatible     = "ti,omap4-sham",
1952                 .data           = &omap_sham_pdata_omap4,
1953         },
1954         {
1955                 .compatible     = "ti,omap5-sham",
1956                 .data           = &omap_sham_pdata_omap5,
1957         },
1958         {},
1959 };
1960 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1961
1962 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1963                 struct device *dev, struct resource *res)
1964 {
1965         struct device_node *node = dev->of_node;
1966         int err = 0;
1967
1968         dd->pdata = of_device_get_match_data(dev);
1969         if (!dd->pdata) {
1970                 dev_err(dev, "no compatible OF match\n");
1971                 err = -EINVAL;
1972                 goto err;
1973         }
1974
1975         err = of_address_to_resource(node, 0, res);
1976         if (err < 0) {
1977                 dev_err(dev, "can't translate OF node address\n");
1978                 err = -EINVAL;
1979                 goto err;
1980         }
1981
1982         dd->irq = irq_of_parse_and_map(node, 0);
1983         if (!dd->irq) {
1984                 dev_err(dev, "can't translate OF irq value\n");
1985                 err = -EINVAL;
1986                 goto err;
1987         }
1988
1989 err:
1990         return err;
1991 }
1992 #else
1993 static const struct of_device_id omap_sham_of_match[] = {
1994         {},
1995 };
1996
1997 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1998                 struct device *dev, struct resource *res)
1999 {
2000         return -EINVAL;
2001 }
2002 #endif
2003
2004 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
2005                 struct platform_device *pdev, struct resource *res)
2006 {
2007         struct device *dev = &pdev->dev;
2008         struct resource *r;
2009         int err = 0;
2010
2011         /* Get the base address */
2012         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2013         if (!r) {
2014                 dev_err(dev, "no MEM resource info\n");
2015                 err = -ENODEV;
2016                 goto err;
2017         }
2018         memcpy(res, r, sizeof(*res));
2019
2020         /* Get the IRQ */
2021         dd->irq = platform_get_irq(pdev, 0);
2022         if (dd->irq < 0) {
2023                 err = dd->irq;
2024                 goto err;
2025         }
2026
2027         /* Only OMAP2/3 can be non-DT */
2028         dd->pdata = &omap_sham_pdata_omap2;
2029
2030 err:
2031         return err;
2032 }
2033
2034 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
2035                              char *buf)
2036 {
2037         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2038
2039         return sprintf(buf, "%d\n", dd->fallback_sz);
2040 }
2041
2042 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
2043                               const char *buf, size_t size)
2044 {
2045         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2046         ssize_t status;
2047         long value;
2048
2049         status = kstrtol(buf, 0, &value);
2050         if (status)
2051                 return status;
2052
2053         /* HW accelerator only works with buffers > 9 */
2054         if (value < 9) {
2055                 dev_err(dev, "minimum fallback size 9\n");
2056                 return -EINVAL;
2057         }
2058
2059         dd->fallback_sz = value;
2060
2061         return size;
2062 }
2063
2064 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2065                               char *buf)
2066 {
2067         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2068
2069         return sprintf(buf, "%d\n", dd->queue.max_qlen);
2070 }
2071
2072 static ssize_t queue_len_store(struct device *dev,
2073                                struct device_attribute *attr, const char *buf,
2074                                size_t size)
2075 {
2076         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2077         ssize_t status;
2078         long value;
2079         unsigned long flags;
2080
2081         status = kstrtol(buf, 0, &value);
2082         if (status)
2083                 return status;
2084
2085         if (value < 1)
2086                 return -EINVAL;
2087
2088         /*
2089          * Changing the queue size in fly is safe, if size becomes smaller
2090          * than current size, it will just not accept new entries until
2091          * it has shrank enough.
2092          */
2093         spin_lock_irqsave(&dd->lock, flags);
2094         dd->queue.max_qlen = value;
2095         spin_unlock_irqrestore(&dd->lock, flags);
2096
2097         return size;
2098 }
2099
2100 static DEVICE_ATTR_RW(queue_len);
2101 static DEVICE_ATTR_RW(fallback);
2102
2103 static struct attribute *omap_sham_attrs[] = {
2104         &dev_attr_queue_len.attr,
2105         &dev_attr_fallback.attr,
2106         NULL,
2107 };
2108
2109 static struct attribute_group omap_sham_attr_group = {
2110         .attrs = omap_sham_attrs,
2111 };
2112
2113 static int omap_sham_probe(struct platform_device *pdev)
2114 {
2115         struct omap_sham_dev *dd;
2116         struct device *dev = &pdev->dev;
2117         struct resource res;
2118         dma_cap_mask_t mask;
2119         int err, i, j;
2120         u32 rev;
2121
2122         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2123         if (dd == NULL) {
2124                 dev_err(dev, "unable to alloc data struct.\n");
2125                 err = -ENOMEM;
2126                 goto data_err;
2127         }
2128         dd->dev = dev;
2129         platform_set_drvdata(pdev, dd);
2130
2131         INIT_LIST_HEAD(&dd->list);
2132         spin_lock_init(&dd->lock);
2133         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2134         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2135
2136         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2137                                omap_sham_get_res_pdev(dd, pdev, &res);
2138         if (err)
2139                 goto data_err;
2140
2141         dd->io_base = devm_ioremap_resource(dev, &res);
2142         if (IS_ERR(dd->io_base)) {
2143                 err = PTR_ERR(dd->io_base);
2144                 goto data_err;
2145         }
2146         dd->phys_base = res.start;
2147
2148         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2149                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
2150         if (err) {
2151                 dev_err(dev, "unable to request irq %d, err = %d\n",
2152                         dd->irq, err);
2153                 goto data_err;
2154         }
2155
2156         dma_cap_zero(mask);
2157         dma_cap_set(DMA_SLAVE, mask);
2158
2159         dd->dma_lch = dma_request_chan(dev, "rx");
2160         if (IS_ERR(dd->dma_lch)) {
2161                 err = PTR_ERR(dd->dma_lch);
2162                 if (err == -EPROBE_DEFER)
2163                         goto data_err;
2164
2165                 dd->polling_mode = 1;
2166                 dev_dbg(dev, "using polling mode instead of dma\n");
2167         }
2168
2169         dd->flags |= dd->pdata->flags;
2170
2171         pm_runtime_use_autosuspend(dev);
2172         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2173
2174         dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2175
2176         pm_runtime_enable(dev);
2177         pm_runtime_irq_safe(dev);
2178
2179         err = pm_runtime_get_sync(dev);
2180         if (err < 0) {
2181                 dev_err(dev, "failed to get sync: %d\n", err);
2182                 goto err_pm;
2183         }
2184
2185         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2186         pm_runtime_put_sync(&pdev->dev);
2187
2188         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2189                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2190                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2191
2192         spin_lock(&sham.lock);
2193         list_add_tail(&dd->list, &sham.dev_list);
2194         spin_unlock(&sham.lock);
2195
2196         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2197                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2198                         struct ahash_alg *alg;
2199
2200                         alg = &dd->pdata->algs_info[i].algs_list[j];
2201                         alg->export = omap_sham_export;
2202                         alg->import = omap_sham_import;
2203                         alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2204                                               BUFLEN;
2205                         err = crypto_register_ahash(alg);
2206                         if (err)
2207                                 goto err_algs;
2208
2209                         dd->pdata->algs_info[i].registered++;
2210                 }
2211         }
2212
2213         err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
2214         if (err) {
2215                 dev_err(dev, "could not create sysfs device attrs\n");
2216                 goto err_algs;
2217         }
2218
2219         return 0;
2220
2221 err_algs:
2222         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2223                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2224                         crypto_unregister_ahash(
2225                                         &dd->pdata->algs_info[i].algs_list[j]);
2226 err_pm:
2227         pm_runtime_disable(dev);
2228         if (!dd->polling_mode)
2229                 dma_release_channel(dd->dma_lch);
2230 data_err:
2231         dev_err(dev, "initialization failed.\n");
2232
2233         return err;
2234 }
2235
2236 static int omap_sham_remove(struct platform_device *pdev)
2237 {
2238         struct omap_sham_dev *dd;
2239         int i, j;
2240
2241         dd = platform_get_drvdata(pdev);
2242         if (!dd)
2243                 return -ENODEV;
2244         spin_lock(&sham.lock);
2245         list_del(&dd->list);
2246         spin_unlock(&sham.lock);
2247         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2248                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2249                         crypto_unregister_ahash(
2250                                         &dd->pdata->algs_info[i].algs_list[j]);
2251         tasklet_kill(&dd->done_task);
2252         pm_runtime_disable(&pdev->dev);
2253
2254         if (!dd->polling_mode)
2255                 dma_release_channel(dd->dma_lch);
2256
2257         sysfs_remove_group(&dd->dev->kobj, &omap_sham_attr_group);
2258
2259         return 0;
2260 }
2261
2262 #ifdef CONFIG_PM_SLEEP
2263 static int omap_sham_suspend(struct device *dev)
2264 {
2265         pm_runtime_put_sync(dev);
2266         return 0;
2267 }
2268
2269 static int omap_sham_resume(struct device *dev)
2270 {
2271         int err = pm_runtime_get_sync(dev);
2272         if (err < 0) {
2273                 dev_err(dev, "failed to get sync: %d\n", err);
2274                 return err;
2275         }
2276         return 0;
2277 }
2278 #endif
2279
2280 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2281
2282 static struct platform_driver omap_sham_driver = {
2283         .probe  = omap_sham_probe,
2284         .remove = omap_sham_remove,
2285         .driver = {
2286                 .name   = "omap-sham",
2287                 .pm     = &omap_sham_pm_ops,
2288                 .of_match_table = omap_sham_of_match,
2289         },
2290 };
2291
2292 module_platform_driver(omap_sham_driver);
2293
2294 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2295 MODULE_LICENSE("GPL v2");
2296 MODULE_AUTHOR("Dmitry Kasatkin");
2297 MODULE_ALIAS("platform:omap-sham");